PEREGRINE PE3239EK

Product Specification
PE3239
2.2 GHz UltraCMOS™ Integer-N PLL
for Low Phase Noise Applications
Product Description
Features
Peregrine’s PE3239 is a high performance integer-N PLL
capable of frequency synthesis up to 2.2 GHz. The
superior phase noise performance of the PE3239 is ideal
for applications such as wireless local loop basestations,
LMDS systems and other demanding terrestrial systems.
• 2.2 GHz operation
• ÷10/11 dual modulus prescaler
• Internal phase detector with
charge pump
The PE3239 features a 10/11 dual modulus prescaler,
counters, phase detector and a charge pump as shown in
Figure 1. Counter values are programmable through a
three wire serial interface.
• Serial programmable
• Low power— 20 mA at 3 V
The PE3239 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the
performance of GaAs with the economy and integration of
conventional CMOS.
• Ultra-low phase noise
• Available in 20-lead TSSOP
Figure 1. Block Diagram
Fin
Fin
Prescaler
10/11
Main
Counter
13
Sdata
Primary
20-bit
20
Latch
Secondary
20-bit
Latch
Phase
Detector
20
20
6
fr
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PD_U
PD_D
Charge
Pump
CP
6
R Counter
©2006 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 12
PE3239
Product Specification
Figure 2. Pin Configuration (Top View)
Figure 3. Package Type
20-lead TSSOP
VDD
1
20
fr
Enh
2
19
GND
S_WR
3
18
N/C
Sdata
4
17
CP
Sclk
5
16
VDD
GND
6
15
Dout
FSELS
7
14
LD
E_WR
8
13
Cext
VDD
9
12
GND
Fin 10
11
Fin
Table 1. Pin Descriptions
Pin No.
Pin Name
Type
Description
1
VDD
(Note 1)
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required.
2
Enh
Input
Enhancement mode. When asserted low (“0”), enhancement register bits are functional. Internal 70 kΩ
pull-up resistor.
3
S_WR
Input
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register data are
transferred to the secondary register on S_WR rising edge.
4
Sdata
Input
Binary serial data input. Input data entered MSB first.
5
Sclk
Input
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit
enhancement register (E_WR “high”) on the rising edge of Sclk.
6
GND
7
FSELS
Input
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal
counters. Internal 70 kΩ pull-down resistor.
8
E_WR
Input
Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the
enhancement register on the rising edge of Sclk. Internal 70 kΩ pull-down resistor.
9
VDD
(Note 1)
Same as pin 1.
10
Fin
Input
Prescaler input from the VCO. Max frequency input is 2.2 GHz.
11
Fin
Input
Prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be
connected in series with a 50 Ω resistor to the ground plane.
12
GND
13
Cext
Output
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor. Connecting Cext to
an external capacitor will low pass filter the input to the inverting amplifier used for driving LD.
14
LD
Output
Lock detect is an open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance,
otherwise LD is a logic low (“0”).
15
Dout
Output
Data out function, Dout, enabled in enhancement mode.
16
VDD
(Note 1)
Same as pin 1.
Ground.
Ground.
©2006 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 12
Document No. 70-0047-02 │ UltraCMOS™ RFIC Solutions
PE3239
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
Pin Name
17
CP
Output
Charge pump current is sourced when fc leads fp and sinked when fc lags fp.
18
NC
Output
No connection.
19
GND
20
fr
Note 1:
Type
Description
Ground.
Input
Reference frequency input.
VDD pins 1, 9, and 16 are connected by diodes and must be supplied with the same positive voltage level.
Electrostatic Discharge (ESD) Precautions
Table 2. Absolute Maximum Ratings
Symbol
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in Table 4.
Parameter/Conditions
Min
Max
Units
Supply voltage
-0.3
4.0
V
VI
Voltage on any input
-0.3
VDD +
0.3
V
II
DC into any input
-10
+10
mA
IO
DC into any output
-10
+10
mA
Latch-Up Avoidance
Storage temperature range
-65
150
°C
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Min
Max
Units
VDD
Tstg
Table 3. Operating Ratings
Symbol
Parameter/Conditions
VDD
Supply voltage
2.85
3.15
V
TA
Operating ambient
temperature range
-40
85
°C
Table 4. ESD Ratings
Symbol
Parameter/Conditions
Level
Units
VESD
ESD voltage human body model
1000
V
Note 1:
Periodically sampled, not 100% tested. Tested per
MIL-STD-883, M3015 C2
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©2006 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 12
PE3239
Product Specification
Table 5. DC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
IDD
Parameter
Operational supply current;
Prescaler enabled
Conditions
Min
VDD = 2.85 to 3.15 V
Typ
Max
Units
20
26
mA
Digital Inputs: S_WR, Sdata, Sclk
VIH
High level input voltage
VDD = 2.85 to 3.15 V
VIL
Low level input voltage
VDD = 2.85 to 3.15 V
IIH
High level input current
VIH = VDD = 3.15 V
IIL
Low level input current
VIL = 0, VDD = 3.15 V
-1
µA
0.7 x VDD
V
0.7 x VDD
V
0.3 x VDD
V
+1
µA
Digital Inputs: Enh (contains a 70 kΩ pull-up resistor)
VIH
High level input voltage
VDD = 2.85 to 3.15 V
VIL
Low level input voltage
VDD = 2.85 to 3.15 V
IIH
High level input current
VIH = VDD = 3.15 V
IIL
Low level input current
VIL = 0, VDD = 3.15 V
0.3 x VDD
V
+1
µA
-100
µA
0.7 x VDD
V
Digital Inputs: FSELS, E_WR (contains a 70 kΩ pull-down resistor)
VIH
High level input voltage
VDD = 2.85 to 3.15 V
VIL
Low level input voltage
VDD = 2.85 to 3.15 V
IIH
High level input current
VIH = VDD = 3.15 V
IIL
Low level input current
VIL = 0, VDD = 3.15 V
0.3 x VDD
V
+100
µA
µA
-1
Reference Divider input: fr
IIHR
High level input current
VIH = VDD = 3.15 V
IILR
Low level input current
VIL = 0, VDD = 3.15 V
+100
µA
µA
-100
Counter output: Dout
VOLD
Output voltage LOW
Iout = 6 mA
VOHD
Output voltage HIGH
Iout = -3 mA
0.4
VDD - 0.4
V
V
Lock detect outputs: (Cext, LD)
VOLC
Output voltage LOW, Cext
Iout = 0.1 mA
VOHC
Output voltage HIGH, Cext
Iout = -0.1 mA
VOLLD
Output voltage LOW, LD
Iout = 1 mA
0.4
VDD - 0.4
V
V
0.4
V
Charge Pump output: CP
ICP – Source
Drive current
VCP = VDD / 2
-2.6
-2
-1.4
mA
ICP – Sink
Drive current
VCP = VDD / 2
1.4
2
2.6
mA
Leakage current
1.0 V < VCP < VDD – 1.0 V
-1
1
µA
Sink vs. source mismatch
VCP = VDD / 2, TA = 25° C
15
%
Output current magnitude variation vs. voltage
1.0 V < VCP < VDD – 1.0 V TA = 25° C
15
%
ICPL
ICP – Source
VS. 1CP Sink
ICP VS. VCP
©2006 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 12
Document No. 70-0047-02 │ UltraCMOS™ RFIC Solutions
PE3239
Product Specification
Table 6. AC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Max
Units
10
MHz
Control Interface and Latches (see Figures 6, 7, 8)
fClk
Serial data clock frequency
tClkH
Serial clock HIGH time
30
ns
tClkL
Serial clock LOW time
30
ns
tDSU
Sdata set-up time to Sclk rising edge
10
ns
tDHLD
Sdata hold time after Sclk rising edge
10
ns
tPW
S_WR pulse width
30
ns
tCWR
Sclk rising edge to S_WR rising edge
30
ns
Sclk falling edge to E_WR transition
30
ns
S_WR falling edge to Sclk rising edge
30
ns
E_WR transition to Sclk rising edge
30
ns
tCE
tWRC
tEC
(Note 1)
Main Divider (Including Prescaler)
Fin
Operating frequency
PFin
Input level range
External AC coupling
200
2200
MHz
-5
5
dBm
20
220
MHz
-5
5
dBm
100
MHz
Main Divider (Prescaler Bypassed)
Fin
Operating frequency
PFin
Input level range
External AC coupling
Reference Divider
fr
Operating frequency
(Note 3)
Pfr
Reference input power (Note 2)
Single ended input
Comparison frequency
(Note 3)
-2
dBm
Phase Detector
fc
20
MHz
100 Hz Offset
-75
dBc/Hz
1 kHz Offset
-85
dBc/Hz
SSB Phase Noise (Fin = 1.3 GHz, fr = 10 MHz, fc = 1.25 MHz, LBW = 70 kHz, V DD = 3.0 V, Temp = -40° C)
Note 1:
Note 2:
Note 3:
fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk
specification.
CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum
phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns.
Parameter is guaranteed through characterization only and is not tested.
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©2006 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 12
PE3239
Product Specification
Typical Performance Data (VDD = 3.0 V, TA = 25°C)
Figure 4. Typical RF Input Sensitivity
0
-5
(dBm)
-10
-15
-20
-25
-30
0
500
1000
1500
2000
2500
3000
Frequency (MHz)
Figure 5. Typical Phase Noise Performance
-60
Frequency = 1300 MHz
Reference = 10 MHz
Loop Band Width = 30 kHz
Comparison Frequency = 1.25 MHz
-70
(dBc/Hz)
-80
-90
-100
-110
-120
-130
100
1000
10000
100000
1000000
Frequency Offset (Hz)
©2006 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 12
Document No. 70-0047-02 │ UltraCMOS™ RFIC Solutions
PE3239
Product Specification
Functional Description
The PE3239 consists of a prescaler, counters, a
phase detector, charge pump and control logic.
The dual modulus prescaler divides the VCO
frequency by either 10 or 11, depending on the
value of the modulus select. Counters “R” and “M”
divide the reference and prescaler output,
respectively, by integer values stored in a 20-bit
register. An additional counter (“A”) is used in
the modulus select logic.
The phase-frequency detector generates up and
down frequency control signals which direct the
charge pump operation. The control logic includes
a selectable chip interface. Data is written into the
internal registers via the three wire serial bus.
There are also various operational and test modes
and a lock detect output.
Figure 6. Functional Block Diagram
R Counter
(6-bit)
fr
Sdata
Control
Pins
Control
Logic
fc
PD_U
R(5:0)
Phase
Detector
M(8:0)
PD_D
Charge
Pump
CP
A(3:0)
LD
Cext
Modulus
Select
Fin
Fin
10/11
Prescaler
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M Counter
(9-bit)
fp
©2006 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 12
PE3239
Product Specification
Main Counter Chain
Normal Operating Mode
Setting the Pre_en control bit “low” enables the
÷10/11 prescaler. The main counter chain then
divides the RF input frequency (Fin) by an integer
derived from the values in the “M” and “A”
counters.
In this mode, the output from the main counter
chain (fp) is related to the VCO frequency (Fin) by
the following equation:
fp = Fin / [10 x (M + 1) + A]
where A ≤ M + 1, 1 ≤ M ≤ 511
(1)
When the loop is locked, Fin is related to the
reference frequency (fr) by the following equation:
Fin = [10 x (M + 1) + A] x (fr / (R+1))
where A ≤ M + 1, 1 ≤ M ≤ 511
(2)
A consequence of the upper limit on A is that Fin
must be greater than or equal to 90 x (fr / (R+1)) to
obtain contiguous channels. The A counter can
accept values as high as 15, but in typical
operation it will cycle from 0 to 9 between
increments in M.
Programming the M counter with the minimum
allowed value of “1” will result in a minimum M
counter divide ratio of “2”.
Prescaler Bypass Mode
Setting the frequency control register bit Pre_en
“high” allows Fin to bypass the ÷10/11 prescaler.
In this mode, the prescaler and A counter are
powered down, and the input VCO frequency is
divided by the M counter directly. The following
equation relates Fin to the reference frequency fr:
Fin = (M + 1) x (fr / (R+1))
where 1 ≤ M ≤ 511
Note that programming R with “0” will pass the
reference frequency (fr) directly to the phase
detector.
Register Programming
Serial Interface Mode
While the E_WR input is “low” and the S_WR
input is “low”, serial input data (Sdata input), B0
to B19, are clocked serially into the primary
register on the rising edge of Sclk, MSB (B0)
first. The contents from the primary register are
transferred into the secondary register on the
rising edge of either S_WR according to the
timing diagrams shown in Figure 7. Data are
transferred to the counters as shown in Table 7
on page 9.
The double buffering provided by the primary
and secondary registers allows for “ping-pong”
counter control using the FSELS input. When
FSELS is “high”, the primary register contents
set the counter inputs. When FSELS is “low”, the
secondary register contents are utilized.
While the E_WR input is “high” and the S_WR
input is “low”, serial input data (Sdata input), B0
to B7, are clocked serially into the enhancement
register on the rising edge of Sclk, MSB (B0)
first. The enhancement register is double
buffered to prevent inadvertent control changes
during serial loading, with buffer capture of the
serially entered data performed on the falling
edge of E_WR according to the timing diagram
shown in Figure 7. After the falling edge of
E_WR, the data provide control bits as shown in
Table 8 on page 9 will have their bit functionality
enabled by asserting the Enh input “low”.
(3)
Reference Counter
The reference counter chain divides the reference
frequency fr down to the phase detector
comparison frequency fc.
The output frequency of the 6-bit R Counter is
related to the reference frequency by the following
equation:
fc = fr / (R + 1)
where 0 ≤ R ≤ 63
©2006 Peregrine Semiconductor Corp. All rights reserved.
Page 8 of 12
(4)
Document No. 70-0047-02 │ UltraCMOS™ RFIC Solutions
PE3239
Product Specification
Table 7. Primary Register Programming
Interface Mode
Enh
R5
R4
M8
M7
Pre_en
M6
M5
M4
M3
M2
M1
M0
R3
R2
R1
R0
A3
A2
A1
A0
Serial*
1
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.
MSB (first in)
(last in) LSB
Table 8. Enhancement Register Programming
Interface
Mode
Enh
Reserved
Reserved
fp Output
Power
down
Counter
load
MSEL
output
fc output
Reserved
Serial*
0
B0
B1
B2
B3
B4
B5
B6
B7
*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
MSB (first in)
(last in) LSB
Figure 7. Serial Interface Mode Timing Diagram
Sdata
E_WR
tEC
tCE
Sclk
S_WR
tDSU
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tDHLD
tClkH
tClkL
tCWR
tPW
tWRC
©2006 Peregrine Semiconductor Corp. All rights reserved.
Page 9 of 12
PE3239
Product Specification
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 9. Enhancement Register Bit Functionality
Bit Function
Description
Bit 0
Reserved**
Bit 1
Reserved**
Bit 2
fp output
Bit 3
Power down
Power down of all functions except programming interface.
Bit 4
Counter load
Immediate and continuous load of counter programming.
Bit 5
MSEL output
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Bit 6
fc output
Bit 7
Reserved**
Drives the M counter output onto the Dout output.
Drives the reference counter output onto the Dout output
** Program to 0
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (fp) and the reference
counter (fc). It has two outputs, namely PD_U,
and PD_D. If the divided VCO leads the divided
reference in phase or frequency (fp leads fc),
PD_D pulses “low”. If the divided reference leads
the divided VCO in phase or frequency (fc leads
fp), PD_U pulses “low”. The width of either pulse
is directly proportional to phase offset between the
two input signals, fp and fc.
The signals from the phase detector couple
directly to a charge pump. PD_U controls a
current source at pin CP with constant amplitude
and pulse duration approximately the same as
PD_U. PD_D similarly drives a current sink at pin
CP. The current pulses from pin CP are low pass
filtered externally and then connected to the VCO
tune voltage. PD_U pulses result in a current
source, which increases the VCO frequency and
PD_D results in a current sink, which decreases
VCO frequency when using a positive Kv VCO.
A lock detect output, LD is also provided, via the
pin Cext. Cext is the logical “NAND” of PD_U and
PD_D waveforms, which is driven through a series
2 kohm resistor. Connecting Cext to an external
shunt capacitor provides low pass filtering of this
signal. Cext also drives the input of an internal
inverting comparator with an open drain output.
Thus LD is an “AND” function of PD_U and PD_D.
Figure 8. Typical PE3239 Loop Filter Application Example
Charge
Pump
To VCO
Tune
R
C2
C1
©2006 Peregrine Semiconductor Corp. All rights reserved.
Page 10 of 12
Document No. 70-0047-02 │ UltraCMOS™ RFIC Solutions
PE3239
Product Specification
Figure 9. Package Drawing
20-lead TSSOP
TOP VIEW
0.65BSC
20
19
18
17
16
15
14
13
12
11
12o REF
3.20 2X
0.20
R 0.90 MIN
4.40±0.10
Ø1.00±0.10
R 0.90 MIN
GAGE
PLANE
1.00
0.25
-B1
1.00
2
3
4
5
6
7
8
9
10
12o REF
.20 C B A
0o
8o
+.15
0.60 -.10
1.0 REF
0.325
-A-
6.50±0.10
0.90±0.05
1.10 MAX
-C0.10 C
0.30 MAX
0.10
0.10±0.05
6.40
CB A
SIDE VIEW
FRONT VIEW
Table 10. Ordering Information
Order Code
Part Marking
Description
Package
Shipping Method
3239-11
PE3239
PE3239-20TSSOP-74A
20-lead TSSOP
74 units / Tube
3239-12
PE3239
PE3239-20TSSOP-2000C
20-lead TSSOP
2000 units / T&R
3239-00
PE3239EK
PE3239-20TSSOP-EVAL KIT
Evaluation Board
1 / Box
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©2006 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 12
PE3239
Product Specification
Sales Offices
The Americas
North Asia Pacific
Peregrine Semiconductor Corporation
Peregrine Semiconductor K.K.
9450 Carroll Park Drive
San Diego, CA 92121
Tel 858-731-9400
Fax 858-731-9499
5A-5, 5F Imperial Tower
1-1-1 Uchisaiwaicho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel: +81-3-3502-5211
Fax: +81-3-3502-5213
Europe
Peregrine Semiconductor, Korea
Peregrine Semiconductor Europe
#B-2402, Kolon Tripolis, #210
Geumgok-dong, Bundang-gu, Seongnam-si
Gyeonggi-do, 463-480 S. Korea
Tel: +82-31-728-4300
Fax: +82-31-728-4305
Bâtiment Maine
13-15 rue des Quatre Vents
F-92380 Garches, France
Tel: +33-1-47-41-91-73
Fax : +33-1-47-41-91-73
South Asia Pacific
Space and Defense Products
Peregrine Semiconductor, China
Americas:
Tel: 505-881-0438
Fax: 505-881-0443
Europe, Asia Pacific:
180 Rue Jean de Guiramand
13852 Aix-En-Provence cedex 3, France
Tel: +33(0) 4 4239 3361
Fax: +33(0) 4 4239 7227
Shanghai, 200040, P.R. China
Tel: +86-21-5836-8276
Fax: +86-21-5836-7652
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
Preliminary Specification
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
©2006 Peregrine Semiconductor Corp. All rights reserved.
Page 12 of 12
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS and HaRP are trademarks of Peregrine
Semiconductor Corp.
Document No. 70-0047-02 │ UltraCMOS™ RFIC Solutions