PRODUCT SPECIFICATION PE3339 3.0 GHz Integer-N PLL for Low Phase Noise Applications Product Description Peregrine’s PE3339 is a high performance integer-N PLL capable of frequency synthesis up to 3.0 GHz. The superior phase noise performance of the PE3339 makes it ideal for applications such as wireless local loop basestations, LMDS systems and other demanding terrestrial systems. Features • 3.0 GHz operation • ÷10/11 dual modulus prescaler • Internal phase detector with charge pump • Serial programmable • Low power ⎯ 23 mA at 3 V • Ultra-low phase noise • Available in 20-lead TSSOP The PE3339 features a 10/11 dual modulus prescaler, counters, phase detector and a charge pump as shown in Figure 1. Counter values are programmable through a three wire serial interface. Fabricated in Peregrine’s patented UTSi® (Ultra Thin Silicon) CMOS technology, the PE3339 offers excellent RF performance with the economy and integration of conventional CMOS. Figure 1. Block Diagram Fin Fin Prescaler 10/11 Main Counter 13 Sdata Primary 20-bit 20 Latch Secondary 20-bit Latch PD_U 20 PEREGRINE SEMICONDUCTOR CORP. ® | CP PD_D 6 fr Charge Pump Phase Detector 20 6 R Counter http://www.psemi.com Copyright © Peregrine Semiconductor Corp. 2004 Page 1 of 12 PE3339 Advance Information Figure 2. Pin Configuration VDD 1 20 fr Enh 2 19 GND S_WR 3 18 N/C Sdata 4 17 CP Sclk 5 16 VDD GND 6 15 Dout FSELS 7 14 LD E_WR 8 13 Cext VDD 9 12 GND Fin 10 11 Fin Table 1. Pin Descriptions Pin No. Pin Name Type Description 1 VDD (Note 1) Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required. 2 Enh Input Enhancement mode. When asserted low (“0”), enhancement register bits are functional. Internal 70 kΩ pull-up resistor. 3 S_WR Input Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register data are transferred to the secondary register on S_WR rising edge. 4 Sdata Input Binary serial data input. Input data entered MSB first. 5 Sclk Input Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk. 6 GND 7 FSELS Input Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal counters. Internal 70 kΩ pull-down resistor. 8 E_WR Input Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the enhancement register on the rising edge of Sclk. Internal 70 kΩ pull-down resistor. 9 VDD (Note 1) Same as pin 1. 10 Fin Input Prescaler input from the VCO. Max frequency input is 3.0 GHz. 11 Fin Input Prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be connected in series with a 50 Ω resistor to the ground plane. 12 GND 13 Cext Output Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor. Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD. 14 LD Output, OD Lock detect is an open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance, otherwise LD is a logic low (“0”). 15 Dout Output Data out function, Dout, enabled in enhancement mode. 16 VDD (Note 1) Same as pin 1. Ground. Ground. Copyright © Peregrine Semiconductor Corp. 2004 Page 2 of 12 File No. 70/0048~02A | UTSi ® CMOS RFIC SOLUTIONS PE3339 Advance Information Pin No. Pin Name 17 CP Output Charge pump current is sourced when fc leads fp and sinked when fc lags fp. 18 NC Output No connection. 19 GND 20 fr Note 1: Type Description Ground. Input Reference frequency input. VDD pins 1, 9, and 16 are connected by diodes and must be supplied with the same positive voltage level. Table 2. Absolute Maximum Ratings Symbol Electrostatic Discharge (ESD) Precautions Parameter/Conditions Min Max Units Supply voltage -0.3 4.0 V VI Voltage on any input -0.3 VDD + 0.3 V II DC into any input -10 +10 mA IO DC into any output -10 +10 mA Storage temperature range -65 150 °C VDD Tstg Latch-Up Avoidance Unlike conventional CMOS devices, UTSi CMOS devices are immune to latch-up. Table 3. Operating Ratings Symbol When handling this UTSi device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 4. Parameter/Conditions Min Max Units VDD Supply voltage 2.85 3.15 V TA Operating ambient temperature range -40 85 °C Table 4. ESD Ratings Symbol VESD Note 1: Parameter/Conditions ESD voltage human body model (Note 1) Level Units 1000 V Periodically sampled, not 100% tested. Tested per MILSTD-883, M3015 C2 PEREGRINE SEMICONDUCTOR CORP. ® | http://www.psemi.com Copyright © Peregrine Semiconductor Corp. 2004 Page 3 of 12 PE3339 Advance Information Table 5. DC Characteristics VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol IDD Parameter Operational supply current; Prescaler enabled Conditions Min Typ Max Units 23 35 mA VDD = 2.85 to 3.15 V Digital Inputs: S_WR, Sdata, Sclk VIH High level input voltage VDD = 2.85 to 3.15 V 0.7 x VDD VIL Low level input voltage VDD = 2.85 to 3.15 V IIH High level input current VIH = VDD = 3.15 V IIL Low level input current VIL = 0, VDD = 3.15 V -1 0.7 x VDD V 0.3 x VDD V +1 µA µA Digital Inputs: Enh (contains a 70 kΩ pull-up resistor) VIH High level input voltage VDD = 2.85 to 3.15 V VIL Low level input voltage VDD = 2.85 to 3.15 V IIH High level input current VIH = VDD = 3.15 V IIL Low level input current VIL = 0, VDD = 3.15 V -100 0.7 x VDD V 0.3 x VDD V +1 µA µA Digital Inputs: FSELS, E_WR (contains a 70 kΩ pull-down resistor) VIH High level input voltage VDD = 2.85 to 3.15 V VIL Low level input voltage VDD = 2.85 to 3.15 V IIH High level input current VIH = VDD = 3.15 V IIL Low level input current VIL = 0, VDD = 3.15 V V 0.3 x VDD V +100 µA µA -1 Reference Divider input: fr IIHR High level input current VIH = VDD = 3.15 V IILR Low level input current VIL = 0, VDD = 3.15 V +100 µA µA -100 Counter output: Dout VOLD Output voltage LOW Iout = 6 mA VOHD Output voltage HIGH Iout = -3 mA 0.4 VDD - 0.4 V V Lock detect outputs: (Cext, LD) VOLC Output voltage LOW, Cext Iout = 0.1 mA VOHC Output voltage HIGH, Cext Iout = -0.1 mA VOLLD Output voltage LOW, LD Iout = 1 mA 0.4 VDD - 0.4 V V 0.4 V Charge Pump output: CP ICP – Source Drive current VCP = VDD / 2 -2.6 -2 -1.4 mA ICP – Sink Drive current VCP = VDD / 2 1.4 2 2.6 mA Leakage current 1.0 V < VCP < VDD – 1.0 V -1 1 µA Sink vs. source mismatch VCP = VDD / 2, TA = 25° C 15 % Output current magnitude variation vs. voltage 1.0 V < VCP < VDD – 1.0 V TA = 25° C 15 % ICPL ICP – Source VS. ICP Sink ICP VS. VCP Copyright © Peregrine Semiconductor Corp. 2004 Page 4 of 12 File No. 70/0048~02A | UTSi ® CMOS RFIC SOLUTIONS PE3339 Advance Information Table 6. AC Characteristics VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol Parameter Conditions Min Max Units 10 MHz Control Interface and Latches (see Figures 3, 4, 5) fClk Serial data clock frequency tClkH Serial clock HIGH time 30 ns tClkL Serial clock LOW time 30 ns tDSU Sdata set-up time to Sclk rising edge 10 ns tDHLD tPW tCWR tCE tWRC tEC (Note 1) Sdata hold time after Sclk rising edge 10 ns S_WR pulse width 30 ns ns Sclk rising edge to S_WR rising edge 30 Sclk falling edge to E_WR transition 30 ns S_WR falling edge to Sclk rising edge 30 ns E_WR transition to Sclk rising edge 30 ns Main Divider (Including Prescaler) Fin Operating frequency PFin Input level range External AC coupling 500 3000 MHz -5 5 dBm 50 300 MHz -5 5 dBm 100 MHz Main Divider (Prescaler Bypassed) Fin Operating frequency PFin Input level range External AC coupling fr Operating frequency (Note 3) Pfr Reference input power (Note 2) Single ended input Comparison frequency (Note 3) Reference Divider -2 dBm Phase Detector fc 20 MHz SSB Phase Noise (Fin = 1.3 GHz, fr = 10 MHz, fc = 1.25 MHz, LBW = 70 kHz, VDD = 3.0 V, Temp = -40° C) 100 Hz Offset -75 dBc/Hz 1 kHz Offset -85 dBc/Hz Note 1: fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification. Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum phase noise performance, the reference input falling edge rate should be faster than 80mV/ns. Note 3: Parameter is guaranteed through characterization only and is not tested. PEREGRINE SEMICONDUCTOR CORP. ® | http://www.psemi.com Copyright © Peregrine Semiconductor Corp. 2004 Page 5 of 12 PE3339 Advance Information Functional Description The PE3339 consists of a prescaler, counters, a phase detector, charge pump and control logic . The dual modulus prescaler divides the VCO frequency by either 10 or 11, depending on the value of the modulus select. Counters “R” and “M” divide the reference and prescaler output, respectively, by integer values stored in a 20-bit register. An additional counter (“A”) is used in the modulus select logic. The phase-frequency detector generates up and down frequency control signals which direct the charge pump operation. The control logic includes a selectable chip interface. Data is written into the internal registers via the three wire serial bus. There are also various operational and test modes and a lock detect output. Figure 3. Functional Block Diagram R Counter (6-bit) fr Sdata Control Pins fc PD_U R(5:0) Control Logic Phase Detector M(8:0) PD_D Charge Pump CP A(3:0) LD Cext Modulus Select Fin Fin Copyright © Peregrine Semiconductor Corp. 2004 Page 6 of 12 10/11 Prescaler M Counter (9-bit) fp File No. 70/0048~02A | UTSi ® CMOS RFIC SOLUTIONS PE3339 Advance Information Main Counter Chain Note that programming R with “0” will pass the reference frequency (fr) directly to the phase detector. Normal Operating Mode Setting the Pre_en control bit “low” enables the ÷10/11 prescaler. The main counter chain then divides the RF input frequency (Fin) by an integer derived from the values in the “M” and “A” counters. In this mode, the output from the main counter chain (fp) is related to the VCO frequency (Fin) by the following equation: fp = Fin / [10 x (M + 1) + A] where A ≤ M + 1, 1 ≤ M ≤ 511 (1) When the loop is locked, Fin is related to the reference frequency (fr) by the following equation: Fin = [10 x (M + 1) + A] x (fr / (R+1)) where A ≤ M + 1, 1 ≤ M ≤ 511 (2) A consequence of the upper limit on A is that Fin must be greater than or equal to 90 x (fr / (R+1)) to obtain contiguous channels. The A counter can accept values as high as 15, but in typical operation it will cycle from 0 to 9 between increments in M. Programming the M counter with the minimum allowed value of “1” will result in a minimum M counter divide ratio of “2”. Prescaler Bypass Mode Setting the frequency control register bit Pre_en “high” allows Fin to bypass the ÷10/11 prescaler. In this mode, the prescaler and A counter are powered down, and the input VCO frequency is divided by the M counter directly. The following equation relates Fin to the reference frequency fr: Fin = (M + 1) x (fr / (R+1)) where 1 ≤ M ≤ 511 (3) Register Programming Serial Interface Mode While the E_WR input is “low” and the S_WR input is “low”, serial input data (Sdata input), B0 to B19, are clocked serially into the primary register on the rising edge of Sclk, MSB (B0) first. The contents from the primary register are transferred into the secondary register on the rising edge of either S_WR according to the timing diagrams shown in Figure 4. Data are transferred to the counters as shown in Table 7 on page 9. The double buffering provided by the primary and secondary registers allows for “ping-pong” counter control using the FSELS input. When FSELS is “high”, the primary register contents set the counter inputs. When FSELS is “low”, the secondary register contents are utilized. While the E_WR input is “high” and the S_WR input is “low”, serial input data (Sdata input), B0 to B7, are clocked serially into the enhancement register on the rising edge of Sclk, MSB (B0) first. The enhancement register is double buffered to prevent inadvertent control changes during serial loading, with buffer capture of the serially entered data performed on the falling edge of E_WR according to the timing diagram shown in Figure 4. After the falling edge of E_WR, the data provide control bits as shown in Table 8 on page 9 will have their bit functionality enabled by asserting the Enh input “low”. Reference Counter The reference counter chain divides the reference frequency fr down to the phase detector comparison frequency fc. The output frequency of the 6-bit R Counter is related to the reference frequency by the following equation: fc = fr / (R + 1) where 0 ≤ R ≤ 63 PEREGRINE SEMICONDUCTOR CORP. ® | (4) http://www.psemi.com Copyright © Peregrine Semiconductor Corp. 2004 Page 7 of 12 PE3339 Advance Information Table 7. Primary Register Programming Interface Mode Enh R5 R4 M8 M7 Serial* 1 B0 B1 B2 B3 Pre_en M6 B4 B5 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3 A2 A1 A0 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 *Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. MSB (first in) (last in) LSB Table 8. Enhancement Register Programming Interface Mode Enh Reserved Reserved fp Output Power down Counter load MSEL output fc output Reserved Serial* 0 B0 B1 B2 B3 B4 B5 B6 B7 *Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge. MSB (first in) (last in) LSB Figure 4. Serial Interface Mode Timing Diagram Sdata E_WR tEC tCE Sclk S_WR tDSU Copyright © Peregrine Semiconductor Corp. 2004 Page 8 of 12 tDHLD tClkH tClkL tCWR File No. 70/0048~02A | tPW tWRC UTSi ® CMOS RFIC SOLUTIONS PE3339 Advance Information Enhancement Register The functions of the enhancement register bits are shown below with all bits active “high”. Table 9. Enhancement Register Bit Functionality Bit Function Bit 0 Reserved** Bit 1 Reserved** Description Bit 2 fp output Bit 3 Power down Drives the M counter output onto the Dout output. Power down of all functions except programming interface. Bit 4 Counter load Immediate and continuous load of counter programming. Bit 5 MSEL output Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output. Bit 6 fc output Bit 7 Reserved** Drives the reference counter output onto the Dout output ** Program to 0 Phase Detector The phase detector is triggered by rising edges from the main Counter (fp) and the reference counter (fc). It has two outputs, namely PD_U, and PD_D. If the divided VCO leads the divided reference in phase or frequency (fp leads fc), PD_D pulses “low”. If the divided reference leads the divided VCO in phase or frequency (fc leads fp), PD_U pulses “low”. The width of either pulse is directly proportional to phase offset between the two input signals, fp and fc. The signals from the phase detector couple directly to a charge pump. PD_U controls a current source at pin CP with constant amplitude and pulse duration approximately the same as PD_U. PD_D similarly drives a current sink at pin CP. The current pulses from pin CP are low pass filtered externally and then connected to the VCO tune voltage. PD_U pulses result in a current source, which increases the VCO frequency and PD_D results in a current sink, which decreases VCO frequency when using a positive Kv VCO. A lock detect output, LD is also provided, via the pin Cext. Cext is the logical “NAND” of PD_U and PD_D waveforms, which is driven through a series 2 kohm resistor. Connecting Cext to an external shunt capacitor provides low pass filtering of this signal. Cext also drives the input of an internal inverting comparator with an open drain output. Thus LD is an “AND” function of PD_U and PD_D. Figure 5. Typical PE3339 Loop Filter Application Example Charge Pump To VCO Tune R C2 C1 PEREGRINE SEMICONDUCTOR CORP. ® | http://www.psemi.com Copyright © Peregrine Semiconductor Corp. 2004 Page 9 of 12 PE3339 Advance Information Figure 6. Package Drawing 20-lead TSSOP (JEDEC MO-153-AC) TOP VIEW 0.65BSC 20 19 18 17 16 15 14 13 12 11 12o REF 3.20 2X 0.20 R 0.90 MIN 4.40±0.10 Ø1.00±0.10 R 0.90 MIN GAGE PLANE 1.00 0.25 -B- 1.00 1 2 3 4 5 6 7 8 9 10 12o REF 0o 8o +.15 0.60 -.10 1.0 REF .20 C B A 0.325 -A6.50±0.10 0.90±0.05 1.10 MAX -C0.10 C 0.30 MAX 0.10 C B A FRONT VIEW Copyright © Peregrine Semiconductor Corp. 2004 Page 10 of 12 0.10±0.05 6.40 SIDE VIEW File No. 70/0048~02A | UTSi ® CMOS RFIC SOLUTIONS PE3339 Advance Information Table 10. Ordering Information Order Code Part Marking Description PE3339-20TSSOP-74A Package 3339-11 PE3339 3339-12 PE3339 PE3339-20TSSOP-200C 20-lead TSSOP 2000 units / T&R 3339-00 PE3339EK PE3339-20TSSOP-EVAL KIT 20-lead TSSOP 1 / Box PEREGRINE SEMICONDUCTOR CORP. ® | http://www.psemi.com 20-lead TSSOP Shipping Method 74 units / Tube Copyright © Peregrine Semiconductor Corp. 2004 Page 11 of 12 PE3339 Advance Information Sales Offices United States Japan Peregrine Semiconductor Corp. 9450 Carroll Park Drive San Diego, CA 92121 Tel 1-858-731-9400 Fax 1-858-731-9499 Peregrine Semiconductor K.K. 5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: (+81)-03-3507-5755 Fax: (+81)-03-3507-5601 Europe Peregrine Semiconductor Europe Bâtiment Maine 13-15 rue des Quatre Vents F- 92380 Garches France Tel (+33)-1-47-41-91-73 Fax (+33)-1-47-41-91-73 For a list of representatives in your area, please refer to our Web site at: http://www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. Peregrine, the Peregrine logotype, Peregrine Semiconductor Corp., and UTSi are registered trademarks of Peregrine Semiconductor Corporation. Copyright © 2004 Peregrine Semiconductor Corp. All rights reserved. Copyright © Peregrine Semiconductor Corp. 2004 Page 12 of 12 File No. 70/0048~02A | UTSi ® CMOS RFIC SOLUTIONS