Product Specification
PE43204
50 Ω RF Digital Attenuator
2-bit; 0, 6, 12, and 18 dB States
Product Description
The PE43204 is a 50Ω, HaRP™-enhanced, high linearity, 2-bit
RF Digital Step Attenuator (DSA) covering an 18 dB
attenuation range in 6 dB steps. With a parallel control
interface, it maintains high attenuation accuracy, fast switching
speed, low insertion loss and low power consumption. This
next generation Peregrine DSA is available in a 3x3 mm 12lead QFN footprint.
Features
• HaRP™-enhanced UltraCMOS™ device
The PE43204 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
• Attenuation: 6, 12, and 18 dB States
• Fast switching speed: Typical 26 ns
• High Linearity: Typical +61 dBm IP3
• Small α-Error
• Best in class 2000 V HBM ESD tolerance
• Parallel Control
• CMOS Compatible
• Packaged in a 12-lead 3x3x0.85 mm QFN
Figure 1. Package Type
12-lead 3x3x0.85 mm QFN Package
Figure 2. Functional Schematic Diagram
Switched Attenuator Array
RF Input
Parallel Control
RF Output
2
Control Logic
Interface
Document No. 70-0257-02 │ www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 8
PE43204
Product Specification
Table 1. Electrical Specifications @ +25°C, VDD = 3.3 V
Parameter
Test Conditions
Min
Typical
Frequency Range
Max
Units
50 - 3000
Attenuation Range
6 dB,12 dB and 18 dB steps
0 -18
Insertion Loss
0 dB - 18 dB Attenuation Settings
50 MHz to < 2000 MHz
2000 MHz – 3000 MHz
Attenuation Error
MHz
Return Loss
Relative Phase
All States
P1dB
Input
IIP3
IIP3 Two tones at +18 dBm, 20 MHz spacing
Switching Speed
50% DC CTRL to 10% / 90% RF
+28
dB
0.6
0.7
dB
+0.1
+0.2
-0.25 / + 0.40
-0.10 / +0.50
dB
dB
15
dB
11
deg
+30
dBm
+61
dBm
26
ns
Performance Plots
Figure 3. Attenuation vs. Attenuation Setting
Figure 4. Attenuation Error vs. Frequency
@ T = +25C
6dB State
12dB State
18dB State
0.50
18
Attenuation Error (dB.)
Attenuation (dB.)
0.40
12
6
0.30
0.20
0.10
0.00
0
-0.10
0
6
12
Attenuation State (dB.)
18
Figure 5. Insertion Loss vs. Temperature
+25C
-40C
0
500
1000
1500
2000
2500
3000
3500
4000
Frequency (MHz.)
Note:
Attenuation Error Equation - AE = [ ABS {ABS(Insertion Loss @ Attenuation
Setting) - ABS(Reference Loss) } ] - [ ABS(Attenuation Setting) ]
Figure 6. Input Return Loss vs Attenuation
@ T = +25C
+85C
0dB
0.00
6dB
12dB
18dB
0.00
-0.10
-5.00
Input Return Loss (dB.)
Insertion Loss (dB.)
-0.20
-0.30
-0.40
-0.50
-0.60
-0.70
-0.80
-10.00
-15.00
-20.00
-25.00
-30.00
-35.00
-0.90
-40.00
-1.00
0
500
1000
1500
2000
2500
3000
3500
Frequency (MHz)
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 8
4000
0
500
1000
1500
2000
2500
3000
3500
4000
Frequency (MHz.)
Document No. 70-0257-02
│ UltraCMOS™ RFIC Solutions
PE43204
Product Specification
Figure 8. Input Return Loss vs Temperature
@ 12dB State
Figure 7. Output Return Loss vs Attenuation
@ T = +25C
6dB
12dB
-40C
18dB
0.00
-5.00
-5.00
-10.00
Input Return Loss (dB.)
Output Return Loss (dB.)
0dB
0.00
-15.00
-20.00
-25.00
-30.00
-35.00
-10.00
-15.00
-20.00
-25.00
-30.00
-35.00
-45.00
0
500
1000
1500
2000
2500
3000
3500
4000
0
500
1000
1500
Frequency (MHz.)
-40C
+25C
2000
2500
3000
3500
4000
3500
4000
Frequency (MHz.)
Figure 9. Output Return Loss vs Temperature
@ 12dB State
Figure 10. Phase vs Attenuation Setting
@ T = +25C
+85C
0.00
18.00
-10.00
16.00
0dB
6dB
12dB
18dB
14.00
-20.00
Phase (Deg.)
-30.00
-40.00
-50.00
-60.00
12.00
10.00
8.00
6.00
4.00
-70.00
2.00
-80.00
0.00
0
500
1000
1500
2000
2500
3000
3500
4000
0
500
1000
1500
Frequency (MHz.)
0dB
6dB
2000
2500
3000
Frequency (MHz)
Figure 12. Attenuation Error vs. Attenuation
Setting @ 3000 MHz
Figure 11. Input IP3 vs Attenuation Setting
@ T = +25C
12dB
-40C
18dB
+25C
+85C
0.6
70
60
0.4
Attenuation Error (dB.)
50
IIP3 (dBm.)
+85C
-40.00
-40.00
Output Return Loss (dB.)
+25C
40
30
20
10
0.2
0
-0.2
-0.4
0
0
500
1000
1500
2000
2500
3000
Frequency (MHz.)
Document No. 70-0257-02 │ www.psemi.com
3500
4000
4500
-0.6
0
6
12
18
Attenuation Setting(dB.)
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 8
PE43204
Product Specification
VDD
C1
C2
Figure 13. Pin Configuration (Top View)
12
11
10
Table 4. Operating Ranges
Parameter
VDD Power Supply Voltage
Min
Typ
Max
Units
3.0
3.3
3.6
V
8
200
µA
IDD Power Supply Current
GND
1
RF1
2
NC
3
9
Exposed
ground paddle
8
7
GND
Digital Input High
0.7xVDD
3.6
V
Digital Input Low
0
0.3xV DD
V
10
µA
+23
dBm
85
°C
RF2
Digital Input Leakage
NC
PIN Input power (50Ω)
20 MHz ≤ 4.0 GHz
TOP Operating temperature range
4
5
-40
25
6
NC
NC
NC
Table 5. Absolute Maximum Ratings
Symbol
Max
Units
-0.3
4.0
V
Voltage on any Digital input
-0.3
VDD+
0.3
V
TST
Storage temperature range
-65
150
°C
PIN
Input power (50Ω)
20 MHz ≤ 4.0 GHz
+23
dBm
VESD
ESD voltage (Human Body Model,
MIL_STD 883 Method 3015.7)
2000
V
VDD
Table 2. Pin Descriptions
Pin No.
Pin Name
1
GND
Ground
2
RF12
RF1 port
VI
Description
3
NC
1
No Connect
4
NC1
No Connect
5
NC1
No Connect
6
NC1
No Connect
7
NC
1
No Connect
8
RF22
RF2 port
Ground
Power supply voltage
Min
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
9
GND
10
C2
Attenuation control bit, 12 dB
11
C1
Attenuation control bit, 6 dB
12
VDD
Power Supply Pin
Notes: 1. Pins 3 through 7 may be tied to ground if desired, but
they are not connected to ground internal to the package
2. All RF pins must be DC blocked with an external series
capacitor or held at 0 VDC.
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the package
must be grounded for proper device operation.
Table 3. Attenuation Word Truth Table
C1
C2
Attenuation Setting RF1-RF2
L
L
Reference I.L.
H
L
6 dB
L
H
12 dB
H
H
18 dB
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 8
Parameter/Conditions
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESDsensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
specified rating.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the PE43204 in
the 12-lead 3x3 QFN package is MSL1.
Switching Frequency
The PE43204 has a maximum 25 kHz switching rate.
Switching rate is defined to be the speed at which the
DSA can be toggled across attenuation states.
Document No. 70-0257-02
│ UltraCMOS™ RFIC Solutions
PE43204
Product Specification
Figure 14. Evaluation Board Layouts
Evaluation Kit
Peregrine Specification 101/0344
The 2-bit DSA EK Board was designed to ease
customer evaluation of Peregrine’s PE43204.
For automated programming, connect the test
harness provided with the EVK to the parallel port
of the PC and to the 6-pin header of the
PCB. Connect the loose wire of the supplied
cable to a power supply set at 3.3V DC. Set the
SP3T switches S1 and S2 to the ‘MIDDLE’ toggle
position. After downloading and installing the
DSA EVK software from www.psemi.com, run the
software and select ‘PE43204’ from the drop down
menu. Using the software, enable or disable
each setting to the desired attenuation state. The
software automatically programs the DSA each
time an attenuation state is enabled or disabled.
Figure 15. Evaluation Board Schematic
Peregrine Specification 102/0416
VCTL
S1
SS14MDP2
1
3
2
J1
HEADER 3X2
1
3
5
2
4
6
4
2
4
6
S2
SS14MDP2
1
3
2
R1
Note: To minimize switching time, C3 and C4 can
be removed.
Document No. 70-0257-02 │ www.psemi.com
C3
C4
10PF
9
8
4
NC
RF1
RF2
7
1
J3
SMASM
Z=50 Ohm
1
2
NC
RF2
PE43204
13 CENTER GND PAD
De-embeding trace
Z=50 Ohm
J4
SMASM
2
10
U1
RF1
J5
SMASM
1
2
3
NC
C2
12
VDD
2
NC
1
Z=50 Ohm
1
5
J2
SMASM
C1 11
0 OHM
10PF
2
The PE43204 will always power up into the state
determined by the voltages on the 2 control pins.
The DSA can be preset to any state within the 18
dB range by pre-setting the parallel control pins
prior to power-up. There is a 10µs delay between
the time the DSA is powered-up to the time the
desired state is set. If the control pins are left
floating during power-up, the device will default to
the minimum attenuation setting (insertion loss
state).
C2
100pF
0 OHM
C1
0.1µF
Power-up Control Settings
R2
4
NC
1
3
5
6
VDD
CTL1
CTL2
VCTL
For manual programming, disconnect the test
harness provided with the EVK. Apply 3.3V to
the Vdd header pin and Ground to the GND
header pin. The DUT can be controlled two ways:
1. The mechanical switches in conjunction with
the VCTL pin can be used. Apply desired control
voltage to VCTL header pin. The top mechanical
switch controls the 6dB stage, the bottom
mechanical switch controls the 12dB stage. For
each switch, the left position is the 0V condition,
while the right position is the Vctrl condition. The
middle position leaves the control pin floating.
2. The CTL1 and CTL2 pins on the header can be
used. Each pin directly controls the 6dB and 12dB
stage respectively. The VCTL pin on the header is
left open. The mechanical switches may be left
uninstalled or must be kept in the middle position.
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 8
PE43204
Product Specification
Figure 16. Package Drawing
QFN
QFN 3x3 mm
A
MAX
0.900
NOM
0.850
MIN
0.800
Note: Pin 1 Identification tab is electrically connected to the exposed ground paddle
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 8
Document No. 70-0257-02
│ UltraCMOS™ RFIC Solutions
PE43204
Product Specification
Figure 17. Tape and Reel Drawing
Tape Feed Direction
Pin 1
Top of
Device
Device Orientation in Tape
Figure 18. Marking Specifications
43204
YYWW
ZZZZZ
YYWW = Date Code
ZZZZZ = Last five digits of Lot Number
Table 6. Ordering Information
Order Code
Part Marking
Description
Package
Shipping Method
EK-43204-02
PE43204 -EK
PE43204 – 12QFN 3x3mm-EK
Evaluation Kit
1 / Box
PE43204MLIBA
43204
PE43204 G - 12QFN 3x3mm-75A
Green 12-lead 3x3mm QFN
Cut tape or loose
PE43204MLIBA-Z
43204
PE43204 G – 12QFN 3x3mm-3000C
Green 12-lead 3x3mm QFN
3000 units / T&R
Document No. 70-0257-02 │ www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 8
PE43204
Product Specification
Sales Offices
The Americas
Peregrine Semiconductor Corporation
Peregrine Semiconductor, Asia Pacific (APAC)
9380 Carroll Park Drive
San Diego, CA 92121
Tel: 858-731-9400
Fax: 858-731-9499
Shanghai, 200040, P.R. China
Tel: +86-21-5836-8276
Fax: +86-21-5836-7652
Europe
Peregrine Semiconductor Europe
Bâtiment Maine
13-15 rue des Quatre Vents
F-92380 Garches, France
Tel: +33-1-4741-9173
Fax : +33-1-4741-9173
High-Reliability and Defense Products
Peregrine Semiconductor, Korea
#B-2607, Kolon Tripolis, 210
Geumgok-dong, Bundang-gu, Seongnam-si
Gyeonggi-do, 463-943 South Korea
Tel: +82-31-728-3939
Fax: +82-31-728-3940
Peregrine Semiconductor K.K., Japan
Teikoku Hotel Tower 10B-6
1-1-1 Uchisaiwai-cho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel: +81-3-3502-5211
Fax: +81-3-3502-5213
Americas
San Diego, CA, USA
Phone: 858-731-9475
Fax: 848-731-9499
Europe/Asia-Pacific
Aix-En-Provence Cedex 3, France
Phone: +33-4-4239-3361
Fax: +33-4-4239-7227
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
Preliminary Specification
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a CNF
(Customer Notification Form).
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 8 of 8
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks
of Peregrine Semiconductor Corp.
Document No. 70-0257-02
│ UltraCMOS™ RFIC Solutions