TI 5962-9762201VFA

SN55LVDS32-SP
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SLLSEB4 – MARCH 2012
HIGH-SPEED DIFFERENTIAL LINE RECEIVER
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FEATURES
1
•
•
•
•
•
•
•
•
•
•
QML-V Qualified, SMD 5962-97621
Operate From a Single 3.3-V Supply
Designed for Signaling Rates of up to 100
Mbps
Differential Input Thresholds ±100 mV Max
Typical Propagation Delay Times of 2.1 ns
Power Dissipation 60 mW Typical Per Receiver
at Maximum Data Rate
Bus-Terminal ESD Protection Exceeds 8 kV
Low-Voltage TTL (LVTTL) Logic Input Levels
Open-Circuit Fail-Safe
Cold Sparing for Space and High Reliability
Applications Requiring Redundancy
J OR W PACKAGE
(TOP VIEW)
DESCRIPTION
The SN55LVDS32 is a differential line receiver that implements the electrical characteristics of low-voltage
differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard
levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a
3.3-V supply rail. Any of the four differential receivers provides a valid logical output state with a ±100-mV
differential input voltage within the input common-mode voltage range. The input common-mode voltage range
allows 1 V of ground potential difference between two LVDS nodes.
The intended application of these devices and signaling technique is both point-to-point and multidrop (one driver
and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The
transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of
data transfer depends on the attenuation characteristics of the media and the noise coupling to the environment.
The SN55LVDS32 is characterized for operation from –55°C to 125°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
SN55LVDS32-SP
SLLSEB4 – MARCH 2012
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
TA
–55°C to 125°C
(1)
(2)
PACKAGE (2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
CDIP - J
5962-9762201VEA
5962-9762201VEA
CFP - W
5962-9762201VFA
5962-9762201VFA
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
xxx
SN55LVDS32 logic diagram
(positive logic)
G
G
1A
1B
4
12
2
3
1Y
1
6
2A
5
2Y
7
2B
3A
3B
4A
4B
2
10
11
9
14
15
13
3Y
4Y
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Table 1. FUNCTION TABLE (1)
SN55LVDS32
ENABLES
DIFFERENTIAL INPUT
A, B
VID ≥ 100 mV
–100 mV < VID ≤ 100 mV
VID ≤ –100 mV
X
Open
(1)
OUTPUT
G
G
Y
H
X
H
X
L
H
H
X
?
X
L
?
H
X
L
X
L
L
L
H
Z
H
X
H
X
L
H
H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
logic symbol †
SN55LVDS32
G
G
1A
1B
2A
2B
3A
3B
4A
4B
†
4
≥1
EN
12
2
3
1Y
1
5
6
2Y
7
10
11
3Y
9
14
13
15
4Y
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
EQUIVALENT OF EACH A OR B INPUT
EQUIVALENT OF G, G, 1,2EN OR
3,4EN INPUTS
VCC
VCC
300 kΩ
TYPICAL OF ALL OUTPUTS
VCC
300 kΩ
50 Ω
5Ω
Input
Y Output
A Input
7V
B Input
7V
7V
7V
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
UNIT
VCC Supply voltage range
VI
(2)
–0.5 V to 4 V
Input voltage range
Enables and output
–0.5 V to VCC + 0.5 V
A or B
–0.5 V to 4 V
Continuous total power dissipation
See Dissipation Rating
Table
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260°C
Tstg Storage temperature range
(1)
–65°C to 150°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages, except differential I/O bus voltages, are with respect to the network ground terminal.
(2)
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR (1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
J
1375 mW
11 mW/°C
880 mW
715 mW
275 mW
W
1000 mW
8 mW/°C
640 mW
520 mW
200 mW
(1)
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
RECOMMENDED OPERATING CONDITIONS
VCC
Supply voltage
VIH
High-level input voltage
G, G, 1,2EN, or 3,4EN
VIL
Low-level input voltage
G, G, 1,2EN, or 3,4EN
|VID|
Magnitude of differential input voltage
VIC
Common-mode input voltage (see Figure 1)
MIN
NOM
MAX
3
3.3
3.6
2
V
V
0.8
V
0.1
0.6
V
|VID|/2
2.4 - |VID|/2
VCC - 0.8
TA
UNIT
Operating free-air temperature
–55
125
V
°C
COMMON-MODE INPUT VOLTAGE RANGE
vs
DIFFERENTIAL INPUT VOLTAGE
VIC - Common-Mode Input Voltage Range - V
2.5
2
Max at VCC > 3.15 V
Max at VCC = 3 V
1.5
1
0.5
Min
0
0
0.1
0.2
0.3
0.4
0.5
VID - Differential Input Voltage - V
0.6
Figure 1. VIC Versus VID and VCC
4
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VITH+
Positive-going differential input voltage
threshold
See Figure 2, Table 2, and
(2)
VITH–
Negative-going differential input voltage
threshold (3)
See Figure 2, Table 2, and
(2)
VOH
High-level output voltage
IOH = –8 mA
VOL
Low-level output voltage
IOL = 8 mA
Supply current
II
Input current (A or B inputs)
II(OFF)
Power-off input current (A or B inputs)
VCC = 0,
IIH
High-level input current (EN, G, or G inputs)
IIL
Low-level input current (EN, G, or G inputs)
IOZ
High-impedance output current
VO = 0 or VCC
MAX
UNIT
100
mV
-100
mV
2.4
V
0.4
Enabled, No load
ICC
(1)
(2)
(3)
MIN TYP (1)
TEST CONDITIONS
10
18
0.25
0.5
-2
-10
-20
-1.2
-3
Disabled
VI = 0
VI = 2.4 V
V
mA
µA
20
μA
VIH = 2 V
10
μA
VIL = 0.8 V
10
μA
±12
μA
VI = 2.4 V
6
All typical values are at TA = 25°C and with VCC = 3.3 V.
|VITH| = 200 mV for operation at –55°C.
The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the
negative-going differential input voltage threshold only.
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time, low-to-high-level output
tPHL
Propagation delay time, high-to-low-level output
tsk(o)
Channel-to-channel output skew (1)
tr
TYP
MAX
1.3
2.3
6
UNIT
ns
1.4
2.2
6.1
ns
0.1
ns
Differential output signal rise time (20% to 80%)
0.6
ns
tf
Differential output signal fall time (80% to 20%)
0.7
ns
tPHZ
Propagation delay time, high-level-to-high-impedance output
6.5
12
ns
tPLZ
Propagation delay time, low-level-to-high-impedance output
5.5
12
ns
tPZH
Propagation delay time, high-impedance-to-high-level output
8
12
ns
tPZL
Propagation delay time, high-impedance-to-low-level output
3
12
ns
(1)
CL = 10 pF, See Figure 3
MIN
See Figure 4
tsk(o) is the maximum delay time difference between drivers on the same device.
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PARAMETER MEASUREMENT INFORMATION
A
Y
VID
B
(VIA + VIB)/2
VIA
VIC
VO
VIB
Figure 2. Voltage Definitions
Table 2. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED VOLTAGES (1)
(1)
6
RESULTING
DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMONMODE
INPUT VOLTAGE
VID (mV)
VIC (mV)
1.2
VIA (mV)
VIB (mV)
1.25
1.15
100
1.15
1.25
-100
1.2
2.4
2.3
100
2.35
2.3
2.4
-100
2.35
0.1
0
100
0.05
0
0.1
-100
0.05
1.5
0.9
600
1.2
0.9
1.5
-600
1.2
2.4
1.8
600
2.1
1.8
2.4
-600
2.1
0.6
0
600
0.3
0
0.6
-600
0.3
These voltages are applied for a minimum of 1.5 µs.
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VID
VIA
CL = 10 pF
VIB
VO
VIA
1.4 V
VIB
1V
0.4 V
0
-0.4 V
VID
tPHL
tPLH
80%
VO
20%
tf
VOH
80%
1.4 V
VOL
20%
tr
A.
All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition
rate(PRR) = 50 Mpps, pulse width = 10 ±0.2 ns.
B.
CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
Figure 3. Timing Test Circuit and Waveforms
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B
1.2 V
500 Ω
A
Inputs
(see Note A)
G
10 pF
(see Note B)
±
VO
VTEST
G
1,2EN or 3,4EN
VTEST
2.5 V
A
1V
2V
1.4 V
0.8 V
G, 1,2EN,
or 3,4EN
2V
1.4 V
0.8 V
G
tPLZ
tPZL
tPLZ
tPZL
Y
VTEST
2.5 V
1.4 V
VOL + 0.5 V
VOL
0
1.4 V
A
G, 1,2EN,
or 3,4EN
2V
1.4 V
0.8 V
G
2V
1.4 V
0.8 V
tPHZ
tPZH
tPHZ
tPZH
Y
VOH
VOH - 0.5 V
1.4 V
0
A.
All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition
rate(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns.
B.
CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
Figure 4. Enable- and Disable-Time Test Circuit and Waveforms
TYPICAL CHARACTERISTICS
8
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TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
vs
FREQUENCY
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
Four Receivers, Loaded
Per Figure 3, Switching
Simultaneously
I CC − Supply Current − mA (rms)
75
t PLH(D) − Low-to-High Propagation Delay Time − ns
85
VCC = 3.6 V
VCC = 3.3 V
65
VCC = 3 V
55
45
35
25
15
50
150
100
200
2.7
2.5
VCC = 3 V
VCC = 3.3 V
2.3
VCC = 3.6 V
2.1
1.9
1.7
1.5
−50
f − Frequency − MHz
0
50
TA − Free-Air Temperature − °C
Figure 5.
100
Figure 6.
t PHL(D) − High-to-Low Propagation Delay Time − ns
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
2.7
2.5
2.3
VCC = 3 V
2.1
VCC = 3.3 V
1.9
VCC = 3.6 V
1.7
1.5
−50
0
50
TA − Free-Air Temperature − °C
Figure 7.
100
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TYPICAL CHARACTERISTICS (continued)
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
5.0
3.5
VOL − Low-Level Output Voltage − V
VOH − High-Level Output Voltage − V
4.5
3.0
2.5
2.0
1.5
1.0
0.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
−60
0.0
−50
−40
−30
−20
−10
IOH − High-Level Output Current − mA
0
0
10
Figure 8.
10
20
30
40
50
60
70
80
IOL − Low-Level Output Current − mA
Figure 9.
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APPLICATION INFORMATION
EQUIPMENT
•
•
•
Hewlett Packard HP6624A DC power supply
Tektronix TDS7404 Real Time Scope
Agilent ParBERT E4832A
Hewlett Packard HP6624A
DC Power Supply
Agilent ParBERT
(E4832A)
Bench Test Board
Tektronix TDS7404
Real Time Scope
Figure 10. Equipment Setup
All Rx running at 100 Mbps; Channel 1: 1Y, Channel 2: 2Y; Channel 3: 3Y; Channel 4: 4Y
Figure 11. Typical Eye Patterns SN55LVDS32: (T = 25°C; VCC = 3.6 V; PRBS = 223-1)
USING AN LVDS RECEIVER WITH RS-422 DATA
Receipt of data from a TIA/EIA-422 line driver can be accomplished using a TIA/EIA-644 line receiver with the
addition of an attenuator circuit. This technique gives the user a high-speed and low-power 422 receiver.
If the ground noise between the transmitter and receiver is not a concern (less than ±1 V), the answer can be as
simple as shown in Figure 12. A resistor divider circuit in front of the LVDS receiver attenuates the 422
differential signal to LVDS levels.
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The resistors present a total differential load of 100 Ω to match the characteristic impedance of the transmission
line and to reduce the signal 10:1. The maximum 422 differential output signal, or 6 V, is reduced to 600 mV. The
high input impedance of the LVDS receiver prevents input bias offsets and maintains a greater than 200-mV
differential input voltage threshold at the inputs to the divider. This circuit is used in front of each LVDS channel
that also receives 422 signals.
R1
45.3 Ω
SN55LVDS32
R3
5.11Ω
A
R4
5.11Ω
B
Y
R2
45.3 Ω
NOTE: The components used were standard values. (1) R1, R2 = NRC12F45R3TR, NIC components, 45.3 Ω, 1/8 W, 1%,
1206 package (2) R3, R4 = NRC12F5R11TR, NIC components, 5.11 Ω, 1/8 W, 1%, 1206 package (3) The resistor
values do not need to be 1% tolerance. However, it can be difficult locating a supplier of resistors having values less
than 100 Ω in stock and readily available. The user may find other suppliers with comparable parts having tolerances
of 5% or even 10%. These parts are adequate for use in this circuit.
Figure 12. RS-422 Data Input to an LVDS Receiver Under Low Ground-Noise Conditions
If ground noise between the RS-422 driver and LVDS receiver is a concern, the common-mode voltage must be
attenuated. The circuit must then be modified to connect the node between R3 and R4 to the LVDS receiver
ground. This modification to the circuit increases the common-mode voltage from ±1 V to greater than ±4.5 V.
The devices are generally used as building blocks for high-speed point-to-point data transmission where ground
differences are less than 1 V. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers
approach ECL speeds without the power and dual-supply requirements.
TRANSMISSION DISTANCE
vs
SIGNALING RATE
Transmission Distance − m
100
30% Jitter
(see Note A)
10
5% Jitter
(see Note A)
1
24 AWG UTP 96 Ω
(PVC Dielectric)
0.1
10
100
1000
Signaling Rate − Mbps
A.
This parameter is the percentage of distortion of the unit interval (UI) with a pseudorandom data pattern.
Figure 13. Typical Transmission Distance Versus Signaling Rate
12
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1
1B
VCC
16
0.1 µF
(see Note A)
100 Ω
2
3
VCC 4
5
6
1A
4B
2Y
4A
4Y
G
2A
3Y
0.001 µF
(see Note A)
15
1Y
G
3.3 V
14
100 Ω
(see Note B)
13
12
11
See Note C
100 Ω
7
2B
3A
10
100 Ω
8
GND
3B
9
A.
Place a 0.1-μF and a 0.001-μF Z5U ceramic, mica, or polystyrene dielectric, 0805 size, chip capacitor between VCC
and the ground plane. The capacitors should be located as close as possible to the device terminals.
B.
The termination resistance value should match the nominal characteristic impedance of the transmission media with
±10%.
C.
Unused enable inputs should be tied to VCC or GND as appropriate.
Figure 14. Typical Application Circuit Schematic
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1/4 ’LVDS31
Strb/Data_TX
Tp Bias on
Twisted-Pair A
Strb/Data_Enable
TP
55 Ω
’LVDS32
5 kΩ
Data/Strobe
55 Ω
3.3 V
TP
20 kΩ
500 Ω
VG on
Twisted-Pair B
1 Arb_RX
500 Ω
20 kΩ
3.3 V
500 Ω
20 kΩ
2 Arb_RX
500 Ω
20 kΩ
3.3 V
7 kΩ
Twisted-Pair B Only
7 kΩ
10 kΩ
Port_Status
3.3 kΩ
NOTES: A.
B.
C.
D.
Resistors are leadless, thick film (0603), 5% tolerance.
Decoupling capacitance is not shown, but recommended.
VCC is 3 V to 3.6 V.
The differential output voltage of the ’LVDS31 can exceed that specified by IEEE1394.
Figure 15. 100-Mbps IEEE 1394 Transceiver
FAIL-SAFE
One of the most common problems with differential signaling applications is how the system responds when no
differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers in that
its output logic state can be indeterminate when the differential input voltage is between –100 mV and100 mV if it
is within its recommended input common-mode voltage range. However, TI LVDS receivers handle the openinput circuit situation differently.
Open-input circuit means that there is little or no input current to the receiver from the data line itself. This could
be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS
receiver pulls each line of the signal pair to near VCC through 300-kΩ resistors (see Figure 16). The fail-safe
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high level, regardless of the differential input voltage.
14
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VCC
300 kΩ
300 kΩ
A
Rt
Y
B
VIT ≈ 2.3 V
Figure 16. Open-Circuit Fail-Safe of LVDS Receiver
It is only under these conditions that the output of the receiver is valid with less than a 100-mV differential input
voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it
is connected as shown in Figure 16. Other termination circuits may allow a dc current to ground that could defeat
the pullup currents from the receiver and the fail-safe feature.
0.01 µF
1
VCC
16
1B
0.1 µF
(see Note A)
100 Ω
2
3
VCC 4
5
6
≈3.6 V
1A
4B
15
1Y
4A
G
4Y
2Y
G
2A
3Y
5V
1N645
(two places)
14
100 Ω
(see Note B)
13
12
11
See Note C
100 Ω
7
2B
3A
GND
3B
10
100 Ω
8
9
A.
Place a 0.1-μF Z5U ceramic, mica, or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground
plane. The capacitor should be located as close as possible to the device terminals.
B.
The termination resistance value should match the nominal characteristic impedance of the transmission media with
±10%.
C.
Unused enable inputs should be tied to VCC or GND, as appropriate.
Figure 17. Operation With 5-V Supply
COLD SPARING
Systems using cold sparing have a redundant device electrically connected without power supplied. To support
this configuration, the spare must present a high-input impedance to the system so that it does not draw
appreciable power. In cold sparing, voltage may be applied to an I/O before and during power up of a device.
When the device is powered off, VCC must be clamped to ground and the I/O voltages applied must be within the
specified recommended operating conditions.
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RELATED INFORMATION
IBIS modeling is available for this device. Contact the local TI sales office or the TI Web site at www.ti.com for
more information.
For more application guidelines, see the following documents:
• Low-Voltage Differential Signaling Design Notes (SLLA014)
• Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038)
• Reducing EMI With LVDS (SLLA030)
• Slew Rate Control of LVDS Circuits (SLLA034)
• Using an LVDS Receiver With RS-422 Data (SLLA031)
16
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Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): SN55LVDS32-SP
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2012
PACKAGING INFORMATION
Orderable Device
5962-9762201VFA
Status
(1)
Package Type Package
Drawing
ACTIVE
CFP
W
Pins
Package Qty
16
1
Eco Plan
TBD
(2)
Lead/
Ball Finish
A42
MSL Peak Temp
(3)
Samples
(Requires Login)
N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN55LVDS32-SP :
• Catalog: SN55LVDS32
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 1
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