TI SN74BCT899

SCBS253 − JUNE 1992 − REVISED NOVEMBER 1993
•
•
•
•
•
State-of-the-Art BiCMOS Design
Significantly Reduces ICCZ
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
Option to Select Generate Parity and Check
or Feed-Through Data/Parity in A-to-B or
B-to-A Directions
Simultaneously Generates and Checks
Parity
Packaged in Plastic Small-Outline Package
description
The SN74BCT899 is a 9-bit to 9-bit parity
transceiver with transparent latches. The device
can operate as a feed-through transceiver or it can
generate/check parity from the 8-bit data buses in
either direction. It has a current-sinking capability
of 24 mA at the A bus and 64 mA at the B bus.
DW PACKAGE
(TOP VIEW)
ODD/EVEN
ERRA
LEAB
A1
A2
A3
A4
A5
A6
A7
A8
APAR
OEBA
GND
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
OEAB
B1
B2
B3
B4
B5
B6
B7
B8
BPAR
LEBA
SEL
ERRB
The SN74BCT899 features independent latchenable (LEAB or LEBA) inputs, a select (SEL)
input for ODD/EVEN parity, and separate
error-signal (ERRA or ERRB) outputs for checking
parity.
The SN74BCT899 is characterized for operation
from 0°C to 70°C.
Copyright  1993, Texas Instruments Incorporated
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POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2−1
SCBS253 − JUNE 1992 − REVISED NOVEMBER 1993
FUNCTION TABLE
INPUTS
OPERATION OR FUNCTION
OEAB
OEBA
SEL
LEAB
LEBA
H
H
X
X
X
Buses A and B are in the high-impedance state.
H
L
L
X
H
Generates parity from B1 −B8 based on ODD/EVEN. Generated parity → APAR. Generated parity
checked against BPAR and output as ERRB.
H
L
L
H
H
Generates parity from B1 −B8 based on ODD/EVEN. Generated parity → APAR. Generated parity
checked against BPAR and output as ERRB. Generated parity also fed back through the A latch
for generate/check as ERRA.
H
L
L
X
L
Generates parity from B-latch data based on ODD/EVEN. Generated parity → APAR. Generated
parity checked against latched BPAR and output as ERRB.
H
L
H
X
H
BPAR /B1 −B8 → APAR/A1 −A8 feed-through mode. Generated parity checked against BPAR and
output as ERRB.
H
L
H
H
H
BPAR /B1 −B8 → APAR/A1 −A8 feed-through mode. Generated parity checked against BPAR and
output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA.
L
H
L
H
X
Generates parity from A1 −A8 based on ODD/EVEN. Generated parity → BPAR. Generated parity
checked against APAR and output as ERRA.
L
H
L
H
H
Generates parity from A1 −A8 based on ODD/EVEN. Generated parity → BPAR. Generated parity
checked against APAR and output as ERRA. Generated parity also fed back through the B latch
for generate/check as ERRB.
L
H
L
L
X
Generates parity from A-latch data based on ODD/EVEN. Generated parity → BPAR. Generated
parity checked against latched APAR and output as ERRA.
L
H
H
H
X
APAR /A1 −A8 → BPAR/B1−B8 feed-through mode. Generated parity checked against APAR and
output as ERRA.
L
H
H
H
X
APAR /A1 −A8 → BPAR/B1−B8 feed-through mode. Generated parity checked against APAR and
output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB.
L
L
X
X
X
Output to A bus and B bus
PARITY FUNCTION TABLE
INPUTS†
OUTPUTS
ODD/EVEN
Σ OF INPUTS
A1 −A8 = H
L
0, 2, 4, 6, 8
L
1, 3, 5, 7
L
0, 2, 4, 6, 8
H
L
L
L
1, 3, 5, 7
H
H
H
H
0, 2, 4, 6, 8
L
H
L
H
1, 3, 5, 7
L
L
H
H
0, 2, 4, 6, 8
H
H
H
BPAR‡
ERRA
L
L
H
L
H
L
APAR
H
1, 3, 5, 7
H
L
L
† If LE = H, current A1 −A8 and APAR data is used. If LE = L,
latched A1−A8 and APAR data is used.
‡ This is the value of BPAR if SEL = L. If SEL = H, BPAR = APAR.
2−2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCBS253 − JUNE 1992 − REVISED NOVEMBER 1993
logic diagram (positive logic)
ODD/EVEN
SEL
OEBA
LEAB
OEAB
LEBA
9-Bit
Transp.
Latch
A1
A2
A3
A4
A5
A6
A7
A8
APAR
9-Bit
Buffer
B1
B2
B3
B4
B5
B6
B7
B8
BPAR
Parity
Generator
ERRA
ERRB
Parity
Generator
9-Bit
Transp.
Latch
9-Bit
Buffer
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . . −0.5 V to 5.5 V
Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 mA
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2−3
SCBS253 − JUNE 1992 − REVISED NOVEMBER 1993
recommended operating conditions (see Note 2)
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
High-level input voltage
High-level output current
IOL
Low-level output current
∆t /∆v
Input transition rise or fall rate
MAX
4.5
5
5.5
V
V
V
VCC
−3
V
A1 −A8
B1 −B8
−15
A1 −A8
24
B1 −B8
64
0
Outputs enabled
POST OFFICE BOX 655303
UNIT
0.8
TA
Operating free-air temperature
NOTE 2: Unused or floating pins (input or I/O) must be held high or low.
2−4
NOM
2
Input voltage
IOH
MIN
• DALLAS, TEXAS 75265
0
mA
mA
10
ns / V
70
°C
SCBS253 − JUNE 1992 − REVISED NOVEMBER 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
A1 −A8, APAR, ERRA, ERRB
VOH
II = −18 mA
IOH = −1 mA
2.7
3.4
2.5
3.4
VCC = 4.5 V
IOH = −1 mA
IOH = − 3 mA
2.4
3.3
IOH = − 3 mA
IOH = − 3 mA
2.7
3.4
2.4
3.4
2
3.1
VCC = 4.5 V
A1 −A8, APAR, ERRA, ERRB
VOL
VCC = 4.5 V
B1 −B8, BPAR
II‡
IIH‡
IIL‡
IOS§
Outputs high
Outputs low
ICC
IOL = 20 mA
IOL = 24 mA
0.35
IOL = 48 mA
IOL = 64 mA
0.42
Outputs disabled, ERR outputs high
Ci
A ports
B ports
MAX
UNIT
−1.2
V
V
0.5
V
0.55
VCC = 5.5 V,
VCC = 5.5 V,
VI = 5.5 V
VI = 2.7 V
100
µA
20
µA
VCC = 5.5 V,
VI = 0.5 V
−20
µA
VCC = 5.5 V,
VO = 0
−60
−150
−100
−225
A to B
0.5
B to A
0.5
2
A to B
43
69
22
34
6
10
B to A
6
10
A to B
0.5
2
B to A
0.5
2
B to A
A to B
Outputs disabled, ERR outputs low
Cio
IOH = −12 mA
IOH = −15 mA
A1 −A8, APAR, ERRA, ERRB
B1 −B8, BPAR
TYP†
VCC = 4.5 V,
VCC = 4.75 V,
VCC = 4.75 V,
B1 −B8, BPAR
MIN
VCC = 5.5 V,
Outputs open
VCC = 5 V,
VI = 0.5 V
VCC = 5 V,
VO = 0.5 V
mA
2
6.5
mA
pF
10.5
pF
12.5
† All typical values are at VCC = 5 V, TA = 25°C.
‡ For I/O ports, the parameters IIH and IIL include the off-state output current.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25°C
MIN
MIN
MAX
UNIT
MAX
tw
tsu
Pulse duration
5
5
ns
Setup time before LE↓
Data high or low
4.5
4.5
ns
th
Hold time after LE↓
Data high or low
1.5
1.5
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2−5
SCBS253 − JUNE 1992 − REVISED NOVEMBER 1993
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Note 3)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPLH
tPHL
A or B
BPAR or APAR
tPLH
tPHL
APAR or BPAR
BPAR or APAR
tPLH
tPHL
A, APAR, or
B, BPAR
ERRA or ERRB
tPLH
tPHL
ODD/EVEN
ERRA or ERRB
tPLH
tPHL
ODD/EVEN
BPAR or APAR
tPLH
tPHL
SEL
BPAR or APAR
tPLH
tPHL
LEAB OR LEBA
B or A
tPLH
tPHL
LEAB OR LEBA
BPAR or APAR
(parity feed-through)
tPLH
tPHL
LEAB OR LEBA
BPAR or APAR
(parity generated)
tPLH
tPHL
LEAB OR LEBA
ERRB or ERRA
tPZH
tPZL
OEAB or OEBA
B or A
tPHZ
tPLZ
OEAB or OEBA
B or A
PARAMETER
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
2−6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC = 5 V,
TA = 25°C
MIN
MAX
7.6
1.9
9.1
6.8
1.8
8.1
MIN
TYP
MAX
1.9
6
1.8
5.2
4.3
11
13
4.3
16.1
4.5
10.7
12.7
4.5
15.3
2.2
5.2
6.7
2.2
8
1.7
4.7
6.3
1.7
7.6
3.4
10.6
12.6
3.4
15.7
3.6
10.5
12.5
3.6
15.3
4.6
8.8
10.5
4.6
12.8
4.1
8.4
10.2
4.1
12.8
4.5
9
10.7
4.5
13.1
4.4
8.5
10.7
4.4
13.3
1.4
4.6
6.2
1.4
7.7
1.6
4.4
5.9
1.6
7.1
2.6
7.6
9.3
2.6
10.9
3.3
6.5
8.2
3.3
9.3
3
6.7
8.3
3
9.9
3
6.1
7.7
3
8.7
5.2
10.2
12.1
5.2
14.8
5.1
8.9
10.7
5.1
12.5
5.3
10.3
12.3
5.3
14.9
5
9.2
11
5
12.9
1.8
5.6
7.2
1.8
9
2.1
10.5
12.2
2.1
13.9
2.9
6.4
8.1
2.9
9.8
2.1
5.5
7.1
2.1
8.1
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
SN74BCT899DW
OBSOLETE
SOIC
DW
28
TBD
Call TI
Call TI
SN74BCT899DWR
OBSOLETE
SOIC
DW
28
TBD
Call TI
Call TI
SN74BCT899DWR
OBSOLETE
SOIC
DW
28
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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