× × SDAS182 − APRIL 1990
D Independent Asychronous Inputs and
D
D
D
D
D
D
N PACKAGE
(TOP VIEW)
Outputs
Bidirectional
32 Words by 9 Bits
Programmable Depth
Data Rates from 0 to 40 MHz
Fall-Through Time . . . 22 ns Typ
3-State Outputs
RSTA
DAF
A0
A1
A2
GND
A3
A4
A5
A6
GND
VCC
A7
A8
LDCKA
FULLA
UNCKB
EMPTYB
SAB
GAB
description
This 576-bit memory uses advanced low-power
Schottky IMPACT-X technology and features
high speed and fast fall-through times. It consists
of two FIFOs organized as 32 words by 9 bits
each.
A FIFO memory is a storage device that allows
data to be written into and read from its array at
independent data rates. These FIFOs are
designed to process data at rates from 0 to 40
MHz in a bit-parallel format, word by word.
The SN74ALS2238 consists of bus-transceiver
circuits, two 32 × 9 FIFOs, and control circuitry
arranged for multiplexed transmission of data
directly from the data bus or from the internal FIFO
memories. Enables GAB and GBA are provided to
control the transceiver functions. The SAB and
SBA control pins are provided to select whether
real-time or stored data is transferred. The
circuitry used for select control eliminates the
typical decoding glitch that occurs in a multiplexer
during the transition between stored and real-time
data. A low level selects real-time data and a high
selects stored data. Eight fundamental
bus-management functions can be performed as
shown in Figure 1.
1
40
2
39
3
38
4
37
5
36
6
35
7
34
8
33
9
32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
RSTB
DBF
B0
B1
B2
GND
B3
B4
B5
B6
GND
VCC
B7
B8
LDCKB
FULLB
UNCKA
EMPTYA
SBA
GBA
A2
A1
A0
GND
DAF
RSTA
RSTB
DBF
GND
B0
B1
FN PACKAGE
(TOP VIEW)
GND
VCC
A3
A4
A5
A6
GND
VCC
A7
A8
LDCKA
3
2 1 44 43 42 41 40
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
B2
GND
VCC
B3
B4
B5
B6
GND
VCC
B7
B8
FULLA
UNCKB
EMPTYB
SAB
GAB
GBA
SBA
EMPTYA
UNCKA
FULLB
LDCKB
Data on the A or B data bus, or both, is written into
the FIFOs on a low-to-high transition at the load
clock (LDCKA or LDCKB) input and is read out on
a low-to-high transition at the unload clock
(UNCKA or UNCKB) input. The memory is full
when the number of words clocked in exceeds, by
the defined depth, the number of words clocked
out.
6 5 4
7
When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory is
empty, UNCK signals have no effect.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
IMPACT-X is a trademark of Texas Instruments Incorporated.
Copyright 1990, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
1
× × SDAS182 − APRIL 1990
description (continued)
Status of the FIFO memories is monitored by the FULLA, FULLB, EMPTYA, and EMPTYB output flags. The
FULLA and FULLB are definable full flags. A high-to-low transition on DAF stores the binary value of A0 through
A4 into a register for use as the value of X. A high-to-low transition on DBF stores the binary value of B0 through
B4 into a register for use as the value of Y. In this way, the depth of either FIFO can be defined to be one to
32 words deep. The value of X and Y must be defined after power up or the stored value of X and Y will be
ambiguous. The FULLA and FULLB outputs are low when their corresponding memories are full and high when
the memories are not full.
The EMPTYA and EMPTYB outputs are low when their corresponding memories are empty and high when they
are not empty. The status flag outputs are always active.
A low-level pulse on the RSTA or RSTB inputs resets the control pointers on FIFO A or FIFO B and also sets
EMPTYA low and FULLA high or EMPTYB low and FULLB high. The outputs are not reset to any specific logic
levels. With DAF at a low level, a low-level pulse on RSTA sets FIFO A to a depth of 32 − X, where X is the value
stored above. With DAF at a high level, a low level pulse on RSTA sets FIFO A to a depth of 32 words. The depth
of FIFO B is set in a similar manner. The first low-to-high transition on LDCKA or LDCKB, either after a reset
pulse or from an empty condition, will cause EMPTYA or EMPTYB to go high and the data to appear on the
Q outputs. It is important to note that the first word does not have to be unloaded. Cascading is easily
accomplished in the word-width direction, but is not possible in the word-depth direction.
The SN74ALS2238 is characterized for operation from 0°C to 70°C.
logic symbol†
SBA
SAB
GAB
GBA
RSTA
DAF
LDCKA
UNCKA
FULLA
EMPTYA
A0
A1
A2
A3
A4
A5
A6
A7
A8
22
19
20
21
1
2
Φ
FIFO
32 × 9 × 2
SN74ALS2238
MODE
0
1
EN1
EN2
RESET A
RESET B
DEF A FULL
DEF B FULL
LDCKA
LDCKB
15
24
16
23
3
4
17
FULL B
FULLA
EMPTYB
EMPTYA
0
0
25
18
38
37
5
36
7
34
8
33
A Data
9
B Data
32
10
31
13
28
14
8
8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the N package.
2
39
26
UNCKB
UNCKA
40
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
27
RSTB
DBF
LDCKB
UNCKB
FULLB
EMPTYB
B0
B1
B2
B3
B4
B5
B6
B7
B8
× × SDAS182 − APRIL 1990
logic diagram (positive logic)
SAB
SBA
19
22
Φ
FIFO B
32 × 9
EMPTYB
UNCKB
GBA
40
39
18
RSTB
DBF
25
26 FULLB
LDCKB
17
38
21
Q
D
B0
One of Nine Channels
To Other Channels
GAB
RSTA
DAF
FULLA
LDCKA
A0
20
Φ
FIFO A
32 × 9
1
2
23
16
15
3
24
D
EMPTYA
UNCKA
Q
One of Nine Channels
To Other Channels
Pin numbers shown are for the N package.
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
3
× × SDAS182 − APRIL 1990
In
FIFO A
Out
Bus A
Bus B
Bus A
Bus B
FIFO B
Out
In
FIFO B
Out
In
SAB SBA GAB GBA
L
X
H
L
In
SAB SBA GAB GBA
X
X
L
L
FIFO A
Out
In
Bus A
Bus B
Bus B
FIFO B
Out
In
SAB SBA GAB GBA
H
L
H
H
SAB SBA GAB GBA
X
L
L
H
FIFO A
Out
In
Bus A
Bus B
Bus B
FIFO B
Out
In
SAB SBA GAB GBA
L
H
H
H
SAB SBA GAB GBA
H
X
H
L
FIFO A
Out
In
FIFO A
Out
Bus A
Bus A
Bus B
Bus B
FIFO B
Out
In
FIFO B
Out
In
SAB SBA GAB GBA
X
H
L
H
SAB SBA GAB GBA
H
H
H
H
Figure 1. Bus-Management Functions
4
FIFO A
Out
Bus A
FIFO B
Out
In
In
FIFO A
Out
Bus A
FIFO B
Out
In
In
FIFO A
Out
In
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
LDCKA
DAF
RSTA
timing diagram for FIFO A†
Don’t Care
W1
W2
W32
Don’t Care
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Don’t Care
X
W2
W32−X
Don’t Care
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
W1
Don’t Care
UNCKA
Invalid
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
W3
W32
Load X Into Depth Register }
W2
Invalid
W1
Depth Set to 32 − X
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
{ Operation of FIFO B is identical to that of FIFO A.
} X includes A0 through A4 only. A5 through A8 are ignored.
FULLA
EMPTYA
Depth Set to Default (32)
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Q0 − Q8
W1
W2
W3
W32
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
A0 − A8
× × SDAS182 − APRIL 1990
ÎÎ
ÎÎ
ÎÎ
5
× × SDAS182 − APRIL 1990
SELECT-MODE CONTROL TABLE
OPERATION
CONTROL
SAB
SBA
A BUS
B BUS
L
L
Real-time B to A bus
Real-time A to B bus
L
H
FIFO B to A bus
Real-time A to B bus
H
L
Real-time B to A bus
FIFO A to B bus
H
H
FIFO B to A bus
FIFO A to B bus
OUTPUT-ENABLE CONTROL TABLE
OPERATION
CONTROL
GAB
GBA
A BUS
B BUS
H
H
A bus enabled
B bus enabled
L
H
A bus enabled
Isolation/ input to B bus
H
L
Isolation / input to A bus
B bus enabled
L
L
Isolation / input to A bus
Isolation/ input to B bus
programming procedure for depth of FIFO A†
Program:
Step 1.
With RSTA at a high level, take DAF from a high level to a low level. The high-to-low transition on
DAF stores the binary value of A0 −A4 for use as the value of X in defining the depth of FIFO A.
Step 2.
With DAF held low, pulse the RSTA signal low. On the low-to-high transition of RSTA, FIFO A is set
to a depth of 32 − X, where X is the value of A0 −A4 stored above.
Step 3.
To redefine the depth of FIFO A to 32 words, hold DAF at a high level and pulse the RSTA signal low.
† The programming procedures used to define the depth of FIFO B are the same as the procedure above.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage: Control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
× × SDAS182 − APRIL 1990
recommended operating conditions (see Note 1)
VCC
VIH
Supply voltage
VIL
Low-level input voltage
IOH
High-level output current
IOL
Low-level output current
fclock
Clock frequency
High-level input voltage
tsu
th
Setup time
Hold time
MAX
4.5
5
5.5
UNIT
V
V
0.8
A or B ports
−15
Status flags
−0.4
A or B ports
24
Status flags
8
LDCKA or LDCKB
0
40
UNCKA or UNCKB
0
40
V
mA
mA
MHz
17
LDCKA or LDCKB low
Pulse duration
NOM
2
RSTA or RSTB low
tw
MIN
12.5
LDCKA or LDCKB high
10
UNCKA or UNCKB low
12.5
UNCKA or UNCKB high
10
DAF or DBF high
10
Data before LDCKA or LDCKB↑
7
Define depth: D4 −D0 before DAF or DBF↓
6
Define depth: DAF or DBF↓ before RSTA or RSTB↑
45
Define depth (32): DAF or DBF high before RSTA or RSTB↑
32
LDCKA or LDCKB (inactive) before RSTA or RSTB↑
5
Data after LDCKA or LDCKB↑
3
Define depth: D4 −D0 after DAF or DBF↓
4
Define depth: DAF or DBF low after RSTA or RSTB↑
0
Define depth (32): DAF or DBF high after RSTA or RSTB↑
0
LDCKA or LDCKB (inactive) after RSTA or RSTB↑
5
ns
ns
ns
TA
Operating free-air temperature
0
70
°C
NOTE 1: To ensure proper operation of this high-speed FIFO device, it is necessary to provide a clean signal to the LDCKA or LDCKB and UNCKA
or UNCKB clock inputs. Any excessive noise or glitching on the clock inputs (which violates the VIL, VIH, or minimum pulse duration
limits) can cause a false clock or improper operation of the internal read and write pointers.
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
7
× × SDAS182 − APRIL 1990
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VOH
Status flags
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
II = − 18 mA
IOH = − 0.4 mA
A or B ports
VCC = 4.5 V,
VCC = 4.5 V,
IOH = − 2 mA
IOH = − 3 mA
VCC = 4.5 V,
VCC = 4.5 V,
IOH = − 15 mA
IOL = 12 mA
VCC = 4.5 V,
VCC = 4.5 V,
A or B ports
VOL
Status flags
II
DAF, DBF, RSTA, RSTB, GAB, GBA, SAB,
SBA, LDCKA, LDCKB, UNCKA, UNCKB
MIN
IIL
IO§
UNIT
−1.2
V
2.4
V
3.2
2
0.25
0.4
IOL = 24 mA
IOL = 4 mA
0.35
0.5
0.25
0.4
VCC = 4.5 V,
IOL = 8 mA
0.35
0.5
VCC = 5.5 V,
VI = 7 V
0.1
V
mA
0.2
DAF, DBF, RSTA, RSTB, GAB, GBA, SAB,
SBA, LDCKA, LDCKB, UNCKA, UNCKB
A or B ports‡
VCC = 5.5 V,
DAF, DBF, RSTA, RSTB, GAB, GBA, SAB,
SBA, LCKA, LDCKB, UNCKA, UNCKB
A or B ports‡
VCC = 5.5 V,
20
VI = 2.7 V
µA
40
−0.2
VI = 0.4 V
mA
−0.4
A or B ports‡
Status flags
MAX
VCC −2
VCC −2
A or B ports
IIH
TYP†
VCC = 5.5 V,
VO = 2.25 V
−20
−130
−15
−100
mA
ICC
VCC = 5.5 V
190
350
mA
† All typical values are at VCC = 5 V, TA = 25°C.
‡ For I/O ports, the parameters IIH and IIL include the offstate output current.
§ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
8
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
× × SDAS182 − APRIL 1990
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
(see Figure 2)
PARAMETER
fmax
FROM
(INPUT)
TO
(OUTPUT)
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω
MIN TYP†
MAX
LDCK, UNCK
40
LDCKA↑, LDCKB↑
7
22
33
7
20
29
5
12
22
5
12
22
B, A
UNIT
MHz
tpd
UNCKA↑, UNCKB↑
tPLH
tPHL
UNCKA↑, UNCKB↑
tPHL
tPHL
RSTA↓, RSTB↓
EMPTYA, EMPTYB
5
12
22
ns
LDCKA↑, LDCKB↑
FULLA, FULLB
5
12
22
ns
5
12
23
6
15
28
2
11
18
2
8
15
LDCKA↑, LDCKB↑
EMPTYA, EMPTYB
UNCKA↑, UNCKB↑
tPLH
tpd
ten
tdis
FULLA, FULLB
RSTA↓, RSTB↓
SAB, SBA‡
B, A
A/B
ns
ns
ns
ns
GBA, GAB
A, B
2
6
15
ns
GBA, GAB
A, B
1
5
12
ns
† All typical values are at VCC = 5 V, TA = 25°C.
‡ These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
9
× × SDAS182 − APRIL 1990
PARAMETER MEASUREMENT INFORMATION
7V
SWITCH POSITION TABLE
Open
S1
R1 = 500 Ω
From Output
Under Test
CL = 50 pF
(see Note A)
Test Point
R2 = 500 Ω
TEST
S1
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
Open
Open
Open
Closed
Open
Closed
LOAD CIRCUIT FOR 3-STATE OUTPUTS
3.5 V
High-Level
Pulse
1.3 V
0.3 V
tw
3.5 V
Timing
Input
1.3 V
3.5 V
Data
Input
1.3 V
1.3 V
0.3 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.3 V
1.3 V
3.5 V
Low-Level
Pulse
0.3 V
th
tsu
1.3 V
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3.5 V
Output
Control
1.3 V
tPZL
1.3 V
tPLZ
0.3 V
In-Phase
Output
Waveform 1
S1 Closed
(see Note C)
VOH
1.3 V
VOL
1.3 V
tPZH
Waveform 2
S1 Open
(see Note C)
VOH
1.3 V
1.3 V
tPHZ
tPLH
tPHL
Out-of-Phase
Output
3.5 V
tPHL
tPLH
1.3 V
0.3 V
3.5 V
Input
(see Note B)
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOL
0.3 V
VOH
1.3 V
0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
10
•
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Clocks and Timers
Interface
Logic
Power Mgmt
Microcontrollers
RFID
RF/IF and ZigBee® Solutions
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lprf
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Military
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2008, Texas Instruments Incorporated