PLL102-15 Low Skew Output Buffer FEATURES • • • • • • • Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spec trum modulation on reference clock to pass to the outputs (up to 33kHz SST modulation). Zero input - output delay. Less than 700 ps device - device skew. Less than 250 ps skew between outputs. Less than 200 ps cycle - cycle jitter. Output Enable function tri -state outputs. 3.3V operation. Available in 8 -Pin 150mil SOIC. VDD 1 CLK1 2 CLKOUT 3 GND 4 PLL102-15 • • PIN CONFIGURATION 8 N/C 7 CLK3 6 CLK2 5 REF_IN Remark If REF_IN clock is stopped for more than 10us after it has already been provided to the chip, and after power-up, the output clocks will disappear. In that instance, a full power-up reset is required in order to reactivate the output clocks. DESCRIPTIONS The PLL102 -15 is a high performance, low skew, low jitter zero delay buffer designed to di stribute high speed clocks and is available in 8 -pin SOIC or TSSOP package. It has four outputs that are synchronized with the input. The synchronization is established via CLKOUT feedback to the input of the PLL. Since the skew b etween the input and outpu t is less than ±350 ps, the device acts as a zero delay buffer. BLOCK DIAGRAM REF_IN PLL CLKOUT CLK1 CLK2 CLK3 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/06/03 Page 1 PLL102-15 Low Skew Output Buffer PIN DESCRIPTIONS Name Number Type Description VDD 1 P 3.3V Power Supply. CLK1 3 2 O Buffered clock output. CLKOUT 3 3 O Buffered clock output. Internal fe ed back on this pin. GND 4 P Ground. REF_IN 2 5 I Input reference frequency. Spread spectrum modulation on this signal will be passed to the output (up to 33kHz SST modulation). CLK2 3 6 O Buffered clock output. CLK3 3 7 O Buffered clock output. NC 8 - No connection. Notes: 2: Weak pull-down. 3: Weak pull -down on all outputs. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/06/03 Page 2 PLL102-15 Low Skew Output Buffer ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS V CC - 0.5 7 V Input Voltage Range VI - 0.5 V CC + 0.5 V Output Voltage Range VO - 0.5 V CC + 0.5 V 260 °C - 65 150 °C 0 70 °C 2 KV Supply Voltage Range Soldering Temperature Storage Temperature TS Ambient Operating Temperature ESD Voltage Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. 2. Electrical Characteristics V D D = 3.0~3.6V, unless otherwise stated PARAMETERS SYMBOL CONDITIONS MIN. TYP. UNITS 3.63 V 0.8 V Supply Voltage V DD Input Low Voltage VIL Input High Voltage V IH Input Low Current IIL V IN = 0V 19 50.0 µA Input High Current I IH V IN = V DD 0.10 100.0 µA Output Low Voltage VOL I O L = 50mA 0.25 0.4 V Output High Voltage VO H I O H = 50mA Power Down Supply Current I DD REF = 0MHz Supply Current I DD Unloaded outputs at 60MHz, SEL inputs at V DD or GND 47745 Fremont Blvd., Fremont, California 94538 2.97 MAX. 2.0 TEL (510) 492-0990 FAX (510) 492-0991 2.4 V 2.9 V 0.3 50.0 µA 30.0 40.0 mA Rev 05/06/03 Page 3 PLL102-15 Low Skew Output Buffer 3. Switching Characteristics PARAMETERS SYMBOL Output Frequency DESCRIPTION MIN. t1 TYP. 25 MAX. UNITS 60 MHz Duty Cycle ( t2 ÷ t1 ) Dt1 Measured at 1.4V, C L =30pF, Fout = 60MHz 40.0 50.0 60.0 % Duty Cycle ( t2 ÷ t1 ) Dt2 Measured at 1.4V 45.0 50.0 55.0 % Rise Time Tr Measured between 0.8V and 2.0V, C L =30pF 1.2 1.5 ns Fall Time Tf Measured between 2.0V and 0.8V, C L =30pF 1.2 1.5 ns 250 ps Output to Output Skew T skew All outputs equally loaded, C L =20p F Delay, REF Rising Edge to CLKOUT Rising Edge T delay Measured at 1.4V 0 ±350 ps 0 700 ps Device to Device Skew T dsk -dsk Measured at V DD /2 on the CLKOUT pins of devices Cycle to Cycle Jitter T cyc -cyc Loaded outputs 200 ps 1.0 ms 70 100 ps 14 30 ps PLL Lock Time T loc k Stable power supply, valid clock presented on REF pin Jitter; Absolute Jitter T jabs At 10,000 cycles, C L =30pF Jitter; 1- sima T j1 -s At 10,000 cycles, C L =30pF - 100 SWITCHING WAVEFORMS Duty Cycle Timing Output - Output Skew t1 t2 1.4V 1.4V Output 1.4V 1.4V 1.4V Output T SKEW 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/06/03 Page 4 PLL102-15 Low Skew Output Buffer SWITCHING WAVE FORMS All Outputs Rise/Fall Time 2.0V Output 3.3V 2.0V 0.8V 0.8V tr 0V tf Input to Output Propagation Delay VDD/2 Input VDD/2 Output Tdelay Device to Device Skew VDD/2 Device1 CLKOUT VDD/2 Device2 CLKOUT Tdsk - dsk 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/06/03 Page 5 PLL102-15 Low Skew Output Buffer Output-Output Skew The skew between CLKOUT and the CLK(1-3) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained from REF_IN to CLKOUT. If all outputs are equally loaded, zero phase difference will maintained from REF_IN to all outputs. If applications requiring zero output-output skew, all the outputs must equally loaded. If the CLK(1-3) outputs are less loaded than CLKOUT, CLK(1-3) outputs will lead it; if the CLK(1-3) is more loaded than CLKOUT, CLK(1-3) will lag the CLKOUT. Since the CLKOUT and the CLK(1-3) outputs are identical, they all start at the same time, but difference loads cause them to have different rise times and different times crossing the measurement thresholds. REF_IN REF_IN CLKOUT CLKOUT CLK(1-3) CLK(1-3) Zero Delay Advanced REF_IN input and all outputs loaded equally REF_IN and CLK(1-3) outputs loaded equally, with CLK(1-3) less loaded than CLKOUT. REF_IN CLKOUT CLK(1-3) Delayed REF_IN input and CLK(1-3) outputs loaded equally, with CLK(1-3) more loaded than CLKOUT. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/06/03 Page 6 PLL102-15 Low Skew Output Buffer PACKAGE INFORMATION 8 PIN Narrow SOIC ( mm ) SOIC Symbol Min. Max. A A1 B C D 1.55 0.15 0.35 0.19 4.80 1.73 0.18 0.49 0.25 4.98 E H L e 3.81 5.84 0.41 3.99 6.20 0.89 1.27 BSC E H D A A 1 C L B e ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492 - 0990 Fax: (510) 492- 0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL102-15 S C PART NUMBER TEMPERATURE C=COMMERCIAL (0°~70°C ) PACKAGE TYPE S=SOIC PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s pr oducts are not authorized for use as critical components in life support devices or systems without the ex press written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/06/03 Page 7 PLL102-15 Low Skew Output Buffer REVISION HISTORY 06/20/01 10/23/01 11/07/01 11/29/01 10/08/02 01/13/03 05/06/03 Created from preliminary PLL102 -05 and PLL102-04 Document Removed Power Down mode in absence of REF (not supported in final version). Added VDD = 3.3V in Electrical Specs for clarity. Added Remark on REF clock absence on page 1 Change pass through modulation rate from 100kHz to 33kHz. Changed Frequency range from “25-75MHz” to “25-60MHz” on Features section on page 1 Changed Supply Current (I DD ) from Unloaded outputs at “66.67MHz” to “60MHz” on page 3 Changed Max. of Output Frequency from “75” to “60” on page 4 Deleted “Fout < 50.0MHz” for Duty Cycle (Dt2) and “Measured at 60MHz” for Cycle to Cycle Jitter (Tcyc -cyc) of Switching Characteristics section on page 4 Bonding diagram modification to P102 -15 (ICS553 compatible) 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 05/06/03 Page 8