PLL PLL520-30

Preliminary
PLL520-30
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
FEATURES
65 mil
65MHz to 130MHz Fundamental Mode Crystal.
Output range: 65MHz – 130MHz (no PLL).
Low Injection Power for crystal 50uW.
Complementary outputs: PECL or LVDS.
Selectable OE Logic
Integrated variable capacitors.
Supports 2.5V or 3.3V-Power Supply.
Available in die form.
Thickness 10 mil.
25
24
23
21
22
(1550,1475)
20
19
18
17
16
26
15
27
14
28
62 mil
•
•
•
•
•
•
•
•
•
DIE CONFIGURATION
13
29
12
11
30
10
31
DESCRIPTIONS
PLL520-30 is a VCXO IC specifically designed to
pull frequency fundamental crystals from 65MHz to
130MHz, with selectable PECL or LVDS outputs and
OE logic (enable high or enable low). Its design was
optimized to tolerate higher limits of interelectrodes
capacitance and bonding capacitance to improve
yield. It achieves very low current into the crystal
resulting in better overall stability. Its internal
varicaps allow an on chip frequency pulling,
controlled by the VCON input.
BLOCK DIAGRAM
X+
X-
4
5
6
7
8
X
DIE SPECIFICATIONS
Name
Value
Size
Reverse side
62 x 65 mil
GND
Pad dimensions
80 micron x 80 micron
Thickness
10 mil
OUTPUT SELECTION AND ENABLE
Pad #9
OUTSEL
OE
Amplifier
w/
integrated
varicaps
3
(0,0)
Y
VCON Oscillator
9
2
1
0
1
Q
Q
Pad #25
OESEL
PLL520-30
Selected Output
LVDS
PECL (default)
Pad #30
OE_CTRL
0
1
(default)
0
1
0
1
State
Tri-state
Output enabled (default)
Output enabled (default)
Tri-state
Pad #9, #25 and #30: Bond to GND to set to “0”, bond to VDD to set to “1”
Pad #30: Logical states defined by PECL levels if OESEL is “1”
Logical states defined by CMOS levels if OESEL is “0”
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 4/20/04 Page 1
Preliminary
PLL520-30
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
Supply Voltage
MIN.
MAX.
UNITS
7
V
V DD
Input Voltage, dc
VI
V SS -0.5
V DD +0.5
V
Output Voltage, dc
VO
V SS -0.5
V DD +0.5
V
Storage Temperature
TS
-65
150
°C
Ambient Operating Temperature*
TA
0
70
°C
Junction Temperature
TJ
125
°C
260
°C
2
kV
Lead Temperature (soldering, 10s)
Input Static Discharge Voltage Protection
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
2. Crystal Specifications
PARAMETERS
Built-in Capacitance
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
2
CX+
CX-
Inter-electrode capacitance
C0
C0/C1 ratio (gamma)
γ
Oscillation Frequency
OF
UNITS
65MHz to 130MHz
(VDD=3.3V)
2
pF
300
-
130
MHz
2.6
Fund.
65
3. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
VCXO Tuning Range
CLK output pullability
On-chip Varicaps control range
SYMBOL
T VCXOSTB
CONDITIONS
MIN.
From power valid
XTAL C 0 /C 1 < 300
TYP.
MAX.
10
ms
200*
0V ≤ VCON ≤ 3.3V
at room temperature
VCON = 0 to 3.3V
UNITS
ppm
±100*
ppm
4 – 18*
pF
Linearity
5*
VCXO Tuning Characteristic
65
ppm/V
VCON input impedance
60
kΩ
VCON modulation BW
0V ≤ VCON ≤ 3.3V, -3dB
10*
25
%
kHz
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 4/20/04 Page 2
Preliminary
PLL520-30
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
4. General Electrical Specifications
PARAMETERS
SYMBOL
Supply Current (Loaded Outputs)
I DD
Operating Voltage
V DD
CONDITIONS
MIN.
PECL/LVDS
3.13
@ 1.25V (LVDS)
@ Vdd – 1.3V (PECL)
Output Clock Duty Cycle
TYP.
45
45
50
50
MAX.
UNITS
100/80
mA
3.47
V
55
55
%
±50
Short Circuit Current
mA
5. Jitter specifications
PARAMETERS
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Period jitter RMS
77.76MHz
3.5*
ps
Period jitter peak-to-peak
77.76MHz
24*
ps
Integrated jitter RMS
Integrated 12 kHz to 20 MHz at 77.76MHz
0.5*
ps
*: To be measured
6. Phase noise specifications
PARAMETERS
Phase Noise
relative to carrier
FREQUENCY
@10Hz
@100Hz
@1kHz
@10kHz
@100kHz
UNITS
77.76MHz
-75
-95
-125
-145
-155
dBc/Hz
Note: Phase Noise at VCON = 0V – to be measured
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 4/20/04 Page 3
Preliminary
PLL520-30
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
7. LVDS Electrical Characteristics
PARAMETERS
SYMBOL
Output Differential Voltage
V DD Magnitude Change
MIN.
TYP.
MAX.
UNITS
V OD
247
355
454
mV
∆V OD
-50
50
mV
1.6
V
Output High Voltage
V OH
Output Low Voltage
V OL
Offset Voltage
CONDITIONS
1.4
R L = 100 Ω
(see figure)
0.9
1.1
V OS
1.125
1.2
1.375
V
Offset Magnitude Change
∆V OS
0
3
25
mV
Power-off Leakage
I OXD
±1
±10
uA
Output Short Circuit Current
I OSD
-5.7
-8
mA
V out = V DD or GND
V DD = 0V
V
8. LVDS Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Differential Clock Rise Time
tr
0.2
0.7
1.0
ns
Differential Clock Fall Time
tf
R L = 100 Ω
C L = 10 pF
(see figure)
0.2
0.7
1.0
ns
LVDS Levels Test Circuit
LVDS Switching Test Circuit
OUT
OUT
CL = 10pF
50Ω
VOD
VDIFF
VOS
RL = 100Ω
50Ω
CL = 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
0V (Differential)
OUT
80%
VDIFF
80%
0V
20%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 4/20/04 Page 4
Preliminary
PLL520-30
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
9. PECL Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
MAX.
UNITS
Output High Voltage
V OH
V DD – 1.025
V DD – 0.750
V
Output Low Voltage
V OL
R L = 50 Ω to (V DD – 2V)
(see figure)
V DD – 1.900
V DD – 1.620
V
10. PECL Switching Characteristics
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Clock Rise Time
tr
@20/80% - PECL
0.3
0.6
1.5
ns
Clock Fall Time
tf
@80/20% - PECL
0.3
0.5
1.5
ns
PECL Levels Test Circuit
OUT
PECL Output Skew
VDD
50Ω
OUT
2.0V
50%
50Ω
OUT
tSKEW
OUT
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
tR
tF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 4/20/04 Page 5
Preliminary
PLL520-30
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
PAD ASSIGNMENT
Pad #
Name
X (µm)
Y (µm)
1
Optional GND
248
109
2
Optional GND
361
109
3
Optional GND
473
109
4
Optional GND
587
109
5
GND
702
109
6
Reserved
874
109
7
Optional GNDBUF
1042
109
8
GNDBUF
1171
109
9
OUTSEL
1400
125
10
LVDS
1400
259
11
PECL
1400
476
12
VDDBUF
1400
616
13
Optional VDDBUF
1400
716
14
PECLB
1400
871
15
LVDSB
1400
1089
16
Not connected
1400
1227
17
GNDBUF
1389
1365
18
Reserved
1232
1365
19
Reserved
1042
1365
20
Not connected
854
1365
21
Optional VDD
659
1365
22
Optional VDD
559
1365
23
VDD
459
1365
24
Optional VDD
358
1365
25
OESEL
194
1365
26
XIN
109
1223
27
XOUT
109
1017
28
Not connected
109
858
29
Not connected
109
646
30
OE_CTRL
109
397
31
VCON
109
181
Note: for optimal Phase Noise performance, it is recommended to bond all optional VDD and GND pads.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 4/20/04 Page 6
Preliminary
PLL520-30
PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
ORDERING INFORMATION
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL520-30 D C
PART NUMBER
TEMPERATURE
C=COMMERCIAL
PACKAGE TYPE
D=DIE
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 4/20/04 Page 7