PROTEC PA5155

ANALOG PRODUCTS DIVISION
FEATURES
GENERAL DESCRIPTION
DAC
24-bit, 8 kHz to 96 kHz sampling frequency
96 dB dynamic range, 96 dB signal to noise ratio, -83 dB
THD+N
40 mW headphone amplifier, pop noise free, capless
option
Stereo enhancement
Bass and Treble adjustments
Various analog output mixing and gains
PA5155 is a high performance, low power and low cost audio
DAC. It consists of 2-ch DAC, headphone amplifier, digital
sound effects, and analog mixing and gain functions.
The device uses advanced multi-bit delta-sigma modulation
technique to convert data between digital and analog.
The multi-bit delta-sigma modulators make the device with low
sensitivity to clock jitter and low out of band noise.
Low Power
1.8V to 3.3V operation
7 mW playback
VMID
VREF
GND
HPGND
AVDD
AGND
HPVDD
BLOCK DIAGRAM
DGND
APPLICATIONS
PVDD
System
2
I C or SPI uC interface
256Fs, 384Fs, USB 12 MHz or 24 MHz
Master or slave serial port
2
I S, Left Justified, DSP/PCM Mode
Fractional PLL for wide range of system clocks
DVDD
LIN
GPS
Bluetooth
MP3, MP4, PMP
Cell phone
Digital camera, camcorder
Portable audio devices
MONO
mixL
+
DACL
mixL
LOUT1
mixR
ROUT1
mixL
LOUT2
DACR
LIN
RIN
Stereo
Enhance
LIN
DACL
DAC
RIN
DACR DACL
mixM
+
DACR
+/-mixR
ROUT2
mixM
MOUT
RIN
MONO
D2S
mixR
+
DACL
VREF
ROUT1
DACR
MOUT
SCLK
DSDIN
Serial Audio Data
DLRCK
CDATA
CCLK
E
µC Interface
CE
PLL
ORDERING INFORMATION
Temperature Range
-40 to 85 °C
Package
Part Number
QFN-28
PA5155-T7
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
95244 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
MUX
MONO
MONO+
MONO-
MCLK
95244
PA5155
Low Power Stereo Audio CODEC
With Headphone Amplifier
OUT3
PA5155
Low Power Stereo Audio CODEC
With Headphone Amplifier
ANALOG PRODUCTS DIVISION
28
27
26
25
24
23
22
CCLK
CDATA
CE
DC
LIN
RIN
MONO+
28-PIN QFN AND PIN DESCRIPTIONS
1
2
3
4
5
6
7
21
20
19
18
17
16
15
MONOVMID
VREF
AGND
AVDD
HPVDD
LOUT2
GND
MOUT
OUT3
ROUT1
LOUT1
HPGND
ROUT2
8
9
10
11
12
13
14
MCLK
DVDD
PVDD
DGND
SCLK
DSDIN
DLRCK
PIN
NAME
I/O
1
MCLK
I
2
DVDD
Supply
Digital core supply
3
PVDD
Supply
Digital IO supply
4
DGND
Supply
Digital ground (return path for both DVDD and PVDD)
5
SCLK
I/O
6
DSDIN
I
7
DLRCK
I/O
8
GND
9
MOUT
O
Mono output
10
OUT3
O
Analog output 3 (can be used as headphone pseudo ground)
11
ROUT1
O
Right output 1 (line or speaker/headphone)
12
LOUT1
O
Left output 1 (line or speaker/headphone)
13
HPGND
Supply
14
ROUT2
O
Right output 2 (line or speaker/headphone)
15
LOUT2
O
Left output 2 (line or speaker/headphone)
16
HPVDD
Supply
Supply for analog output drivers (LOUT1/2, ROUT1/2)
17
AVDD
Supply
Analog supply
18
AGND
Supply
Analog ground
19
VREF
O
Decoupling capacitor
20
VMID
O
Decoupling capacitor
21
MONO-
I
Mono input (negative side)
22
MONO+
I
Mono input (positive side)
23
RIN
I
Right channel input
24
LIN
I
Left channel input
25
NU
26
CE
27
CDATA
28
CCLK
Supply
DESCRIPTION
Master clock
Audio data bit clock
DAC audio data
DAC audio data left and right clock
Ground or no connect
Ground for analog output drivers (LOUT1/2, ROUT1/2)
Not used by chip (arbitrary connection)
I
I/O
I
Control select or device address selection
Control data input or output
Control clock input
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
95244 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5155
Low Power Stereo Audio CODEC
With Headphone Amplifier
ANALOG PRODUCTS DIVISION
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Supply Voltage …………………………. MIN-0.3V MAX +5.0V
Input Voltage ………………… MIN GND-0.3V MAX VDD+0.3V
Operating Temperature………………..MIN -40°C MAX +85°C
Storage Temperature…………………MIN -65°C MAX +150°C
Analog Supply Voltage ……………….… MIN 1.7V MAX 3.6V
Digital Supply Voltage ………………….. MIN 1.5V MAX 3.6V
Note: Continuous operation at or beyond these conditions may
permanently damage the device.
DAC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS
Test conditions are as the following unless otherwise specify:
AVDD=+3.3V, DVDD=+1.8V, AGND=0V, DGND=0V, Ambient temperature=+25 C, Fs=48 KHz, 96 KHz or 192 KHz, MCLK/LRCK=256.
PARAMETER
MIN
TYP
MAX
UNIT
Dynamic Range (Note 1)
83
96
98
dB
THD+N
-85
-83
-75
dB
Channel Separation (1KHz)
80
85
90
dB
Signal to Noise ratio
83
96
98
dB
DAC Performance
Inter-channel Gain Mismatch
0.05
dB
Filter Frequency Response – Single Speed
Passband
0
Stopband
0.5465
0.4535
Fs
Fs
Passband Ripple
±0.05
Stopband Attenuation
dB
40
dB
Filter Frequency Response – Double Speed
Passband
0
Stopband
0.5833
Fs
±0.005
dB
Fs
Passband Ripple
Stopband Attenuation
0.4167
40
dB
De-emphasis Error at 1 KHz (Single Speed Mode Only)
Fs = 32KHz
Fs = 44.1KHz
Fs = 48KHz
Analog Output
0.002
0.013
0.0009
Full Scale Output Level
AVDD/3.3
dB
Vrms
Note
1. The value is measured used A-weighted filter.
POWER CONSUMPTION CHARACTERISTICS
PARAMETER
MIN
TYP
MAX
UNIT
Normal Operation Mode
DVDD=1.8V, AVDD=1.8V:
Play back
DVDD=3.3V, AVDD=3.3V:
Play back
31
Power Down Mode
DVDD=1.8V, AVDD=1.8V
DVDD=3.3V, AVDD=3.3V
0.3
1.9
7
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
95244 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
mW
mW
PA5155
Low Power Stereo Audio CODEC
With Headphone Amplifier
ANALOG PRODUCTS DIVISION
SERIAL AUDIO PORT SWITCHING SPECIFICATIONS
PARAMETER
Symbol
MIN
MCLK frequency
MCLK duty cycle
40
LRCK frequency
LRCK duty cycle
40
SCLK frequency
MAX
UNIT
51.2
MHz
60
%
200
KHz
60
%
26
MHz
SCLK pulse width low
TSCLKL
15
ns
SCLK Pulse width high
TSCLKH
15
ns
SCLK falling to LRCK edge
TSLR
–10
SDIN valid to SCLK rising setup time
TSDIS
10
ns
SCLK rising to SDIN hold time
TSDIH
10
ns
10
ns
LRCK
Input
tslr
tsclkh
tsclkl
SLCK
Input
tsdo
tsclkw
SDOUT
tsdis
tsdih
SDIN
Serial Audio Port Timing
SERIAL CONTROL PORT SWITCHING SPECIFICATIONS
PARAMETER
Symbol
MIN
MAX
UNIT
10
MHz
SPI Mode
SPI_CLK clock frequency
SPI_CLK edge to SPI_CSn falling
TSPICS
5
ns
SPI_CSn High Time Between transmissions
TSPISH
500
ns
SPI_CSn falling to SPI_CLK edge
TSPISC
10
ns
SPI_CLK low time
TSPICL
45
ns
SPI_CLK high time
TSPICH
45
ns
SPI_DIN to SPI_CLK rising setup time
TSPIDS
10
ns
SPI_CLK rising to DATA hold time
TSPIDH
15
ns
2-wire Mode
SCL Clock Frequency
Bus Free Time Between Transmissions
FSCL
100
KHz
TTWID
4.7
us
Start Condition Hold Time
TTWSTH
4.0
us
Clock Low time
TTWCL
4.0
us
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
95244 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5155
Low Power Stereo Audio CODEC
With Headphone Amplifier
ANALOG PRODUCTS DIVISION
Clock High Time
TTWCH
4.0
us
Setup Time for Repeated Start Condition
TTWSTS
4.7
us
SDA Hold Time from SCL Falling
TTWDH
0.1
us
SDA Setup time to SCL Rising
TTWDS
100
ns
Rise Time of SCL
TTWR
25
us
Fall Time SCL
TTWF
25
ns
TSPIDS
TSPIDH
SPI_DIN
TSPICL
TSPICH
SPI_CLK
SPI_CSn
TSPISH
TSPICS
TSPISC
Serial Control Port SPI Timing
SDA
TTWSTS
TTWSTH
TTWCL
SCL
TTWDH
TTWID
TTWDS
TTWCH
S
TTWF TTWR
P
S
Serial Control Port 2-wire Timing
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
95244 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5155
Low Power Stereo Audio CODEC
With Headphone Amplifier
ANALOG PRODUCTS DIVISION
TYPICAL APPLICATION CIRCUIT
CLOCK MODES AND SAMPLING FREQUENCIES
According to the input serial audio data sampling frequency, the device can work in two speed modes: single speed or double speed.
The ranges of the sampling frequency in these two modes are listed in Table 1. The device can work either in master clock mode or
slave clock mode.
In slave mode, LRCK and SCLK are supplied externally. LRCK and SCLK must be synchronously derived from the system clock with
specific rates. The device can auto detect MCLK/LRCK ratio according to Table 1. The device only supports the MCLK/LRCK ratios
listed in Table 1. The LRCK/SCLK ratio is normally 64.
Table 1 Slave Mode Sampling Frequencies and MCLK/LRCK Ratio
Speed Mode
Sampling Frequency
MCLK/LRCK Ratio
Single Speed
8kHz – 50kHz
256, 384, 512, 768, 1024
Double Speed
50kHz – 100kHz
128, 192, 256, 384, 512
In master mode, LRCK and SCLK are derived internally from MCLK. The available MCLK/LRCK ratios and SCLK/LRCK ratios are
listed in Table 2.
Table 2 Master Mode Sampling Frequencies and MCLK/LRCK Ratio
MCLK
MCLK
CLKDIV2=0 CLKDIV2=1
Normal Mode
12.288 MHz 24.576MHz
DAC Sample Rate
(DLRCK)
DACFsRatio
[4:0]
SCLK
Ratio
8 kHz (MCLK/1536)
48 kHz (MCLK/256)
12 kHz (MCLK/1024)
16 kHz (MCLK/768)
24 kHz (MCLK/512)
32 kHz (MCLK/384)
01010
00010
00111
00110
00100
00011
MCLK/6
MCLK/4
MCLK/4
MCLK/6
MCLK/4
MCLK/6
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
95244 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5155
Low Power Stereo Audio CODEC
With Headphone Amplifier
ANALOG PRODUCTS DIVISION
11.2896 MHz 22.5792MHz
18.432 MHz
36.864MHz
16.9344 MHz 33.8688MHz
USB Mode
12 MHz
24MHz
8 kHz (MCLK/1536)
48 kHz (MCLK/256)
96 kHz (MCLK/128)
8.0182 kHz (MCLK/1408)
44.1 kHz (MCLK/256)
11.025 kHz (MCLK/1024)
22.05 kHz (MCLK/512)
8.0182 kHz (MCLK/1408)
44.1 kHz (MCLK/256)
88.2 kHz (MCLK/128)
8 kHz (MCLK/2304)
48 kHz (MCLK/384)
12 kHz (MCLK/1536)
16 kHz (MCLK/1152)
24 kHz (MCLK/768)
32 kHz (MCLK/576)
8 kHz (MCLK/2304)
48 kHz (MCLK/384)
96 kHz (MCLK/192)
8.0182 kHz (MCLK/2112)
44.1 kHz (MCLK/384)
11.025 kHz (MCLK/1536)
22.05 kHz (MCLK/768)
8.0182 kHz (MCLK/2112)
44.1 kHz (MCLK/384)
88.2 kHz (MCLK/192)
01010
00010
00000
01001
00010
00111
00100
01001
00010
00000
01100
00011
01010
01000
00110
00101
01100
00011
00001
01011
00011
01010
00110
01011
00011
00001
MCLK/4
MCLK/4
MCLK/2
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/4
MCLK/2
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/3
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/6
MCLK/3
8 kHz (MCLK/1500)
48 kHz (MCLK/250)
8.0214 kHz (MCLK/1496)
44.118 kHz (MCLK/272)
11.0259 kHz (MCLK/1088)
12 kHz (MCLK/1000)
16 kHz (MCLK/750)
22.0588 kHz (MCLK/544)
24 kHz (MCLK/500)
32 kHz (MCLK/375)
8.0214 kHz (MCLK/1496)
44.118 kHz (MCLK/272)
8 kHz (MCLK/1500)
48 kHz (MCLK/250)
88.235 kHz (MCLK/136)
96 kHz (MCLK/125)
11011
10010
11010
10011
11001
11000
10111
10110
10101
10100*
11010
10011
11011
10010
10001
10000
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
MCLK
PA5155 has a high performance fractional-N PLL. PLL can be used for non-standard MCLK to generate standard internal master
clock, for example 12.288 MHz for 48 kHz sampling frequency or 11.2896 MHz for 44.1 kHz sampling frequency. By default, PLL is in
power down and reset, and the internal master clock uses MCLK clock from pin directly. The following table shows the PLL setting
(MCLKDIV2, PLL_N, PLL_K and PLLOUT_DIV2) for typical non-standard MCLK to generate standard internal master clock.
F2
(MHz)
MCLKDIV2
PLLOUT_DIV2
R
N
f (*0.6574)
PLL_N
PLL_K
11.91
Internal
Master
Clock
(MHz)
11.2896
90.3168
0
1
7.5833
7
0.3834
7
188A3F
11.91
12.288
98.304
0
1
8.2539
8
0.1669
8
AAE8C
12
11.2896
90.3168
0
1
7.5264
7
0.3460
7
16256C
MCLK
(MHz)
12
12.288
98.304
0
1
8.192
8
0.1262
8
813E0
13
11.2896
90.3168
0
1
6.9474
6
0.6228
6
27DBAB
13
12.288
98.304
0
1
7.5618
7
0.3693
7
17A2B0
14.4
11.2896
90.3168
0
1
6.272
6
0.1788
6
B717D
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
95244 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5155
Low Power Stereo Audio CODEC
With Headphone Amplifier
ANALOG PRODUCTS DIVISION
14.4
12.288
98.304
0
1
6.8267
6
0.5434
6
22C7B5
19.2
11.2896
90.3168
1
1
9.408
9
0.2682
9
112A3C
19.2
12.288
98.304
1
1
10.24
10
0.1578
A
A18D8
19.68
11.2896
90.3168
1
1
9.1785
9
0.1173
9
7827A
19.68
12.288
98.304
1
1
9.9902
9
0.6509
9
29A8A2
19.8
11.2896
90.3168
1
1
9.1229
9
0.0808
9
52BA7
19.8
12.288
98.304
1
1
9.9297
9
0.6111
9
271D0A
24
11.2896
90.3168
1
1
7.5264
7
0.3460
7
16.256C
24
12.288
98.304
1
1
8.192
8
0.1262
8
813E0
26
11.2896
90.3168
1
1
6.9474
6
0.6228
6
27DBAB
26
12.288
98.304
1
1
7.5618
7
0.3693
7
17A2B0
27
11.2896
90.3168
1
1
6.6901
6
0.4536
6
1D0880
27
12.288
98.304
1
1
7.2818
7
0.1852
7
BDB09
MICRO-CONTROLLER CONFIGURATION INTERFACE
The device supports standard SPI and 2-wire micro-controller configuration interface. External micro-controller can completely
configure the device through writing to internal configuration registers. Please see section 8 for the details of configuration register
definition.
The identical device pins are used to configure either SPI or 2-wire interface. In SPI mode, pin CE, CCLK and CDATA function as
SPI_CSn, SPI_CLK and SPI_DIN. In 2-wire mode, pin CE, CCLK and CDATA function as AD0, SCL and SDA. To select SPI mode,
apply high to low transition signal to CE pin. Otherwise the device will operate in 2-wire interface mode.
SPI
PA5155 has a SPI (Serial Peripheral Interface) compliant synchronous serial slave controller inside the chip. It provides the ability to
allow the external master SPI controller to access the internal registers, and thus control the operations of chip.
All lines on the SPI bus are unidirectional: The SPI_CLK is generated by the master controller and is primarily used to synchronize
data transfer, the SPI_DIN line carries data from the master to the slave; SPI_CSn is generated by the master to select PA5155.
The timing diagram of this interface is given in Figure 1. The high to low transition at SPI_CSn pin indicates the SPI interface
selected. Each write procedure contains 3 words, i.e. Chip Address plus R/W bit, internal register address and internal register data.
Every word length is fixed at 8 bits. The input SPI_DIN data are sampled at the rising edge of SPI_CLK clock. The MSB bit in each
word is transferred firstly. The transfer rate can be up to 10Mbps.
SPI_DIN
Chip Address
7 bits - 0010000
0
1
5
R/
Wb
6
7
RAM
8 bits
8
9
14
Register Data
8 bits
15
16
17
22
23
SPI_CLK
SPI_CSn
RAM = Register Address Mapping
Figure 1 SPI Configuration Interface Timing Diagram
2-WIRE
2-wire interface is a bi-directional serial bus that uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. The
timing diagram for data transfer of this interface is given in Figure 2. Data are transmitted synchronously to SCL clock on the SDA line
on a byte-by-byte basis. Each bit in a byte is sampled during SCL high with MSB bit being transmitted firstly. Each transferred byte is
followed by an acknowledge bit from receiver to pull the SDA low. The transfer rate of this interface can be up to 100k bps.
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
95244 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5155
ANALOG PRODUCTS DIVISION
Low Power Stereo Audio CODEC
With Headphone Amplifier
Figure 2 Complete Data Transfer for 2-wire Interface
A master controller initiates the transmission by sending a “start” signal, which is defined as a high-to-low transition at SDA while SCL
is high. The first byte transferred is the slave address. It is a seven-bit chip address followed by a RW bit. The chip address must be
001000x,where x equals AD0 (pin CE). The RW bit indicates the slave data transfer direction. Once an acknowledge bit is received,
the data transfer starts to proceed on a byte-by-byte basis in the direction specified by the RW bit. The master can terminate the
communication by generating a “stop” signal, which is defined as a low-to-high transition at SDA while SCL is high.
In 2-wire interface mode, the registers can be written and read. The formats of “write” and “read” instructions are shown in Table 3
and Table 4. Please note that, to read data from a register, you must set R/W bit to 0 to access the register address and then set R/W
to 1 to read data from the register. There are no acknowledge bit after data to be written or read, this is the only difference from the
2
I C protocol.
Table 3 Write Data to Register in 2-wire Interface Mode
Chip Address
001000
R/W
Chip Address
001000
Chip Address
001000
R/W
AD0
Register Address
Data to be written
0
ACK
RAM
ACK
DATA
Table 4 Read Data from Register in 2-wire Interface Mode
Register Address
AD0
0
ACK
RAM
R/W
Data to be read
AD0
1
ACK
DATA
CONFIGURATION REGISTER DEFINITION
SPI and 2-wire configuration interface share the same registers because there is only one interface active at any time. There are total
of 53 user programmable 8-bit registers in this device. These registers control the operations of DAC. External master controller can
access these registers by using the slave address specified in RAM (Register Address Map) register as shown in the Table 5.
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
95244 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5155
Low Power Stereo Audio CODEC
With Headphone Amplifier
ANALOG PRODUCTS DIVISION
Table 5 Bit Content of Register Address Map
Adr
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
Name
Bit7
Bit6
LOUT1 Volume
LP_OUT1
PDN_LOUT1
ROUT1 Volume
PDN_ROUT1
LOUT2 Volume
LP_OUT2
PDN_LOUT2
Output
ROUT2 Volume
PDN_ROUT2
Setting
MOUT Volume
LP_MOUT
PDN_MOUT
OUT Control 1
LP_OUT3
PDN_OUT3
OUT Control 2
Left Mixer
LI2LOMU
Right Mixer
MI2ROMU
Mixer
Mono Mixer
LI2MOMU
Setting
DAC to Mixer PDN_MONODIFF
DMEN
Mixer LP mode
Left DAC Volume
Right DAC
Volume
DAC Control
LP_DACL
PDN_DACL
DAC Control
AUTOMUTE CLICKFREE
DAC Control
DAC Control
Shelving1_A
DAC
Setting
Shelving1_B
Shelving2_A
Shelving2_B
95244 Rev.0. 01/10
Bit5
Bit4
OUT3SW
LI2LOVOL
MI2ROVOL
LI2MOVOL
LD2MOMU
Bit3
Bit2
LOUT1VOL
ROUT1VOL
LOUT2VOL
ROUT2VOL
MOUTVOL
LP_ROUT2INV
ROUT2INV
MI2LOMU
RI2ROMU
RI2MOMU
RD2MOMU
LD2LOMU
LP_MONODIFF
DACLVOL
RD2LOMU
LP_MMIX
Bit1
L2R2BOTH
MI2LOVOL
RI2ROVOL
RI2MOVOL
LD2ROMU
LP_LMIX
default
40
40
40
40
40
40
L1R1BOTH 00
FF
FF
FF
RD2ROMU BF
LP_RMIX
00
C0
DACRVOL
LP_DACR
PDN_DACR
VPPSCALE
DACINVL
DACINVR
DACZEROL
DACZEROR
DACLMU
DACLRBOTH DACSOFTRAMP
DACTOEN
DACDAT
DACMONO
SHV1_A[29:24]
SHV1_A[23:16]
SHV1_A[15:8]
SHV1_A[7:0]
SHV1_B[29:24]
SHV1_B[23:16]
SHV1_B[15:8]
SHV1_B[7:0]
SHV2_A[29:24]
SHV2_A[23:16]
SHV2_A[15:8]
SHV2_A[7:0]
SHV2_B[29:24]
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
NOT FOR USE IN LIFE SUPPORT SYSTEMS
Bit0
C0
DACRMU
DACRAMPRATE
DACSE
55
C4
08
00
1F
F7
FD
FF
1F
F7
FD
FF
1F
F7
FD
FF
1F
PA5155
ANALOG PRODUCTS DIVISION
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
Low Power Stereo Audio CODEC
With Headphone Amplifier
SHV2_B[23:16]
SHV2_B[15:8]
SHV2_B[7:0]
SHV3_A[29:24]
SHV3_A[23:16]
SHV3_A[15:8]
SHV3_A[7:0]
Shelving3_A
Shelving3_B
Digital
Audio
I/F
Setting
31 Reference
32 Setting
33
34
35
36
37
PLL
38
Setting
39
3A
3B
Adr
0
1
Output
2 Setting
3
Digital Interface
Digital Interface
Sample Rate
SCLK Divider
Reset
Power Down
Reference
Reference
Reference
Reference
Reference
Reference
PLL Control
PLL Control
PLL Control
PLL Control
PLL Control
PLL Control
Name
LOUT1 Volume
ROUT1 Volume
LOUT2 Volume
ROUT2 Volume
95244 Rev.0. 01/10
DACFORMAT
SHV3_B[29:24]
SHV3_B[23:16]
SHV3_B[15:8]
SHV3_B[7:0]
DACLRSWP
DACLRP
MCLKDIV2
SCLKINV
DACSR
SCLKDIV
DACWL
FSMODE
DACMSC
RST_CP
PDN_ANA
IBIASSW
MOUT_REF2
pdn
Bit7
LP_OUT1
LP_OUT2
PDN_DIG
PDN_DLL
SEQEN
ENREFR
VROI
VMIDSEL
VMIDLOW
28
PDN_VREFGEN PDN_IBIASGEN LP_DACVRP LP_VREFBUF PDN_VREFBUF VREFR_LO 34
VSEL
FC
MOUT_REF1 OUT3_REF2
OUT3_REF1
OUT2_REF2
OUT2_REF1
OUT1_REF2 OUT1_REF1 55
MONO_REF2 MONO_REF1
MIX_REF2
MIX_REF1
05
cp2
cp1
cp0
SupSel1
SupSel0
kvco1
kvco0
08
LP
MCLKSEL
PLLOUT_DIV2
PLL_RB
PLL_EN
00
DITH_MAG
PLL_N
00
PLL_K[21:16]
00
PLL_K[15:8]
00
PLL_K[7:0]
00
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
default
PDN_LOUT1
LOUT1VOL
40
PDN_ROUT1
ROUT1VOL
40
PDN_LOUT2
LOUT2VOL
40
PDN_ROUT2
ROUT2VOL
40
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PDN_FSM
F7
FD
FF
1F
F7
FD
FF
1F
F7
FD
FF
00
01
06
00
00
0C
00
PA5155
Low Power Stereo Audio CODEC
With Headphone Amplifier
ANALOG PRODUCTS DIVISION
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
MOUT Volume
LP_MOUT
PDN_MOUT
OUT Control 1
LP_OUT3
PDN_OUT3
OUT Control 2
Left Mixer
LI2LOMU
Right Mixer
MI2ROMU
Mixer
Mono Mixer
LI2MOMU
Setting
DAC to Mixer PDN_MONODIFF
DMEN
Mixer LP mode
Left DAC Volume
Right DAC
Volume
DAC Control
LP_DACL
PDN_DACL
DAC Control
AUTOMUTE CLICKFREE
DAC Control
DAC Control
Shelving1_A
DAC
Setting
Shelving1_B
Shelving2_A
Shelving2_B
Shelving3_A
95244 Rev.0. 01/10
MOUTVOL
LP_ROUT2INV
ROUT2INV
OUT3SW
LI2LOVOL
MI2ROVOL
LI2MOVOL
LD2MOMU
MI2LOMU
RI2ROMU
RI2MOMU
RD2MOMU
LD2LOMU
LP_MONODIFF
DACLVOL
RD2LOMU
LP_MMIX
L2R2BOTH
MI2LOVOL
RI2ROVOL
RI2MOVOL
LD2ROMU
LP_LMIX
RD2ROMU
LP_RMIX
DACRVOL
LP_DACR
PDN_DACR
VPPSCALE
DACINVL
DACINVR
DACZEROL
DACZEROR
DACLMU
DACLRBOTH DACSOFTRAMP
DACTOEN
DACDAT
DACMONO
SHV1_A[29:24]
SHV1_A[23:16]
SHV1_A[15:8]
SHV1_A[7:0]
SHV1_B[29:24]
SHV1_B[23:16]
SHV1_B[15:8]
SHV1_B[7:0]
SHV2_A[29:24]
SHV2_A[23:16]
SHV2_A[15:8]
SHV2_A[7:0]
SHV2_B[29:24]
SHV2_B[23:16]
SHV2_B[15:8]
SHV2_B[7:0]
SHV3_A[29:24]
SHV3_A[23:16]
SHV3_A[15:8]
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
NOT FOR USE IN LIFE SUPPORT SYSTEMS
L1R1BOTH
40
40
00
FF
FF
FF
BF
00
C0
C0
DACRMU
DACRAMPRATE
DACSE
55
C4
08
00
1F
F7
FD
FF
1F
F7
FD
FF
1F
F7
FD
FF
1F
F7
FD
FF
1F
F7
FD
PA5155
ANALOG PRODUCTS DIVISION
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
Low Power Stereo Audio CODEC
With Headphone Amplifier
SHV3_A[7:0]
SHV3_B[29:24]
Shelving3_B
Digital
Audio
I/F
Setting
31 Reference
32 Setting
33
34
35
36
37
PLL
38
39 Setting
3A
3B
Digital Interface
Digital Interface
Sample Rate
SCLK Divider
Reset
Power Down
Reference
Reference
Reference
Reference
Reference
Reference
PLL Control
PLL Control
PLL Control
PLL Control
PLL Control
PLL Control
95244 Rev.0. 01/10
DACFORMAT
SHV3_B[23:16]
SHV3_B[15:8]
SHV3_B[7:0]
DACLRSWP
DACLRP
MCLKDIV2
SCLKINV
DACSR
SCLKDIV
DACWL
FSMODE
DACMSC
RST_CP
PDN_ANA
IBIASSW
MOUT_REF2
pdn
PDN_DIG
PDN_DLL
SEQEN
ENREFR
VROI
VMIDSEL
VMIDLOW
28
PDN_VREFGEN PDN_IBIASGEN LP_DACVRP LP_VREFBUF PDN_VREFBUF VREFR_LO 34
VSEL
FC
MOUT_REF1 OUT3_REF2
OUT3_REF1
OUT2_REF2
OUT2_REF1
OUT1_REF2 OUT1_REF1 55
MONO_REF2 MONO_REF1
MIX_REF2
MIX_REF1
05
cp2
cp1
cp0
SupSel1
SupSel0
kvco1
kvco0
08
LP
MCLKSEL
PLLOUT_DIV2
PLL_RB
PLL_EN
00
DITH_MAG
PLL_N
00
PLL_K[21:16]
00
PLL_K[15:8]
00
PLL_K[7:0]
00
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PDN_FSM
FF
1F
F7
FD
FF
00
01
06
00
00
0C
00
PA5155
ANALOG PRODUCTS DIVISION
Low Power Stereo Audio CODEC
With Headphone Amplifier
OUTPUT SETTINGS
Register 0 – LOUT1 Volume, Default 0100 0000
Bit Name
Bit
Description
LP_LOUT1
7
0 – normal (default)
1 – low power setting for LOUT1
PDN_LOUT1 6
0 – not power down
1 – power down LOUT1 (default)
LOUT1VOL
5:0
LOUT1 volume control
000000 – -45 dB (default)
000001 – -43.5 dB
000010 – -42 dB
…
011110 – 0 dB
011111 – 1.5 dB
…
100100 – 9 dB
Register 1 – ROUT1 Volume, Default 0100 0000
Bit Name
Bit
Description
LP_ROUT1
7
0 – normal (default)
1 – low power setting for ROUT1
PDN_ROUT1
6
0 – not power down
1 – power down ROUT1 (default)
ROUT1VOL
5:0
ROUT1 volume control
000000 – -45 dB (default)
000001 – -43.5 dB
000010 – -42 dB
…
011110 – 0 dB
011111 – 1.5 dB
…
100100 – 9 dB
Register 2 – LOUT2 Volume, Default 0100 0000
Bit Name
Bit
Description
LP_LOUT2
7
0 – normal (default)
1 – low power setting for LOUT2
PDN_LOUT2
6
0 – not power down
1 – power down LOUT2 (default)
LOUT2VOL
5:0
LOUT2 volume control
000000 – -45 dB (default)
000001 – -43.5 dB
000010 – -42 dB
…
011110 – 0 dB
011111 – 1.5 dB
…
100100 – 9 dB
Register 3 – ROUT2 Volume, Default 0100 0000
Bit Name
Bit
Description
LP_ROUT2
7
0 – normal (default)
1 – low power setting for ROUT2
PDN_ROUT2
6
0 – not power down
1 – power down ROUT2 (default)
ROUT2VOL
5:0
ROUT2 volume control
000000 – -45 dB (default)
000001 – -43.5 dB
000010 – -42 dB
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
95244 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5155
ANALOG PRODUCTS DIVISION
Low Power Stereo Audio CODEC
With Headphone Amplifier
…
011110 – 0 dB
011111 – 1.5 dB
…
100100 – 9 dB
Register 4 – MOUT Volume, Default 0100 0000
Bit Name
Bit
Description
LP_MOUT
7
0 – normal (default)
1 – low power setting for Mono Out
PDN_MOUT
6
0 – not power down
1 – power down mono out (default)
MOUTVOL
5:0
Mono Out volume control
000000 – -45 dB (default)
000001 – -43.5 dB
000010 – -42 dB
…
011110 – 0 dB
011111 – 1.5 dB
…
100100 – 9 dB
Register 5 – Out Control 1, Default 0100 0000
Bit Name
Bit
Description
LP_OUT3
7
0 – normal (default)
1 – low power setting for OUT3
PDN_OUT3
6
0 – not power down
1 – power down OUT3 (default)
OUT3SW
5:4
OUT3 select
00 – VREF (default)
01 – ROUT1 signal
10 – MONOOUT
11 – right mixer output
LP_ROUT2INV
3
0 – normal (default)
1 – low power setting for ROUT2INV
ROUT2INV
2
0 – no Inversion (default)
1 – ROUT2 signal inverted
Register 6 – Out Control 2, Default 0000 0000
Bit Name
Bit
Description
L2R2BOTH
1
1 – simultaneous load of LOUT2VOL and ROUT2VOL
0 – disable simultaneous load (default)
L1R1BOTH
0
1 – simultaneous load of LOUT1VOL and ROUT1VOL
0 – disable simultaneous load (default)
MIXER SETTING
Register 7 – Left Mixer, Default 1111 1111
Bit Name
Bit
Description
LI2LOMU
7
1 – mute left line in to left out mixer (default)
0 – not mute
LI2LOVOL
6:4
Left line in to left out mixer volume control
000 – 6 dB
001 – 3 dB
010 – 0 dB
011 – -3 dB
100 – -6 dB
101 – -9 dB
110 – -12 dB
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
95244 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5155
ANALOG PRODUCTS DIVISION
MI2LOMU
3
MI2LOVOL
2:0
Low Power Stereo Audio CODEC
With Headphone Amplifier
111 – -15 dB (default)
1 – mute microphone in to left out mixer (default)
0 – not mute
Microphone in to left out mixer volume control
000 – 6 dB
001 – 3 dB
010 – 0 dB
011 – -3 dB
100 – -6 dB
101 – -9 dB
110 – -12 dB
111 – -15 dB (default)
Register 8 – Right Mixer, Default 1111 1111
Bit Name
Bit
Description
MI2ROMU
7
1 –mute microphone in to right out mixer (default)
0 – not mute
MI2ROVOL
6:4
Microphone in to right out mixer volume control
000 – 6 dB
001 – 3 dB
010 – 0 dB
011 – -3 dB
100 – -6 dB
101 – -9 dB
110 – -12 dB
111 – -15 dB (default)
RI2ROMU
3
1 – mute right line in to right out mixer (default)
0 – not mute
RI2ROVOL
2:0
Right line in to rights out mixer volume control
000 – 6 dB
001 – 3 dB
010 – 0 dB
011 – -3 dB
100 – -6 dB
101 – -9 dB
110 – -12 dB
111 – -15 dB (default)
Register 9 – Mono Mixer, Default 1111 1111
Bit Name
Bit
Description
LI2MOMU
7
1 – mute left line in to mono out mixer (default)
0 – not mute
LI2MOVOL
6:4
Left line in to mono out mixer volume control
000 – 6 dB
001 – 3 dB
010 – 0 dB
011 – -3 dB
100 – -6 dB
101 – -9 dB
110 – -12 dB
111 – -15 dB (default)
RI2MOMU
3
1 – mute right line in to mono out mixer (default)
0 – not mute
RI2MOVOL
2:0
Right line in to mono out mixer volume control
000 – 6 dB
001 – 3 dB
010 – 0 dB
011 – -3 dB
100 – -6 dB
101 – -9 dB
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
95244 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5155
ANALOG PRODUCTS DIVISION
Low Power Stereo Audio CODEC
With Headphone Amplifier
110 – -12 dB
111 – -15 dB (default)
Register 10 – DAC to Mixer, Default 1011 1111
Bit Name
Bit
Description
PDN_MONODIFF
7
1 – power down mono differential input stage (default)
0 – not power down
DMEN
6
1 – mono differential line in enable
0 – single-ended line in from MONO+ (default)
LD2MOMU
5
1 – mute left DAC to mono out mixer (default)
0 – not Mute
RD2MOMU
4
1 – mute right DAC to mono out mixer (default)
0 – not mute
LD2LOMU
3
1 – mute left DAC to left out mixer (default)
0 – not mute
RD2LOMU
2
1 – mute right DAC to left out mixer (default)
0 – not mute
LD2ROMU
1
1 – mute left DAC to right out mixer (default)
0 – not mute
RD2ROMU
0
1 – mute right DAC to right out mixer (default)
0 – not mute
Register 11 – Mixer LP Mode, Default 0000 0000
Bit Name
Bit
Description
LP_MONODIFF
3
0 – normal (default)
1 – low power setting for mono differential input stage
LP_MMIX
2
0 – normal (default)
1 – low power setting for mono mixer
LP_LMIX
1
0 – normal (default)
1 – low power setting for left mixer
LP_RMIX
0
0 – normal (default)
1 – low power setting for right mixer
DAC SETTING
Register 12 – Left DAC Volume, Default 1100 0000
Bit Name
Bit
Description
DACLVOL
7:0
Left DAC volume control
00000000 – 0 dB
… 0.5 dB/step
11000000 – -127 dB (default)
Register 13 – Right DAC Volume, Default 1100 0000
Bit Name
Bit
Description
DACRVOL
7:0
Right DAC volume control
00000000 – 0 dB
… 0.5 dB/step
11000000 – -127 dB (default)
Register 14 – DAC Control 1, Default 0101 0101
Bit Name
Bit
Description
LP_DACL
7
0 – normal (default)
1 – low power setting for left DAC
PDN_DACL
6
0 – not power down
1 – power down left DAC (default)
LP_DACR
5
0 – normal (default)
1 – low power setting for right DAC
PDN_DACR
4
0 – not power down
1 – power down right DAC (default)
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
95244 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5155
ANALOG PRODUCTS DIVISION
DACLMU
2
DACRMU
0
Low Power Stereo Audio CODEC
With Headphone Amplifier
1 – left DAC mute (default)
0 – left DAC not mute
1 – right DAC mute (default)
0 – right DAC not mute
Register 15 – DAC Control 2, Default 1100 0100
Bit Name
Bit
Description
AUTOMUTE
7
Auto mute function: long period of zero inputs (8k audio samples) will mute the analog output. Any
single non-zero input will un-mute. It is done per channel based.
0 – disable
1 – enable (default)
CLICKFREE
6
0 – disable digital click free power up and down
1 – enable digital click free power up and down (default)
VPPSCALE
5:4
Reserved
DACLRBOTH
3
1 – enable simultaneous load of DACLVOL and DACRVOL
0 – disable simultaneous load (default)
DACSOFTRAMP
2
1 – enable DAC soft ramp at mute and volume change (default)
0 – disable
DACRAMPRATE
1:0
These bits define DAC gain control ramp rate
00 – 0.5 dB per 4 LRCKs (default)
01 – 0.5 dB per 8 LRCKs
10 – 0.5 dB per 16 LRCKs
11 – 0.5 dB per 32 LRCKs
Register 16 – DAC Control 3, Default 0000 1000
Bit Name
Bit
Description
DACINVL
5
0 – DAC left channel output no phase inversion (default)
1 – DAC left channel output 180 degree phase inversion
DACINVR
4
0 – DAC right channel output no phase inversion (default)
1 – DAC right output 180 degree phase inversion
DACTOEN
3
Reserved
DACDAT
2
0 – disable DAC data 6 dB attenuate
1 – -6 dB enable
Register 17 – DAC Control 4, Default 0000 0000
Bit Name
Bit
Description
DACZEROL
5
0 – normal (default)
1 – set left channel DAC output all zero
DACZEROR
4
0 – normal (default)
1 – set right channel DAC output all zero
DACMONO
3
0 – stereo (default), and enable SE function
1 – mono ((L+R)/2) into DACL and DACR, and disable SE function
DACSE
2:0
Stereo enhancement gain
000 – 0 (default)
001 – 1/8
…
111 – 7/8
Register 18 – SHELVING1_A[29:24], Default 0001 1111
Bit Name
Bit
Description
SHEV1_A[29:24]
5:0
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
Register 19 – SHELVING1_A[23:16], Default 1111 0111
Bit Name
Bit
Description
SHEV1_A[23:16]
7:0
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
95244 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5155
ANALOG PRODUCTS DIVISION
Low Power Stereo Audio CODEC
With Headphone Amplifier
Register 20 – SHELVING1_A[15:8], Default 1111 1101
Bit Name
Bit
Description
SHEV1_A[15:8]
7:0
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
Register 21 – SHELVING1_A[7:0], Default 1111 1111
Bit Name
Bit
Description
SHEV1_A[7:0]
7:0
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
Register 22 – SHELVING1_B[29:24], Default 0001 1111
Bit Name
Bit
Description
SHEV1_B[29:24]
5:0
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
Register 23 – SHELVING1_B[23:16], Default 1111 0111
Bit Name
Bit
Description
SHEV1_B[23:16]
7:0
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
Register 24 – SHELVING1_B[15:8], Default 1111 1101
Bit Name
Bit
Description
SHEV1_B[15:8]
7:0
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
Register 25 – SHELVING1_B[7:0], Default 1111 1111
Bit Name
Bit
Description
SHEV1_B[7:0]
7:0
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
Register 26 – SHELVING2_A[29:24], Default 0001 1111
Bit Name
Bit
Description
SHEV2_A[29:24]
5:0
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
Register 27 – SHELVING2_A[23:16], Default 1111 0111
Bit Name
Bit
Description
SHEV2_A[23:16]
7:0
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
Register 28 – SHELVING2_A[15:8], Default 1111 1101
Bit Name
Bit
Description
SHEV2_A[15:8]
7:0
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
Register 29 – SHELVING2_A[7:0], Default 1111 1111
Bit Name
Bit
Description
SHEV2_A[7:0]
7:0
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
Register 30 – SHELVING2_B[29:24], Default 0001 1111
Bit Name
Bit
Description
SHEV2_B[29:24]
5:0
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
Register 31 – SHELVING2_B[23:16], Default 1111 0111
Bit Name
Bit
Description
SHEV2_B[23:16]
7:0
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
Register 32 – SHELVING2_B[15:8], Default 1111 1101
Bit Name
Bit
Description
SHEV2_B[15:8]
7:0
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
Register 33 – SHELVING2_B[7:0], Default 1111 1111
Bit Name
Bit
Description
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
95244 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5155
ANALOG PRODUCTS DIVISION
SHEV2_B[7:0]
7:0
Low Power Stereo Audio CODEC
With Headphone Amplifier
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
Register 34 – SHELVING3_A[29:24], Default 0001 1111
Bit Name
Bit
Description
SHEV3_A[29:24]
5:0
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
Register 35 – SHELVING3_A[23:16], Default 1111 0111
Bit Name
Bit
Description
SHEV3_A[23:16]
7:0
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
Register 36 – SHELVING3_A[15:8], Default 1111 1101
Bit Name
Bit
Description
SHEV3_A[15:8]
7:0
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
Register 37 – SHELVING3_A[7:0], Default 1111 1111
Bit Name
Bit
Description
SHEV3_A[7:0]
7:0
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
Register 38 – SHELVING3_B[29:24], Default 0001 1111
Bit Name
Bit
Description
SHEV3_B[29:24]
5:0
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
Register 39 – SHELVING3_B[23:16], Default 1111 0111
Bit Name
Bit
Description
SHEV3_B[23:16]
7:0
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
Register 40 – SHELVING3_B[15:8], Default 1111 1101
Bit Name
Bit
Description
SHEV3_B[15:8]
7:0
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
Register 41 – SHELVING3_B[7:0], Default 1111 1111
Bit Name
Bit
Description
SHEV3_B[7:0]
7:0
30-bit a coefficient for shelving filter; Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f}
DIGITAL AUDIO INTERFACE SETTING
Register 42 – Digital Audio Interface 1, Default 0000 0000
Bit Name
Bit
Description
DACFORMAT
7:6
Audio data format
00 – I2S format (default)
01 – left justify
10 – right justify,
11 – DSP mode
DACLRSWP
5:4
00 – left data = left DAC, right data = right DAC (default)
01 – left data = left DAC, right data = left DAC
10 – left data = right DAC, right data = right DAC
11 – left data = right DAC, right data = left DAC
DACLRP
3
I2S/left justified/right justified case:
0 – L/R normal polarity (default)
1 – L/R invert polarity
DSP mode case:
nd
0 – Mode A, MSB is available on 2 SCLK rising edge after LRCK rising edge
st
1 – Mode B, MSB is available on 1 SCLK rising edge after LRCK rising edge
DACWL
2:0
Data word length
000 – 24-bit (default)
001 – 20-bit
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
95244 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5155
ANALOG PRODUCTS DIVISION
Low Power Stereo Audio CODEC
With Headphone Amplifier
010 – 18-bit
011 – 16-bit
100 – 32-bit
Register 43 – Digital Audio Interface 2, Default 0000 0001
Bit Name
Bit
Description
MCLKDIV2
4
0 – chip clock is MCLK (default)
1 – chip clock is MCLK divide by 2
SCLKINV
2
0 – normal (default)
1 – SCLK inverted
FSMODE
1
0 – single speed mode (default)
1 – double speed mode
DACMSC
0
1 – master mode serial port (default)
0 – slave mode serial port
Register 44 – Digital Audio Sample Rate, Default 0000 0110
Bit Name
Bit
Description
DACSR
4:0
DAC sample rate, MCLK frequency/LRCK frequency
00000 – 128
10000 – 125
00001 – 192
10001 – 136
00010 – 256
10010 – 250
00011 – 384
10011 – 272
00100 – 512
10100 – 375
00101 – 576
10101 – 500
00110 – 768 (default)
10110 – 544
00111 – 1024
10111 – 750
01000 – 1152
11000 – 1000
01001 – 1408
11001 – 1088
01010 – 1536
11010 – 1496
01011 – 2112
11011 – 1500
01100 – 2304
Other – Reserved
Register 45 – SCLK Divider, Default 0000 0000
Bit Name
Bit
Description
SCLKDIV
4:0
SCLK divider
0 – divide depend on DACSR and clock frequency
1 – divide by 1
2 – divide by 2
3 – divide by 3
4 – divide by 4
5 – divide by 6
6 – divide by 8
7 – divide by 9
8 – divide by 11
9 –divide by 12
10 – divide by 16
11 – divide by 18
12 – divide by 22
13 – divide by 24
14 – divide by 33
15 – divide by 36
16 – divide by 44
17 – divide by 48
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
95244 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5155
ANALOG PRODUCTS DIVISION
Low Power Stereo Audio CODEC
With Headphone Amplifier
18 – divide by 66
19 – divide by 72
other – divide by 4
REFERENCE SETTING
Register 46 – Control Port Registers Reset, Default 0000 0000
Bit Name
Bit
Description
RST_CP
7
0 – not reset (default)
1 – reset all registers of control port
Register 47 – Power Down Control, Default 0000 1100
Bit Name
Bit
Description
PDN_ANA
3
0 – not power down
1 – power down analog blocks (default)
PDN_DIG
2
0 – not power down
1 – power down digital blocks (default)
PDN_FSM
1
0 – not power down (default)
1 – power down FSM
PDN_DLL
0
0 – not power down (default)
1 – power down DLL
Register 48 – Reference 1, Default 0000 0000
Bit Name
Bit
Description
SEQ_EN
0
0 – internal power up/down sequence disable (default)
1 – internal power up/down sequence enable
Register 49 – Reference 2, Default 0010 1000
Bit Name
Bit
Description
ENREFR
5
0 – disable reference
1 – enable reference (default)
VROI
4
0 – 1.5k VREF to analog output resistance (default)
1 – 40k VREF to analog output resistance
VMIDSEL
3:2
00 – Vmid disabled (off mode)
01 – 50k divider enabled (playback/record mode)
10 – 500k divider enabled (standby mode, default)
11 – 5 k divider enabled (fast start-up mode)
VMIDLOW
1:0
Reserved
Register 50 – Reference 3, Default 0011 0100
Bit Name
Bit
Description
PDN_VREFGEN
5
0 – not power down
1 – power down VREFGEN (default)
PDN_IBIASGEN
4
0 – not power down
1 – power down IBIASGEN (default)
LP_DACVRP
3
0 – normal (default)
1 – low power mode for DACVRP
LP_VREFBUF
2
0 – normal
1 – low power for VREFBUF (default)
PDN_VREFBUF
1
0 – not power down (default)
1 – power down VREFBUF
VREFR_LO
0
0 – normal (default)
1 – low power for VREFR
Register 51 – Reference 4, Default 1111 1100
Bit Name
Bit
Description
IBIASSW
7
Reserved
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
95244 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5155
ANALOG PRODUCTS DIVISION
VSEL
6:0
Low Power Stereo Audio CODEC
With Headphone Amplifier
Reserved
Register 52 – Reference 5, Default 0101 0101
Bit Name
Bit
Description
MOUT_REF2
7
Reserved
MOUT_REF1
6
Reserved
OUT3_REF2
5
Reserved
OUT3_REF1
4
Reserved
OUT2_REF2
3
Reserved
OUT2_REF1
2
Reserved
OUT1_REF2
1
Reserved
OUT1_REF1
0
Reserved
Register 53 – Reference 6, Default 0000 0101
Bit Name
Bit
Description
MONO_REF2
3
Reserved
MONO_REF1
2
Reserved
MIX_REF2
1
Reserved
MIX_REF1
0
Reserved
PLL SETTING
Register 54 – PLL Control 1, Default 0000 1000
Bit Name
Bit
Description
pdn
7
0 – not power down (default)
1 – power down PLL analog
cp2
6
Reserved
cp1
5
Reserved
cp0
4
Reserved
SupSel1
3
Reserved
SupSel0
2
Reserved
kvco1
1
Reserved
kvco0
0
Reserved
Register 55 – PLL Control 2, Default 0000 0000
Bit Name
Bit
Description
LP
4
0 – normal mode (default)
1 – low power mode for PLL analog
MCLKSEL
3
Select internal master clock
0 – from MCLK pin (default)
1 – from PLL (to use PLL, make sure PLLEN=1, PLL_RB=1, otherwise, the setting will close chip
clock)
PLLOUT_DIV2
2
0 – divide disabled, PLL out clock is vcoout/4 (default)
1 – divide enabled, PLL out clock is vcoout/8
PLL_RB
1
0 – PLL held in reset (default)
1 – PLL running (if PLLEN=1)
PLL_EN
0
0 – PLL disabled (default)
1 – PLL enabled
Register 56 – PLL Control 3, Default 0000 0000
Bit Name
Bit
Description
DITH_MAG
6:4
Reserved
PLL_N
3:0
Integer part of PLL input/output frequency ratio; Use value greater than 5 and less than 13
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
95244 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5155
Low Power Stereo Audio CODEC
With Headphone Amplifier
ANALOG PRODUCTS DIVISION
Register 57 – PLL_K[21:16], Default 0000 0000
Bit Name
Bit
Description
PLL_K[21:16]
5:0
Fractional part of PLL input/output frequency ratio (treat as one 22-digital binary number)
Register 59 – PLL_K[15:8], Default 0000 0000
Bit Name
Bit
Description
PLL_K[15:8]
7:0
Fractional part of PLL input/output frequency ratio (treat as one 22-digital binary number)
Register 60 – PLL_K[7:0], Default 0000 0000
Bit Name
Bit
Description
PLL_K[7:0]
7:0
Fractional part of PLL input/output frequency ratio (treat as one 22-digital binary number)
DIGITAL AUDIO INTERFACE
The device provides four formats of serial audio data interface to the input of the DAC through LRCK, SCLK and SDIN pins. The four
2
formats are I S, left justified, right justified and DSP/PCM mode. DAC input DSDIN is sampled by PA5155 on the rising edge of
DSCLK. The relationship of SDATA (SDIN), SCLK and LRCK with the three formats is shown through Figure 3 to Figure 7.
1 SCLK
1
SDATA
2
1 SCLK
3
n- 2 n- 1
MSB
n
1
LSB
MSB
2
3
n- 2 n- 1
n
LSB
SCLK
LEFT CHANNEL
LRCK
RIGHT CHANNEL
Figure 3 I2S Serial Audio Data Format Up To 24-bit
SDATA
1
2
3
n- 2 n- 1
MSB
n
1
LSB
MSB
2
3
n- 2 n- 1
n
LSB
SCLK
LRCK
RIGHT CHANNEL
LEFT CHANNEL
Figure 4 Left Justified Serial Audio Data Format Up To 24-bit
SDATA
1
2
3
MSB
n- 2 n- 1
n
1
LSB
MSB
2
3
n- 2 n- 1
n
LSB
SCLK
LRCK
LEFT CHANNEL
RIGHT CHANNEL
Figure 5 Right Justified Serial Audio Data Format Up To 24-bit
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
95244 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5155
ANALOG PRODUCTS DIVISION
Low Power Stereo Audio CODEC
With Headphone Amplifier
Figure 6 DSP/PCM Mode A
Figure 7 DSP/PCM Mode B
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
95244 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5155
ANALOG PRODUCTS DIVISION
Low Power Stereo Audio CODEC
With Headphone Amplifier
PACKAGE DIMENSIONS AND MEASUREMENTS
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
95244 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS
PA5155
Low Power Stereo Audio CODEC
With Headphone Amplifier
ANALOG PRODUCTS DIVISION
Tape and Reel Specifications
Reel Dia
A0
B0
K0
D
E
F
W
P0
P2
P
t-max
178 (7”)
4.10±0.05
4.10±0.05
0.80±0.05
1.50±0.10
1.75±0.10
5.50±0.05
12.00±0.30
4.00±0.10
2.00±0.05
8.00±0.10
0.30
10 Pitches Cumulative
Tolerance on Tape± 0.2
P0
P2
D
t
E
Pin 1
indicated
by Dot
Top cover tape
A0
F
W
PA5155
XXXX
B0
PA5155
XXXX
PA5155
XXXX
K0
P
Life Support Policy
PROTEK ANALOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF PROTEK DEVICES.
561 E. Elliot Road #175 Chandler, AZ 85225 Tel: (480) 539-2900. Fax: (480) 747-1715
www.protekanalog.com
95244 Rev.0. 01/10
NOT FOR USE IN LIFE SUPPORT SYSTEMS