DS34C87T www.ti.com SNLS376B – MAY 1998 – REVISED APRIL 2013 DS34C87T CMOS Quad TRI-STATE Differential Line Driver Check for Samples: DS34C87T FEATURES DESCRIPTION • • • • • The DS34C87T is a quad differential line driver designed for digital data transmission over balanced lines. The DS34C87T meets all the requirements of EIA standard RS-422 while retaining the low power characteristics of CMOS. This enables the construction of serial and terminal interfaces while maintaining minimal power consumption. 1 2 • • • • TTL Input Compatible Typical Propagation Delays: 6 ns Typical Output Skew: 0.5 ns Outputs Won't Load Line When VCC = 0V Meets the Requirements of EIA Standard RS422 Operation from Single 5V Supply TRI-STATE Outputs for Connection to System Buses Low Quiescent Current Available in Surface Mount The DS34C87T accepts TTL or CMOS input levels and translates these to RS-422 output levels. This part uses special output circuitry that enables the individual drivers to power down without loading down the bus. This device has separate enable circuitry for each pair of the four drivers. The DS34C87T is pin compatible to the DS3487T. All inputs are protected against damage due to electrostatic discharge by diodes to VCC and ground. Connection and Logic Diagrams Top View Figure 2. Logic Diagram See PIN DESCRIPTIONS for details. Figure 1. PDIP Package See Package Numbers D0016A or NFG0016E 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998–2013, Texas Instruments Incorporated DS34C87T SNLS376B – MAY 1998 – REVISED APRIL 2013 www.ti.com Truth Table (1) Input (1) Control Non-Inverting Inverting Input Output Output H H H L L H L H X L Z Z L = Low logic state H = High logic state X = Irrelevant Z = TRI-STATE (high performance) These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) (4) −0.5 to 7.0V Supply Voltage (VCC) −1.5 to VCC +1.5V DC Voltage (VIN) −0.5 to 7V DC Output Voltage (VOUT ) Clamp Diode Current (IIK , IOK) ±20 mA DC Output Current, per pin (I OUT) ±150 mA DC VCC or GND Current (ICC) ±150 mA −65°C to +150°C Storage Temperature Range (T STG) Maximum Power Dissipation (PD) @ 25°C (5) PDIP Package 1736 mW SOIC Package 1226 mW Lead Temperature (TL) (Soldering 4 sec) 260°C This device does not meet 2000V ESD rating. (6) (1) (2) (3) (4) (5) (6) Unless otherwise specified, all voltages are referenced to ground. All currents into device pins are positive; all currents out of device pins are negative. Absolute Maximum Ratings are those values beyond which the safety of the device cannot be specified. They are not meant to imply that the device should be operated at these limits. The table of “Electrical Characteristics” provide conditions for actual device operation. ESD Rating: HBM (1.5 kΩ, 100 pF) Inputs ≥ 1500V Outputs ≥ 1000V EIAJ (0Ω, 200 pF) All Pins ≥ 350V If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Ratings apply to ambient temperature at 25°C. Above this temperature derate NFG0016E Package 13.89 mW/°C, and D0016A Package 9.80 mW/°C. ESD Rating: HBM (1.5 kΩ, 100 pF) Inputs ≥ 1500V Outputs ≥ 1000V EIAJ (0Ω, 200 pF) All Pins ≥ 350V Operating Conditions Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) DS34C87T Input Rise or Fall Times (tr, tf) 2 Submit Documentation Feedback Min Max Units 4.50 5.50 V 0 VCC V −40 +85 °C 500 ns Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS34C87T DS34C87T www.ti.com SNLS376B – MAY 1998 – REVISED APRIL 2013 DC Electrical Characteristics (1) VCC = 5V ±10% (unless otherwise specified) Parameter VIH Test Conditions High Level Input Min Typ Max 2.0 Units V Voltage VIL Low Level Input 0.8 V Voltage VOH High Level Output V IN = VIH or VIL, Voltage I OUT = −20 mA Low Level Output V IN = VIH or VIL, Voltage I OUT = 48 mA Differential Output R L = 100 Ω Voltage See (2) Difference In R L = 100 Ω Differential Output See (2) Common Mode R L = 100 Ω Output Voltage See (2) Difference In R L = 100 Ω Common Mode Output See (2) IIN Input Current V IN = VCC, GND, VIH, or VIL ICC Quiescent Supply I OUT = 0 μA, Current V IN = VCC or GND 200 500 μA V IN = 2.4V or 0.5V (3) 0.8 2.0 mA TRI-STATE Output V OUT = VCC or GND ±0.5 ±5.0 μA Leakage Current Control = VIL Output Short V IN = VCC or GND −150 mA Circuit Current See (2) and Power Off Output VCC = 0V VOUT = 6V 100 μA Leakage Current See (2) −100 μA VOL VT |VT|–| VT| VOS |VOS– VOS| IOZ ISC IOFF (1) (2) (3) (4) 2.5 3.4 0.3 2.0 0.5 3.1 2.0 −30 V V V 0.4 V 3.0 V 0.4 V ±1.0 μA (4) VOUT = −0.25V Unless otherwise specified, min/max limits apply across the −40°C to 85°C temperature range. All typicals are given for VCC = 5V and TA = 25°C. See EIA Specification RS-422 for exact test conditions. Measured per input. All other inputs at VCC or GND. This is the current sourced when a high output is shorted to ground. Only one output at a time should be shorted. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS34C87T 3 DS34C87T SNLS376B – MAY 1998 – REVISED APRIL 2013 www.ti.com Switching Characteristics (1) VCC = 5V ±10%, t r, tf ≤ 6 ns (Figure 3, Figure 4, Figure 5, Figure 6) Parameter Test Conditions Min Typ Max Units tPLH, tPHL Propagation Delay Input to Output S1 Open 6 11 ns Skew See (2) S1 Open 0.5 3 ns tTLH, tTHL Differential Output Rise And Fall Times S1 Open 6 10 ns tPZH Output Enable Time S1 Closed 12 25 ns tPZL Output Enable Time S1 Closed 13 26 ns tPHZ Output Disable Time (3) S1 Closed 4 8 ns tPLZ Output Disable Time (3) S1 Closed 6 12 ns CPD Power Dissipation Capacitance CIN Input Capacitance (1) (2) (3) (4) (4) 100 pF 6 pF Unless otherwise specified, min/max limits apply across the −40°C to 85°C temperature range. All typicals are given for VCC = 5V and TA = 25°C. Skew is defined as the difference in propagation delays between complementary outputs at the 50% point. Output disable time is the delay from the control input being switched to the output transistors turning off. The actual disable times are less than indicated due to the delay added by the RC time constant of the load. CPD determines the no load dynamic power consumption, PD = CPD V2CC f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + ICC. Comparison Table of Switching Characteristics into “LS-Type” Load (1) VCC = 5V, TA = +25°C, tr ≤ 6 ns, tf ≤ 6 ns (Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11) Parameter tPLH, tPHL Test Conditions Propagation Delay DS34C87 DS3487 Units Typ Max Typ Max 6 10 10 15 1.5 2.0 4 7 10 15 ns 8 11 17 25 ns 7 10 15 25 ns 11 19 11 25 ns 14 21 15 25 ns ns Input to Output Skew See (2) tTHL, tTLH Differential Output Rise ns and Fall Times tPHZ tPLZ Output Disable Time CL = 50 pF, RL = 200Ω, See (3) S1 Closed, S2 Closed Output Disable Time CL = 50 pF, RL = 200Ω, See tPZH (3) Output Enable Time S1 Closed, S2 Closed CL = 50 pF, RL = ∞, S1 Open, S2 Closed tPZL Output Enable Time CL = 50 pF, RL = 200Ω, S1 Closed, S2 Open (1) (2) (3) 4 This table is provided for comparison purposes only. The values in this table for the DS34C87 reflect the performance of the device but are not tested or ensured. Skew is defined as the difference in propagation delays between complementary outputs at the 50% point. Output disable time is the delay from the control input being switched to the output transistors turning off. The actual disable times are less than indicated due to the delay added by the RC time constant of the load. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS34C87T DS34C87T www.ti.com SNLS376B – MAY 1998 – REVISED APRIL 2013 AC TEST CIRCUIT AND SWITCHING TIME WAVEFORMS Note: C1 = C2 = C3 = 40 pF (including Probe and Jig Capacitance), R1 = R2 = 50Ω, R3 = 500Ω Figure 3. AC Test Circuit Input pulse; f = 1 MHz, 50%, tr ≤ 6 ns, tf ≤ 6ns Figure 4. Propagation Delays Figure 6. Differential Rise and Fall Times Figure 7. Propagation Delays Test Circuit for “LS-Type” Load Figure 5. Enable and Disable Times Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS34C87T 5 DS34C87T SNLS376B – MAY 1998 – REVISED APRIL 2013 www.ti.com Figure 8. Differential Rise and Fall Times Test Circuit for “LS-Type” Load Figure 9. Load Enable and Disable Times Test Circuit for “LS-Type” Load Figure 10. Load Propagation Delays for “LS-Type” Load Figure 11. Load Enable and Disable Times for “LS-Type” Load TYPICAL APPLICATIONS *RT is optional although highly recommended to reduce reflection. 6 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS34C87T DS34C87T www.ti.com SNLS376B – MAY 1998 – REVISED APRIL 2013 PIN DESCRIPTIONS Pin Number (PDIP or SOIC package) Pin Name Function 1 INPUT A Channel A - TTL/CMOS input 2 OUTPUT A - True True Output for Channel A, RS422 Levels 3 OUTPUT A - Inverting Inverting Output for Channel A, RS422 Levels 4 A/B CONTROL Enable Pin for Channels A and B, Active High, TTL/CMOS Levels 5 OUTPUT B - Inverting Inverting Output for Channel B, RS422 Levels 6 OUTPUT B - True True Output for Channel B, RS422 Levels 7 INPUT B Channel B - TTL/CMOS input 8 GND Ground Pin (0 V) 9 INPUT C Channel C - TTL/CMOS input 10 OUTPUT C - True True Output for Channel C, RS422 Levels 11 OUTPUT C - Inverting Inverting Output for Channel C, RS422 Levels 12 C/D CONTROL Enable Pin for Channels C and D, Active High, TTL/CMOS Levels 13 OUTPUT D - Inverting Inverting Output for Channel D, RS422 Levels 14 OUTPUT D - True True Output for Channel D, RS422 Levels 15 INPUT D Channel D - TTL/CMOS input 16 VCC Power Supply Pin, 5.0V typical Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS34C87T 7 DS34C87T SNLS376B – MAY 1998 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision A (April 2013) to Revision B • 8 Page Changed layout of National Data Sheet to TI format ............................................................................................................ 7 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: DS34C87T PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) DS34C87TM ACTIVE SOIC D 16 48 TBD Call TI Call TI -40 to 85 DS34C87TM DS34C87TM/NOPB ACTIVE SOIC D 16 48 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS34C87TM DS34C87TMX ACTIVE SOIC D 16 2500 TBD Call TI Call TI -40 to 85 DS34C87TM DS34C87TMX/NOPB ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS34C87TM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2013 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS34C87TMX SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1 DS34C87TMX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS34C87TMX SOIC D 16 2500 367.0 367.0 35.0 DS34C87TMX/NOPB SOIC D 16 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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