Preliminary FM24C04C 4Kb Serial 5V F-RAM Memory Features 4K bit Ferroelectric Nonvolatile RAM Organized as 512 x 8 bits High Endurance 1012 Read/Writes 36 Year Data Retention at +75C NoDelay™ Writes Advanced High-Reliability Ferroelectric Process Fast Two-wire Serial Interface Up to 1 MHz maximum bus frequency Direct hardware replacement for EEPROM Supports legacy timing for 100 kHz & 400 kHz Description The FM24C04C is a 4-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 36 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. The FM24C04C performs write operations at bus speed. No write delays are incurred. Data is written to the memory array in the cycle after it has been successfully transferred to the device. The next bus cycle may commence immediately without the need for data polling. The FM24C04C is capable of supporting 1012 read/write cycles, or a million times more write cycles than EEPROM. These capabilities make the FM24C04C ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The combination of features allows more frequent data writing with less overhead for the system. Low Power Operation 5V operation 100 A Active Current (100 kHz) 4 A (typ.) Standby Current Industry Standard Configuration Industrial Temperature -40 C to +85 C 8-pin “Green”/RoHS SOIC (-G) Pin Configuration NC A1 A2 1 8 2 7 3 6 VSS 4 5 Pin Names A1-A2 SDA SCL WP VSS VDD VDD WP SCL SDA Function Device Select Address 1 and 2 Serial Data/Address Serial Clock Write Protect Ground Supply Voltage Ordering Information FM24C04C-G FM24C04C-GTR “Green”/RoHS 8-pin SOIC “Green”/RoHS 8-pin SOIC, Tape & Reel The FM24C04C provides substantial benefits to users of serial EEPROM, yet these benefits are available in a hardware drop-in replacement. The FM24C04C is available in an industry standard 8-pin SOIC package and uses a familiar two-wire protocol. The specifications are guaranteed over the industrial temperature range from -40°C to +85°C. This is a product that has fixed target specifications but are subject to change pending characterization results. Rev. 1.1 June 2011 Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 www.ramtron.com Page 1 of 12 FM24C04C Address Latch Counter 64 x 64 FRAM Array 8 Serial to Parallel Converter SDA Data Latch SCL WP A1 A2 Control Logic Figure 1. Block Diagram Pin Description Pin Name A1-A2 I/O Input SDA I/O SCL Input WP Input NC VDD VSS Rev. 1.1 June 2011 Supply Supply Pin Description Address 1-2: The address pins set the device select address. The device address value in the 2-wire slave address must match the setting of these two pins. These pins are internally pulled down. Serial Data/Address: This is a bi-directional pin used to shift serial data and addresses for the two-wire interface. It employs an open-drain output and is intended to be wireOR’d with other devices on the two-wire bus. The input buffer incorporates a Schmitt trigger for noise immunity and the output driver includes slope control for falling edges. A pull-up resistor is required. Serial Clock: The serial clock input for the two-wire interface. Data is clocked out of the device on the SCL falling edge, and clocked in on the SCL rising edge. The SCL input also incorporates a Schmitt trigger input for improved noise immunity. Write Protect: When WP is high, the entire array is write-protected. When WP is low, all addresses may be written. This pin is internally pulled down. No connect Supply Voltage Ground Page 2 of 12 FM24C04C Overview Two-wire Interface The FM24C04C is a serial FRAM memory. The memory array is logically organized as 512 x 8 and is accessed using an industry standard two-wire interface. Functional operation of the FRAM is similar to serial EEPROMs. The major difference between the FM24C04C and a serial EEPROM with the same pinout relates to its superior write performance. The FM24C04C employs a bi-directional two-wire bus protocol using few pins and little board space. Figure 2 illustrates a typical system configuration using the FM24C04C in a microcontroller-based system. The industry standard two-wire bus is familiar to many users but is described in this section. Memory Architecture When accessing the FM24C04C, the user addresses 512 locations each with 8 data bits. These data bits are shifted serially. The 512 addresses are accessed using the two-wire protocol, which includes a slave address (to distinguish other devices), a page address, and a word address. The word address consists of 8bits that specify one of 256 addresses. The page address is 1-bit and so there are 2 pages of 256 locations. The complete address of 9-bits specifies each byte address uniquely. Most functions of the FM24C04C either are controlled by the two-wire interface or are handled automatically by on-board circuitry. The memory is read or written at the speed of the two-wire bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. That is, by the time a new bus transaction can be shifted into the part, a write operation will be complete. This is explained in more detail in the interface section below. By convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. The device that is controlling the bus is the master. The master is responsible for generating the clock signal for all operations. Any device on the bus that is being controlled is a slave. The FM24C04C is always a slave device. The bus protocol is controlled by transition states in the SDA and SCL signals. There are four conditions: Start, Stop, Data bit, and Acknowledge. Figure 3 illustrates the signal conditions that specify the four states. Detailed timing diagrams are shown in the electrical specifications. VDD Rmin = 1.8 Kohm Rmax = tR/Cbus Microcontroller SDA Users can expect several obvious system benefits from the FM24C04C due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly. By contrast an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle. SCL SDA SCL FM24C04C FM24C04C A1 A2 A1 A2 VDD Figure 2. Typical System Configuration Note that the FM24C04C contains no power management circuits other than a simple internal power-on reset. It is the user’s responsibility to ensure that VDD is within data sheet tolerances to prevent incorrect operation. Rev. 1.1 June 2011 Page 3 of 12 FM24C04C Figure 3. Data Transfer Protocol Stop Condition A Stop condition is indicated when the bus master drives SDA from low to high while the SCL signal is high. All operations must end with a Stop condition. If an operation is pending when a stop is asserted, the operation will be aborted. The master must have control of SDA (not a memory read) in order to assert a Stop condition. Start Condition A Start condition is indicated when the bus master drives SDA from high to low while the SCL signal is high. All read and write transactions begin with a Start condition. An operation in progress can be aborted by asserting a Start condition at any time. Aborting an operation using the Start condition will ready the FM24C04C for a new operation. If during operation the power supply drops below the specified VDD minimum, the system should issue a Start condition prior to performing another operation. Data/Address Transfer All data transfers (including addresses) take place while the SCL signal is high. Except under the two conditions described above, the SDA signal should not change while SCL is high. Acknowledge The Acknowledge takes place after the 8th data bit has been transferred in any transaction. During this state the transmitter should release the SDA bus to allow the receiver to drive it. The receiver drives the SDA signal low to acknowledge receipt of the byte. If the receiver does not drive SDA low, the condition is a NoAcknowledge and the operation is aborted. The receiver could fail to acknowledge for two distinct reasons. First, if a byte transfer fails, the NoAcknowledge ends the current operation so that the device can be addressed again. This allows the last Rev. 1.1 June 2011 byte to be recovered in the event of a communication error. Second and most common, the receiver does not acknowledge the data to deliberately end an operation. For example, during a read operation, the FM24C04C will continue to place data onto the bus as long as the receiver sends acknowledges (and clocks). When a read operation is complete and no more data is needed, the receiver must not acknowledge the last byte. If the receiver acknowledges the last byte, this will cause the FM24C04C to attempt to drive the bus on the next clock while the master is sending a new command such as a Stop command. Slave Address The first byte that the FM24C04C expects after a start condition is the slave address. As shown in Figure 4, the slave address contains the device type, the device select, the page of memory to be accessed, and a bit that specifies if the transaction is a read or a write. Bits 7-4 are the device type and should be set to 1010b for the FM24C04C. The device type allows other types of functions to reside on the 2-wire bus within an identical address range. Bits 3-2 are the device address. If bit 3 matches the A2 pin and bit 2 matches the A1 pin the device will be selected. Bit 1 is the page select. It specifies the 256-byte block of memory that is targeted for the current operation. Bit 0 is the read/write bit. A 0 indicates a write operation. Word Address After the FM24C04C (as receiver) acknowledges the slave ID, the master will place the word address on the bus for a write operation. The word address is the lower 8-bits of the address to be combined with the 1-bit page select to specify exactly the byte to be written. The complete 9-bit address is latched internally. Page 4 of 12 FM24C04C Memory Operation Figure 4. Slave Address No word address occurs for a read operation. Reads always use the lower 8-bits that are held internally in the address latch and the 9th address bit is part of the slave address. Reads always begin at the address following the previous access. A random read address can be loaded by doing a write operation as explained below. After transmission of each data byte, just prior to the acknowledge, the FM24C04C increments the internal address latch. This allows the next sequential byte to be accessed with no additional addressing. After the last address (1FFh) is reached, the address latch will roll over to 000h. There is no limit to the number of bytes that can be accessed with a single read or write operation. Data Transfer After all address information has been transmitted, data transfer between the bus master and the FM24C04C can begin. For a read operation the FM24C04C will place 8 data bits on the bus then wait for an acknowledge. If the acknowledge occurs, the next sequential byte will be transferred. If the acknowledge is not sent, the read operation is concluded. For a write operation, the FM24C04C will accept 8 data bits from the master then send an acknowledge. All data transfer occurs MSB (most significant bit) first. The FM24C04C is designed to operate in a manner very similar to other 2-wire interface memory products. The major differences result from the higher performance write capability of FRAM technology. These improvements result in some differences between the FM24C04C and a similar configuration EEPROM during writes. The complete operation for both writes and reads is explained below. Write Operation All writes begin with a slave address then a word address. The bus master indicates a write operation by setting the LSB of the Slave address to a 0. After addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condition. Any number of sequential bytes may be written. If the end of the address range is reached internally, the address counter will wrap from 1FFh to 000h. Unlike other nonvolatile memory technologies, there is no write delay with FRAM. The entire memory cycle occurs in less time than a single bus clock. Therefore any operation including read or write can occur immediately following a write. Acknowledge polling, a technique used with EEPROMs to determine if a write is complete is unnecessary and will always return a done condition. An actual memory array write occurs after the 8th data bit is transferred. It will be complete before the acknowledge is sent. Therefore if the user desires to abort a write without altering the memory contents, this should be done using a start or stop condition prior to the 8th data bit. The FM24C04C needs no page buffering. Pulling write protect high will disable writes to the entire array. The FM24C04C will not acknowledge data bytes that are written when write protect is asserted. In addition, the address counter will not increment if writes are attempted. Pulling WP low (VSS) will deactivate this feature. Figures 5 and 6 below illustrate both a single-byte and multiple- byte write cases. Rev. 1.1 June 2011 Page 5 of 12 FM24C04C By Master Start S Address & Data Slave Address 0 A Word Address By F-RAM Stop A Data Byte A P Acknowledge Figure 5. Byte Write By Master Start S Address & Data Slave Address 0 A Word Address Stop A By F-RAM Data Byte A Data Byte A P Acknowledge Figure 6. Multiple-Byte Write Read Operation There are two basic types of read operations. They are current address read and selective address read. In a current address read, the FM24C04C uses the internal address latch to supply the lower 8 address bits. In a selective read, the user performs a procedure to set these lower address bits to a specific value. Current Address & Sequential Read The FM24C04C uses an internal latch to supply the lower 8 address bits for a read operation. A current address read uses the existing value in the address latch as a starting place for the read operation. This is the address immediately following that of the last operation. To perform a current address read, the bus master supplies a slave address with the LSB set to 1. This indicates that a read operation is requested. The page select bit in the slave address specifies the block of memory that is used for the read operation. After the acknowledge, the FM24C04C will begin shifting out data from the current address. The current address is the bit from the slave address combined with the 8 bits that were in the internal address latch. Beginning with the current address, the bus master can read any number of bytes. Thus a sequential read is simply a current address read with multiple byte transfers. After each byte the internal address counter will be incremented. Each time the bus master acknowledges a byte, this indicates that the FM24C04C should read out the next sequential byte. There are four ways to properly terminate a read operation. Failing to properly terminate the read will most likely create a bus contention as the FM24C04C Rev. 1.1 June 2011 attempts to read out additional data onto the bus. The four valid methods are as follows. 1. 2. 3. 4. The bus master issues a no-acknowledge in the 9th clock cycle and a stop in the 10th clock cycle. This is illustrated in the diagrams below. This is the preferred method. The bus master issues a no-acknowledge in the 9th clock cycle and a start in the 10th. The bus master issues a stop in the 9th clock cycle. Bus contention may result. The bus master issues a start in the 9th clock cycle. Bus contention may result. If the internal address reaches 1FFh it will wrap around to 000h on the next read cycle. Figures 7 and 8 show the proper operation for current address reads. Selective (Random) Read A simple technique allows a user to select a random address location as the starting point for a read operation. This involves using the first two bytes of a write operation to set the internal address byte followed by subsequent read operations. To perform a selective read, the bus master sends out the slave address with the LSB set to 0. This specifies a write operation. According to the write protocol, the bus master then sends the word address byte that is loaded into the internal address latch. After the FM24C04C acknowledges the word address, the bus master issues a start condition. This simultaneously aborts the write operation and allows the read command to be issued with the slave address LSB set to a 1. The operation is now a current address read. See Figure 9. Page 6 of 12 FM24C04C By Master Start No Acknowledge Address Stop S Slave Address By F-RAM 1 A Data Byte Acknowledge 1 P Data Figure 7. Current Address Read By Master Start Address No Acknowledge Acknowledge Stop S Slave Address By F-RAM 1 A Data Byte A Acknowledge Data Byte 1 P Data Figure 8. Sequential Read By Master Address Start Start Address No Acknowledge Acknowledge Stop S By F-RAM Slave Address 0 A Word Address A S Slave Address 1 A Acknowledge Data Byte A Data Byte 1 P Data Figure 9. Selective (Random) Read Endurance The FM24C04C internally operates with a read and restore mechanism. Therefore, endurance cycles are applied for each read or write cycle. The memory architecture is based on an array of rows and columns. Each read or write access causes an endurance cycle for an entire row. In the FM24C04C, a row is 64 bits wide. Every 8-byte boundary marks Rev. 1.1 June 2011 the beginning of a new row. Endurance can be optimized by ensuring frequently accessed data is located in different rows. Regardless, F-RAM read and write endurance is effectively unlimited at the 1MHz two-wire speed. Even at 3000 accesses per second to the same row, 10 years time will elapse before 1 trillion endurance cycles occur. Page 7 of 12 FM24C04C Electrical Specifications Absolute Maximum Ratings Symbol VDD VIN TSTG TLEAD VESD Description Power Supply Voltage with respect to VSS Voltage on any pin with respect to VSS Storage Temperature Lead temperature (Soldering, 10 seconds) Electrostatic Discharge Voltage - Human Body Model (AEC-Q100-002 Rev. E) - Charged Device Model (AEC-Q100-011 Rev. B) - Machine Model (AEC-Q100-003 Rev. E) Package Moisture Sensitivity Level Ratings -1.0V to +7.0V -1.0V to +7.0V and VIN < VDD+1.0V * -55C to + 125C 260 C 3kV 1.25kV 100V MSL-1 * Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40 C to + 85 C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Typ Max Units VDD Main Power Supply 4.5 5.0 5.5 V IDD VDD Supply Current @ SCL = 100 kHz 100 A @ SCL = 400 kHz 200 A @ SCL = 1 MHz 400 A ISB Standby Current 4 10 A ILI Input Leakage Current ±1 A ILO Output Leakage Current ±1 A VIH Input High Voltage 0.7 VDD VDD + 0.3 V VIL Input Low Voltage -0.3 0.3 VDD V VOL Output Low Voltage 0.4 V @ IOL = 3.0 mA RIN Input Resistance (WP, A1, A2) For VIN = VIL (max) 40 K For VIN = VIH (min) 1 M VHYS Input Hysteresis 0.05 VDD V Notes 1 2 3 3 5 4 Notes 1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V 2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued. 3. VIN or VOUT = VSS to VDD. Does not apply to WP, A1, A2 pins. 4. This parameter is periodically sampled and not 100% tested. 5. The input pull-down circuit is strong (40K) when the input voltage is below VIL and much weaker (1M) when the input voltage is above VIH. Rev. 1.1 June 2011 Page 8 of 12 FM24C04C AC Parameters (TA = -40 C to + 85 C, VDD = 4.5V to 5.5V, CL = 100 pF unless otherwise specified) Symbol fSCL tLOW tHIGH tAA Parameter SCL Clock Frequency Clock Low Period Clock High Period SCL Low to SDA Data Out Valid Min 0 4.7 4.0 tBUF Bus Free Before New Transmission Start Condition Hold Time Start Condition Setup for Repeated Start Data In Hold Data In Setup Input Rise Time Input Fall Time Stop Condition Setup Data Output Hold (from SCL @ VIL) Noise Suppression Time Constant on SCL, SDA 4.7 1.3 0.5 s 4.0 4.7 0.6 0.6 0.25 0.25 s s 0 250 0 100 0 100 300 100 ns ns ns ns s ns 50 ns tHD:STA tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH tSP Max 100 Min 0 1.3 0.6 3 Min 0 0.6 0.4 0.9 1000 300 4.0 0 Max 400 0.55 300 300 0.6 0 50 Max 1000 0.25 0 50 Units kHz s s s Notes 1 1 Notes : All SCL specifications as well as start and stop conditions apply to both read and write operations. 1 This parameter is periodically sampled and not 100% tested. Capacitance (TA = 25 C, f=1.0 MHz, VDD = 5V) Symbol Parameter CI/O Input/Output Capacitance (SDA) CIN Input Capacitance Max 8 6 Units pF pF Notes 1 1 Notes 1 This parameter is periodically sampled and not 100% tested. Power Cycle Timing VDD VDD min. tVR tVF tPU tPD SDA,SCL Power Cycle Timing (TA = -40C to +85C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Max tPU Power Up (VDD min) to First Access (Start condition) 1 tPD Last Access (Stop condition) to Power Down (VDD min) 0 tVR VDD Rise Time 30 tVF VDD Fall Time 100 Notes 1. Slope measured at any point on VDD waveform. Rev. 1.1 June 2011 Units Notes ms s s/V s/V 1 1 Page 9 of 12 FM24C04C AC Test Conditions Input Pulse Levels Input rise and fall times Input and output timing levels Equivalent AC Load Circuit 0.1 VDD to 0.9 VDD 10 ns 0.5 VDD 5.5V 1700 Output Diagram Notes All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional relationships are illustrated in the relevant datasheet sections. These diagrams illustrate the timing parameters only. 100 pF Read Bus Timing tR ` tF tHIGH tSP tLOW tSP SCL tSU:SDA 1/fSCL tBUF tHD:DAT tSU:DAT SDA tDH tAA Stop Start Start Acknowledge Write Bus Timing tHD:DAT SCL tHD:STA tSU:STO tSU:DAT tAA SDA Start Data Retention Symbol Parameter TDR @ +85ºC @ +80ºC @ +75ºC Rev. 1.1 June 2011 Stop Start Acknowledge Min 10 18 36 Max - Units Years Years Years Notes Page 10 of 12 FM24C04C Mechanical Drawing 8-pin SOIC (JEDEC Standard MS-012 variation AA) Recommended PCB Footprint 7.70 3.90 ±0.10 3.70 6.00 ±0.20 2.00 0.65 1.27 Pin 1 4.90 ±0.10 1.27 0.33 0.51 0.25 0.50 1.35 1.75 0.10 0.25 0.19 0.25 45 0.10 mm 0-8 0.40 1.27 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. SOIC Package Marking Scheme XXXXXXX-P RLLLLLLL RICYYWW Legend: XXXXXX= part number, P= package type R=rev code, LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM24C04C, “Green”/RoHS SOIC package, Year 2010, Work Week 49 FM24C04C-G A00002G1 RIC1049 Rev. 1.1 June 2011 Page 11 of 12 FM24C04C Revision History Revision 1.0 1.1 Rev. 1.1 June 2011 Date 5/20/2011 6/30/2011 Summary Initial Release Added ESD ratings. Page 12 of 12