SGLS124A − JULY 2002 − REVISED DECEMBER 2003
D Controlled Baseline
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
applications
− One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of
−40°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product Change Notification
Qualification Pedigree†
Single Supply 2.7-V to 5.5-V Operation
±0.4 LSB Differential Nonlinearity (DNL),
±1.5 LSB Integral Nonlinearity (INL)
12-Bit Parallel Interface
Compatible With TMS320 DSP
Internal Power On Reset
Settling Time 1 µs Typ
Low Power Consumption:
− 8 mW for 5-V Supply
− 4.3 mW for 3-V Supply
Reference Input Buffers
Voltage Output
Monotonic Over Temperature
Asynchronous Update
D Battery Powered Test Instruments
D Digital Offset and Gain Adjustment
D Battery Operated/Remote Industrial
D
D
D
D
D
Controls
Machine and Motion Control Devices
Cordless and Wireless Telephones
Speech Synthesis
Communication Modulators
Arbitrary Waveform Generation
DW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
20
19
18
17
16
15
14
13
12
11
D1
D0
CS
WE
LDAC
PD
GND
OUT
REFIN
VDD
† Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
description
The TLV5619 is a 12-bit voltage output DAC with a microprocessor and TMS320 compatible parallel interface.
The 12 data bits are double buffered so that the output can be updated asynchronously using the LDAC pin.
During normal operation, the device dissipates 8 mW at a 5-V supply and 4.3 mW at a 3-V supply. The power
consumption can be lowered to 50 nW by setting the DAC to power-down mode.
The output voltage is buffered by a ×2 gain rail-to-rail amplifier, which features a Class A output stage to improve
stability and reduce settling time.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 125°C
SOP − DW
Tape and reel
TLV5619QDWREP
TLV5619QEP
‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002 − 2003, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#'
+&%#$ %! # $('%%"#$ (' #,' #'!$ '-"$ $#&!'#$
$#"+"+ .""#/ +&%# (%'$$0 +'$ # '%'$$"*/ %*&+'
#'$#0 "** (""!'#'$
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1
SGLS124A − JULY 2002 − REVISED DECEMBER 2003
functional block diagram
REFIN
12
+
_
D0 19
20
D1
1
D2
2
D3
3
D4
4
D5
5
D6
6
D7
7
D8
8
D9
9
D10
10
D11
Resistor
String DAC
12
17
WE
12
Power-On
Reset
Select
and
Control
Logic
18
CS
12-Bit
DAC
Latch
12-Bit
Input
Register
15
PD
16
LDAC
Terminal Functions
TERMINAL
NAME
CS
D0 (LSB)−D11 (MSB)
NO.
I/O
DESCRIPTION
18
I
Chip select
19, 20,
1 − 10
I
Parallel data input
GND
14
LDAC
16
I
Load DAC
OUT
13
O
Analog output
PD
15
I
When low, disables all buffer amplifier voltages to reduce supply current
REFIN
12
I
Voltage reference input
VDD
WE
17
2
Ground
11
Positive power supply
I
Write enable
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
x2
13
OUT
SGLS124A − JULY 2002 − REVISED DECEMBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage (VDD to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to VDD + 0.3 V
Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V
Digital input voltage range to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to VDD + 0.3 V
Operating free-air temperature range, TA: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
NOM
Supply voltage, VDD (5-V Supply)
4.5
5
5.5
V
Supply voltage, VDD (3-V Supply)
2.7
3
3.3
V
High-level digital input voltage, VIH
VDD = 2.7 V
VDD = 5.5 V
Low-level digital input voltage, VIL
VDD = 2.7 V
VDD = 5.5 V
MAX
UNIT
2
V
2.4
0.6
0.8
Reference voltage, Vref to REFIN terminal (5-V Supply)
0
2.048
Reference voltage, Vref to REFIN terminal (3-V Supply)
0
1.024
Load resistance, RL
2
10
Load capacitance, CL
Operating free-air temperature, TA
−40
VDD −1.5
VDD −1.5
V
V
V
kΩ
100
pF
125
°C
NOTES: 1. The recommended operating levels for both VIH and VIL apply to all valid values of VDD.
2. Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes.
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3
SGLS124A − JULY 2002 − REVISED DECEMBER 2003
electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted)
static DAC specifications
PARAMETER
EZS
EG
TEST CONDITIONS
MIN
MAX
UNIT
Resolution
Vref(REFIN) = 2.048 V at 5 V,
1.024 V at 3 V
Integral nonlinearity (INL)
Vref(REFIN) = 2.048 V at 5 V,
1.024 V at 3 V,
See Note 3
± 1.5
±4
LSB
Differential nonlinearity (DNL)
Vref(REFIN) = 2.048 V at 5 V,
1.024 V at 3 V,
See Note 4
± 0.4
±1
LSB
Zero-scale error (offset error at zero scale)
Vref(REFIN) = 2.048 V at 5 V,
1.024 V at 3 V,
See Note 5
±3
± 20
mV
Zero-scale-error temperature coefficient
Vref(REFIN) = 2.048 V at 5 V,
1.024 V at 3 V,
See Note 6
3
Gain error
Vref(REFIN) = 2.048 V at 5 V,
1.024 V at 3 V,
See Note 7
± 0.25
Gain error temperature coefficient
Vref(REFIN) = 2.048 V at 5 V,
1.024 V at 3 V,
See Note 8
1
12
Zero scale
PSRR
TYP
Power-supply rejection ratio
ppm/°C
± 0.5
% of FS
voltage
ppm/°C
65
See Notes 9 and 10
Gain
bits
dB
65
NOTES: 3. The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors.
4. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
5. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
6. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) − EZS (Tmin)]/Vref × 106/(Tmax − Tmin).
7. Gain error is the deviation from the ideal output (2 × Vref − 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.
8. Gain temperature coefficient is given by: EG TC = [EG(Tmax) − EG (Tmin)]/Vref × 106/(Tmax − Tmin).
9. Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of
this signal imposed on the zero-code output voltage.
10. Gain-error rejection ratio (EG-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal
imposed on the full-scale output voltage after subtracting the zero scale change.
output specifications
PARAMETER
VO
TEST CONDITIONS
Voltage output range
RL = 10 kΩ
Output load regulation accuracy
VO(OUT) = 4.096 V,
2.048 V
IOSC(source)
Output short circuit source current
VO(OUT) = 0 V,
Full scale code
IO(source)
Output source current
RL = 100 Ω
4
POST OFFICE BOX 655303
MIN
TYP
0
RL = 2 kΩ
0.1
5-V Supply
100
3-V Supply
25
5-V Supply
10
3-V Supply
10
• DALLAS, TEXAS 75265
MAX
VDD−0.4
0.29
UNIT
V
% of FS
voltage
mA
mA
SGLS124A − JULY 2002 − REVISED DECEMBER 2003
electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted)
reference input (REFIN)
PARAMETER
Vref
Ri
Reference input voltage
Ci
Reference input capacitance
TEST CONDITIONS
See Note 11
MIN
TYP
0
Reference input resistance
MAX
UNIT
VDD−1.5
10
V
MΩ
5
pF
Reference feed through
REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 12)
−60
dB
Reference input bandwidth
REFIN = 0.2 Vpp + 1.024 V dc at −3 dB
1.4
MHz
NOTES: 11. Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes.
12. Reference feedthrough is measured at the DAC output with an input code = 0x000 and a Vref(REFIN) input = 1.024 V dc + 1 Vpp at
1 kHz.
digital inputs (D0 − D11, CS, WE, LDAC, PD)
PARAMETER
IIH
IIL
High-level digital input current
Ci
Input capacitance
TEST CONDITIONS
MIN
TYP
VI = VDD
VI = 0 V
Low-level digital input current
MAX
UNIT
1
µA
−1
µA
8
pF
power supply
PARAMETER
IDD
Power supply current
TEST CONDITIONS
MIN
No load, All inputs 0 V or VDD
TYP
MAX
5-V Supply
1.6
3
3-V Supply
1.44
2.7
0.01
10
Power down supply current
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
mA
µA
5
SGLS124A − JULY 2002 − REVISED DECEMBER 2003
operating characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted)
analog output dynamic performance
PARAMETER
SR
ts
S/N
S/(N+D)
TEST CONDITIONS
CL = 100 pF,
RL = 10 kΩ,
Code 32 to code 4095,
Code 4095 to code 32,
Vref(REFIN) = 2.048 V,
1.024 V,
VO from 10% to 90%
90% to 10%
Output settling time (full scale)
To ± 0.5 LSB,
RL = 10 kΩ,
CL = 100 pF,
See Note 13
Glitch energy
DIN = all 0s to all 1s
Signal to noise
fs = 480 kSPS,
BW = 20 kHz,
CL = 100 pF,
fOUT = 1 kHz,
RL = 10 kΩ
TA = 25°C, See Note 14
Signal to noise + distortion
fs = 480 kSPS,
BW = 20 kHz,
CL = 100 pF,
fOUT = 1 kHz,
RL = 10 kΩ,
kΩ
TA = 25°C, See Note 14
Total harmonic distortion
fs = 480 kSPS,
BW = 20 kHz,
CL = 100 pF,
fOUT = 1 kHz,
RL = 10 kΩ,
TA = 25°C, See Note 14
Spurious free dynamic range
fs = 480 kSPS,
BW = 20 kHz,
CL = 100 pF,
fOUT = 1 kHz,
RL = 10 kΩ,
TA = 25°C, See Note 14
Slew rate
MIN
TYP
5-V
Supply
8
12
V/µs
3-V
Supply
6
9
V/µs
1
MAX
3
5
5-V
Supply
65
78
5-V
Supply
58
67
3-V
Supply
58
69
−68
60
UNIT
µs
nV−s
dB
−60
72
NOTES: 13. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of 0x020 to 0x3DF or 0x3DF to 0x020. Limits are ensured by design and characterization, but are not production tested.
14. 1 kHz sinewave generated by DAC, reference voltage = 1.024 V at 3 V and 2.048 V at 5 V.
timing requirement
digital inputs
MIN
NOM
MAX
UNIT
tsu(CS-WE)
tsu(D)
Setup time, CS low before positive WE edge
th(D)
tsu(WE-LD)
twh(WE)
tw(LD)
Pulse width, WE high
Pulse width, LDAC low
25
ns
6
13
ns
Setup time, data ready before positive WE edge
9
ns
Hold time, data held after positive WE edge
0
ns
0
ns
25
ns
Setup time, positive WE edge before LDAC low
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• DALLAS, TEXAS 75265
SGLS124A − JULY 2002 − REVISED DECEMBER 2003
PARAMETER MEASUREMENT INFORMATION
D(0−11)
X
Data
X
tsu(D)
th(D)
CS
tsu(CE-WE)
twh(WE)
WE
tsu(WE-LD)
tw(LD)
LDAC
Figure 1. Timing Diagram
POST OFFICE BOX 655303
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7
SGLS124A − JULY 2002 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
MAXIMUM OUTPUT VOLTAGE
vs
LOAD
MAXIMUM OUTPUT VOLTAGE
vs
LOAD
3
5
VDD = 3 V, Vref = 1.2 V,
Input Code = 4095
VDD = 5 V, Vref = 2 V,
Input Code = 4095
2.5
VO − Output Voltage − V
VO − Output Voltage − V
4
3
2
2
1.5
1
1
100 k
100
10 k
1k
RL − Output Load − Ω
0.5
100 k
10
100
10 k
1k
RL − Output Load − Ω
Figure 3
Figure 2
TOTAL HARMONIC DISTORTION
vs
LOAD
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
0
VDD = 5 V, Vref = 2 V,
Tone at 1 kHz
VDD = 5 V
THD − Total Harmonic Distortion − dB
THD − Total Harmonic Distortion − dB
0
−20
−40
−60
−80
−10
−20
−30
−40
−50
−60
−70
−100
100 k
−80
10 k
1k
100
RL − Output Load − Ω
10
0
5
10
15
Figure 5
POST OFFICE BOX 655303
20
25
f − Frequency − kHz
Figure 4
8
10
• DALLAS, TEXAS 75265
30
35
SGLS124A − JULY 2002 − REVISED DECEMBER 2003
TYPICAL CHARACTERISTICS
SNRD − Signal-To-Noise Ratio + Distortion − dB
SIGNAL-TO-NOISE + DISTORTION
vs
FREQUENCY
80
VDD = 5 V
70
60
50
40
30
20
10
0
0
5
10
15
20
25
30
35
f − Frequency − kHz
DNL − Differential Nonlinearity − LSB
Figure 6
1
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
−1
0
500
1000
1500
2000
2500
3000
3500
4000
Code
Figure 7. Differential Nonlinearity
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9
SGLS124A − JULY 2002 − REVISED DECEMBER 2003
INL − Integral Nonlinearity − LSB
TYPICAL CHARACTERISTICS
4
3
2
1.5
1
0.5
0
−0.5
−1
−1.5
−2
−3
−4
0
500
1000
1500
2000
2500
3000
Code
Figure 8. Integral Nonlinearity
POWER DOWN SUPPLY CURRENT
vs
TIME
1
I DD − Supply Current − mA
0.1
0.01
0.001
0.0001
0.00001
0.000001
0
100
200
300
400
500
t − Time − ms
Figure 9
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
600
3500
4000
SGLS124A − JULY 2002 − REVISED DECEMBER 2003
APPLICATION INFORMATION
definitions of specifications and terminology
integral nonlinearity (INL)
The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum
deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale
errors.
differential nonlinearity (DNL)
The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the
measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage
changes in the same direction (or remains constant) as a change in the digital input code.
zero-scale error (EZS)
Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.
gain error (EG)
Gain error is the error in slope of the DAC transfer function.
signal-to-noise ratio + distortion (S/N+D)
S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.
spurious free dynamic range (SFDR)
SFDR is the difference between the rms value of the output signal and the rms value of the largest spurious
signal within a specified bandwidth. The value for SFDR is expressed in decibels.
total harmonic distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal
and is expressed in decibels.
POST OFFICE BOX 655303
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11
SGLS124A − JULY 2002 − REVISED DECEMBER 2003
APPLICATION INFORMATION
linearity, offset, and gain error using single end supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage
may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage remains at zero until the input code value produces a sufficient positive output voltage to
overcome the negative offset voltage, resulting in the transfer function shown in Figure 10.
Output
Voltage
0V
DAC Code
Negative
Offset
Figure 10. Effect of Negative Offset (Single Supply)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero input code (all inputs 0) and full scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full scale code and the lowest code that produces a positive output voltage.
general function
The TLV5619 is a 12-bit, single supply DAC, based on a resistor string architecture. It consists of a parallel
interface, a power down control logic, a resistor string, and a rail-to-rail output buffer. The output voltage (full
scale determined by reference) is given by:
2 REF CODE [V]
0x1000
Where REF is the reference voltage and CODE is the digital input value, range 0x000 to 0xFFF. A power on
reset initially puts the internal latches to a defined state (all bits zero).
12
POST OFFICE BOX 655303
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SGLS124A − JULY 2002 − REVISED DECEMBER 2003
APPLICATION INFORMATION
parallel interface
The device latches data on the positive edge of WE. It must be enabled with CS low. LDAC low updates the
DAC with the value in the holding latch. LDAC is an asynchronous input and can be held low, if a separate update
is not necessary. However, to control the DAC using the load feature, LDAC can be driven low after the positive
WE edge.
TMS320C2XX, 5X
A(0−15)
TLV5619
IS
Address
Decoder
CS
LDAC
WE
WE
D(0−11)
D(0−15)
Figure 11. Proposed Interface Between TLV5619 and TMS320C2XX, 5X DSPs
TMS320C3X
A(0−15)
TLV5619
Address
Decoder
TCLK0
CS
LDAC
R/W
WE
IOSTROBE
D(0−11)
D(0−15)
Figure 12. Proposed Interface Between TLV5619 and TMS320C3X DSPs
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SGLS124A − JULY 2002 − REVISED DECEMBER 2003
APPLICATION INFORMATION
TLV5619 interfaced to TMS320C203 DSP
hardware interface
Figure 13 shows an example of the connection between the TLV5619 and the TMS320C203 DSP. The only
other device that is needed in addition to the DSP and the DAC is the 74AC138 address decoding circuit . Using
this configuration, the DAC address is 0x0084 within the I/O memory space of the TMS320C203.
LDAC is held low so that the output voltage is updated with the rising WE edge. The power down mode is
deactivated permanently by pulling PD to VDD.
TMS320C203
74AC138
A2
A
A3
A4
B
Y1
C
5V
G1
G2A
A6
IS
G2B
TLV5619
12
D(0−11)
D(0−11)
VDD
PD
CS
OUT
WE
WE
REF191
Output
RLOAD
LDAC
REFIN
Figure 13. TLV5619 to TMS320C203 DSP Interface Connection
software
No setup procedure is needed to access the TLV5619. The output voltage can be set using one command:
out data_addr,
DAC_addr
Where data_addr points to the address location (in this example 0x0060) holding the new output voltage data
and DAC_addr is the I/O space address of the TLV5619 (in this example 0x0084).
The following code shows, how to use the timer of the TMS320C203 as a time base to generate a voltage ramp
with the TLV5619. A timer interrupt is generated every 205 µs. The corresponding interrupt service routine
increments the output code (stored at 0x0060) for the DAC and writes the new code to the TLV5619. Only the
12 LSBs of the data in 0x0060 are used by the DAC, so that the resulting period of the saw waveform is:
τ = 4096 × 205 E-6 s = 0.84 s
14
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SGLS124A − JULY 2002 − REVISED DECEMBER 2003
APPLICATION INFORMATION
software listing
; File: ramp.asm
; Description: This program generates a ramp.
;−−−−−−−−−−−−− I/O and memory mapped regs −−−−−−−−−−−
.include “regs.asm”
TLV5619
.equ
0084h
;−−−−−−−−−−−−− vectors −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
.ps
0h
b
start
b
INT1
b
INT23
b
TIM_ISR
*********************************************************************
* Main Program
*********************************************************************
.ps
1000h
.entry
start:
ldp
#0
; set data page to 0
; disable interrupts
setc
INTM
; disable maskable interrupts
splk
#0ffffh, IFR
splk
#0004h,
IMR
; set up the timer
splk
#0000h,
60h
splk
#0042h,
61h
out
61h, PRD
out
60h, TIM
splk
#0c2fh,
62h
out
62h,
TCR
; enable interrupts
clrc
INTM
; enable maskable interrupts
; loop forever!
next
idle
; wait for interrupt
b
next
; all else fails stop here
done
b
done ; hang there
*********************************************************************
* Interrupt Service Routines
*********************************************************************
INT1:
ret
; do nothing and return
INT23:
ret
; do nothing and return
TIM_ISR:
; useful code
add
#1h ; increment accumulator
sacl
60h
out
60h, TLV5619 ; write to DAC
clrc
intm ; re-enable interrupts
ret
; return from interrupt
.end
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TLV5619QDWREP
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
V62/03615-01XE
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV5619-EP :
• Catalog: TLV5619
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TLV5619QDWREP
Package Package Pins
Type Drawing
SOIC
DW
20
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.8
13.1
2.65
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jul-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV5619QDWREP
SOIC
DW
20
2000
346.0
346.0
41.0
Pack Materials-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TLV5619QDWREP
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
V62/03615-01XE
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV5619-EP :
• Catalog: TLV5619
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TLV5619QDWREP
Package Package Pins
Type Drawing
SOIC
DW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
10.8
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.1
2.65
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV5619QDWREP
SOIC
DW
20
2000
367.0
367.0
45.0
Pack Materials-Page 2
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