SLIS008 − D3282, AUGUST 1989 − REVISED JUNE 1990 • • • • • • • • • KV PACKAGE (TOP VIEW) 8-Bit Serial-In Parallel-Out Driver 1-A Output Current Capability Per Channel or 8-A Total Current Overcurrent Limiting and Out-of-Saturation Voltage Protection on Driver Outputs Contains Eight Open-Collector Saturating Sink Outputs With Low On-State Voltage High-Impedance Inputs With Hysteresis Are Compatible With TTL or CMOS Levels Very Low Standby Power 20 mW Typical Status of Output Drivers May Be Monitored at Serial Output 3-State Serial Output Permits Serial Cascading or Wire-AND Device Connections 25-V Transient Clamping With Inductive Switching on Outputs, 40-mJ Rating Per Driver Output 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Y4 Y5 Y6 Y7 RST VCC SO GND SI SCLK SIOE Y0 Y1 Y2 Y3 The tab is electrically connected to GND. description The TPIC2801 octal intelligent-power switch is a monolithic BIDFET† integrated circuit designed to sink currents up to 1 A at 30 V simultaneously at each of eight driver outputs under serial input data control. Status of the individual driver outputs is available in serial data format. The driver outputs have overcurrent limiting and out-of-saturation voltage protection features. Applications include driving solenoids, relays, dc motors, lamps, and other medium-current or high-voltage loads. The device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit parallel latch, which independently controls each of the eight Y-output drivers. Data is entered into the device serially via the serial input (SI) and goes directly into the lowest bit (0) of the shift register. Using proper timing signals, the input data is passed to the corresponding output latch and output driver. A logic-high bit at SI turns the corresponding output driver (Yn)off. A logic-low bit at SI turns the corresponding output driver on. Serial data is transferred into SI on the high-to-low transition of serial clock (SCLK) input in 8-bit bytes with data for the Y7 output (most significant bit) first and data for Y0 output (least significant bit) last. Both SI and SCLK are active when serial input-output enable (SIOE) input is low and are disabled when SIOE is high. Each driver output is monitored by a voltage comparator that compares the Y-output voltage level with an internal out-of-saturation threshold voltage reference level. The logic state of the comparator output is dependent upon whether the Y output is greater or smaller than the reference voltage level. An activated driver output is unlatched and turned off when the output voltage exceeds the out-of-saturation threshold voltage level except when the internal unlatch enable is low and disabled. The high-to-low transition of SIOE transfers the logic state of the comparator output to the shift register. † BIDFET − Bipolar, double-diffused, N-channel and P-channel MOS transistors on same chip. This is a patented process. Copyright 1990, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • 2−1 SLIS008 − D3282, AUGUST 1989 − REVISED JUNE 1990 logic symbol† RST 11 [SER PERIF DRIV] S6 G7 tUD 7 SIOE 5 S C5 7R 7G8/7EN9 7C4 7C2 SCLK 6 8C3 SRG8 8C1/8 SI 7 8, 1D 10, 2D 11, 2D 6 4D 10 5S 6 4D 10 5S 6 [1.8 V] 6 3 Z11 2 15 14 13 12 6 6 4D 17 5S 6 3D [1.8 V] Z17 9 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • Y2 Y3 Y4 Y5 Y6 Y7 VCOMP † This symbol is in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication 617-12. 2−2 Y1 VCOMP 1 17, 2D Y0 VCOMP Z10 [1.8 V] 4 9 SO SLIS008 − D3282, AUGUST 1989 − REVISED JUNE 1990 logic diagram (positive logic) RST SIOE 11 5 S SRG8 S SCLK 6 C4 C1/ C2 SI 7 5 tUD UE C5 R 1D 2D Curr Limit 4D 5S 4 3 2D 2 1 15 14 13 12 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 8 8 8 8 8 GND 1.8 V 3D 9 SO C3 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • 2−3 SLIS008 − D3282, AUGUST 1989 − REVISED JUNE 1990 Terminal Functions PIN I/O DESCRIPTION NAME NO. GND 8 RST 11 I SCLK 6 I SI 7 I Serial input. This terminal is the serial data input. A high on this terminal programs a particular output off, and a low turns it on. SIOE 5 I Serial input-output enable. Data is transferred from the shift registers to the power outputs on the rising edge of this signal. The falling edge of this signal parallel loads the output voltage sense bits from the power output stages into the shift register. The output driver for SO is enabled when this terminal is low, provided RST is high. SO 9 O Serial output. This terminal is the serial 3-state output from the shift register and is in a high-impedance state when SIOE is high or RST is low. A high for a data bit on this terminal indicates that the corresponding power output (Yn) is high. This means that the output was programmed to be off the last time a byte was input to the device or that the output faulted and was latched off by the output voltage-sense indicator. A low on this output indicates that the corresponding power output (Yn) is low (on output stage or open-circuit condition). VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Ground. Common return for entire chip. The current from this terminal is potentially as high as 4 A if all outputs are on. GND is used for both logic and power circuits. 10 4 3 2 1 15 14 13 12 Reset. An asynchronous reset is provided for the shift register and the parallel latches. This terminal is active when low and has no internal pullup. When active, it causes the power outputs to turn off. A power-on clear can be implemented using an RC network to VCC. Serial clock. This terminal clocks the shift register. The serial output (SO) changes state on the rising edge of SCLK and serial input (SI) data is accepted on the falling edge. 5-V supply voltage O Power outputs. These outputs are provided with current limiting and voltage sense for fault indication and protection. The nominal load current for these outputs is 500 mA, and the current limiting is set to a minimum of 1.2 A. The active-low outputs also have voltage clamps set at about 35 V for recirculation of inductive load current. Internal 90-kΩ pulldown resistors are provided at each output. These resistors hold the output low during an open-circuit condition. schematic of inputs and outputs EQUIVALENT OF SERIAL OUTPUT (SO) EQUIVALENT OF ALL LOGIC INPUTS (SI, SCLK, SIOE, RST) EQUIVALENT OF Y OUTPUTS (Yn) VCC VCC VCC Output 34 V Input 90 kΩ Output GND VBE ≈ 30 mV All resistor and voltage values shown are nominal. 2−4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • 0.025 Ω SLIS008 − D3282, AUGUST 1989 − REVISED JUNE 1990 absolute maximum ratings over operating temperature range (unless otherwise noted) Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 7 V Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −15 mA Peak output sink current at Y, IO repetitive, tw = 10 ms, duty cycle = 50%, (see Notes 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally limited Continuous output current at Y, IO (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A Peak current through GND: Nonrepetitive tw = 0.2 ms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 8 A Repetitive, tw = 10 ms, duty cycle = 50% . . . . . . . . . . . . . . . . . . . . . . . . . . − 6 A Continuous current through GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 4.5 A Output clamp energy, EOK (after turning off IO(on) = 0.5 A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mJ Continuous dissipation at (or below) TA = 25°C (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.575 W Continuous dissipation at (or below) TC = 75°C (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 W Operating case or virtual junction temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 150°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C Lead temperature 1, 6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C NOTES: 1. All voltage values are with respect to network GND. 2. Each Y output is individually current limited with a typical overcurrent limit of about 1.4 A. 3. Multiple Y outputs of this device can conduct rated current simultaneously; however, power dissipation (average) over a short time interval must fall within the continuous dissipation range and the GND current must fall within the GND-terminal current range. 4. For operation above 25°C free-air temperature, derate linearly at the rate of 28.6 mW/°C. For operation above 75°C case temperature, derate linearly at the rate of 333 mW/°C. To avoid exceeding the maximum virtual junction temperature, these ratings must not be exceeded. recommended operating conditions Supply voltage, VCC MIN NOM MAX UNIT 4.75 5 5.25 V High-level input voltage, VIH 0.7 VCC 5.25 V Low-level input voltage, VIL −0.3 0.2 VCC V Output voltage, VO(off) 30 Continuous output current, IO(on) Operating case temperature, TC −40 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • 25 V 1 A 105 °C 2−5 SLIS008 − D3282, AUGUST 1989 − REVISED JUNE 1990 electrical characteristics over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) driver array outputs (Y0 to Y7) PARAMETER VOK VO(on) Output clamp voltage On-state output voltage TEST CONDITIONS IO = 0.5 A, With output programmed on MIN TYP† MAX 30 36 40 V 0.4 0.5 V 0.6 1 V 0.8 1.5 V 1.8 2 V 1 mA Output programmed off and current shunted to GND IOL = 0.5 A IOL = 0.75 A IOL = 1 A, During unlatch disable With output programmed on and an overcurrent fault condition VTOS Out-of-saturation threshold voltage IO(off) Off-state output current VO = 24 V with output programmed off IO(cl) Output current limit VO = 3 V with output programmed on 1.6 1.05 1.4 UNIT A shift register (inputs SI, SIOE, SCLK, and RST) PARAMETER VT + VT − Positive-going threshold voltage Vhys II Hysteresis voltage (VT+ − VT−) Ci Input capacitance TEST CONDITIONS MIN Negative-going threshold voltage MAX UNIT 0.7 VCC V 0.2 VCC V 0.85 Input current 2.25 V ± 10 µA 20 pF TYP† MAX UNIT 0.2 0.4 VI = 0 to VCC VI = 0 to VCC shift register (output SO) PARAMETER TEST CONDITIONS VOL VOH Low-level output voltage High-level output voltage IO = 1.6 mA IO = − 0.8 mA IO Output current VO = 0 to VCC, ICC Supply current Co Output capacitance † All typical values are at VCC = 5 V, TJ = 25°C. 2−6 MIN VCC −1.3 V SIOE input high ± 10 TJ = 105°C TJ = 25°C 150 250 All outputs off TJ = − 40°C TJ = 25°C VO = 0 to VCC, SIOE input high All outputs on, IO = 0.5 A at all outputs • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • V 200 4 µA mA 10 20 pF SLIS008 − D3282, AUGUST 1989 − REVISED JUNE 1990 timing requirements over receommended ranges of supply voltage and operating case temperature (see Figure 1) MIN MAX UNIT 0 500 kHz fclock tw(SCLKH) Clock frequency, SCLK tw(SCLKL) tw(RST) Pulse duration, SCLK low Pulse duration, RST low tsu1 tsu2 Setup time, SIOE↓ before SCLK↑ 1000 ns Setup time, SCLK↓ before SIOE↑ 1000 ns tsu3 th1 Setup time, SI high before SCLK↓ 500 ns Hold time, SI low after SCLK↓ 500 ns tr tf Rise time (SCLK, SI, SIOE) 2 µs Fall time (SCLK, SI, SIOE) 2 µs Pulse duration, SCLK high See Note 5 840 ns 840 ns 1000 ns NOTE 5: For cascaded operation, the clock pulse durations [tw (SCLKL) and tw (SCLKH) ] must be a minimum of 700 ns (giving a maximum clock frequency of 632 kHz). thermal characteristics PARAMETER RθJC Thermal resistance, junction-to-case temperature RθJA Thermal resistance, junction-to-ambient temperature MIN MAX UNIT 3 °C/W 35 °C/W switching characteristics over recommended ranges of supply voltage and operating case temperature PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN MAX UNIT ten tdis Enable time SIOE↓ SO CL = 20 pF, RL = 2 kΩ, See Figure 2 1000 ns Disable time SIOE↑ SO CL = 20 pF, RL = 2 kΩ, See Figure 2 1000 ns td1 td2 Delay time, valid data SCLK↑ SO CL = 200 pF, See Figure 3 740 ns Delay time, unlatch disable SIOE↑ Yn CL = 20 pF, RL = 5 Ω, 250 µs tr(SO) Rise time, SO CL = 200 pF, See Figure 3 150 ns tf(SO) Fall time, SO CL = 200 pF, See Figure 3 150 ns td(on) Delay time, turn on SIOE↑ Yn CL = 20 pF, See Figure 5 RL = 28 Ω, IOL = 500 mA, 10 µs td(off) Delay time, turn off SIOE↑ Yn CL = 20 pF, See Figure 5 RL = 28 Ω, IOL = 500 mA, 10 µs tv Valid time, SO output data remains valid after SCLK high SCLK↑ SO CL = 200 pF, See Figure 3 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • See Figure 4 75 0 ns 2−7 SLIS008 − D3282, AUGUST 1989 − REVISED JUNE 1990 PARAMETER MEASUREMENT INFORMATION VIH RST 10% tw(RST) 10% VIL VIH SIOE 10% 10% tsu1 tw(SCLKH) 90% SCLK 90% 10% tsu3 SI tr 10% tw(SCLKL) 10% ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ tf th 90% 90% Valid 10% 10% Don’t Care VIH 90% 90% 10% ÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇ Don’t Care Valid Figure 1. Input Timing Waveforms ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ VCC SIOE TPIC2801 Under Test GND RL = 2 kΩ SO 90% 2.5 V TEST CIRCUIT FOR ENABLE AND DISABLE TIMES VIL 10% 5V 90% 2.5 V 10% 0V tdis ten Output CL = 20 pF (see Note A) VIH 10 ns 2.5 V SIOE Input VIL Don’t Care 10 ns 5V VIL tsu2 SO Output Waveform 1 (see Note B) 2.5 V 50% 50% VOL ten SO Output Waveform 2 (see Note B) tdis VOH 50% 50% VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control when SIOE is high. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control when SIOE is high. Figure 2. Test Circuit and Voltage Waveforms for Enable and Disable Times 2−8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • SLIS008 − D3282, AUGUST 1989 − REVISED JUNE 1990 PARAMETER MEASUREMENT INFORMATION 10 ns 5V VCC SCLK TPIC2801 Under Test SCLK Input SO 5V 0.7 VCC 2.5 V 2.5 V 0.2 VCC td1 Output CL = 200 pF (see Note A) GND 10 ns 0 tv SO Output Waveform 1 (see Note B) VOH 0.7 VCC 0.2 VCC VOL tr(SO) td1 TEST CIRCUIT FOR VALID DATA DELAY TIME td1 AND VALID TIME tv tv SO Output Waveform 2 (see Note B) VOH 0.7 VCC 0.2 VCC VOL tf(SO) VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the low-to-high transition of SCLK causes the SO output to switch from low to high. Waveform 2 is for an output with internal conditions such that the low-to-high transition of SCLK causes the SO output to switch from high to low. Figure 3. Test Circuit and Voltage Waveforms for Delay Times 5V 11 V VCC 10 ns 10 ns SIOE Input RL = 5 Ω 10% SIOE TPIC2801 Under Test GND Y Output Y-Output Voltage (see Note B) 10% 5V 0 Voff = 11 V 50% Von = 5 V CL = 20 pF (see Note A) TEST CIRCUIT FOR UNLATCH DISABLE DELAY TIME td2 (see Notes C and D) 90% 90% 2.5 V 2.5 V td2 Y-Output Current (see Note B) IO(CL) = 1.2 A 50% 0 VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Output voltage and current waveforms are for an output with internal conditions such that the low-to-high transition of SIOE causes the output to switch from being off to being on. C. td2 = delay until Y-output current goes off under fault condition. D. Load voltage VS and load resistance RL are selected such that on-state voltage at the Y output under test, Von is greater than the maximum out-of-saturation hold voltage, VTOS. Thus VOL = Von > VTOS(max) = 1.98 V. Figure 4. Test Circuit and Voltage and Current Waveforms for Unlatch Disable Delay • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • 2−9 SLIS008 − D3282, AUGUST 1989 − REVISED JUNE 1990 PARAMETER MEASUREMENT INFORMATION 10 ns 14 V 10 ns 5V SIOE Input VCC SIOE TPIC2801 Under Test 10% RL = 28 Ω Y 90% 90% 2.5 V 2.5 V 5V 10% 0 Output CL = 20 pF (see Note A) Y-Output Waveform 1 (see Note B) tpd(off) 90% 50% 10% GND 14 V VOL tpd(on) TEST CIRCUIT FOR TURN-OFF td(off) AND TURN-ON td(on) DELAY TIMES (see Note C) Y-Output Waveform 2 (see Note B) 14 V 90% 10% 50% VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the low-to-high transition of SIOE causes the output to switch from on to off. Waveform 2 is for an output with internal conditions such that the low-to-high transition of SIOE causes the output to switch from off to on. C. td(off) = tPLH, td(on) = tPHL. Figure 5. Test Circuit and Voltage Waveforms for Turn-Off and Turn-On Delay Times APPLICATION INFORMATION 10 5 7 Microcontroller With Bus 4 VCC Y0 SIOE Y1 SI Y2 SO Y3 SCLK Y4 RST Y5 GND Y6 L 3 2 9 6 R 1 11 8 15 14 13 12 VCC = 5 V ± 5% R = 30 Ω ± 5% L = 10 mH ±10% 8 Loads up to 0.5 A Each Y7 TPIC2801 Figure 6. Microcontroller Driving Eight Loads Using a TPIC2801 for Load Interface 2−10 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • 14 V ± 0.5 V SLIS008 − D3282, AUGUST 1989 − REVISED JUNE 1990 PRINCIPLES OF OPERATION timing data transfer Figure 7 shows the overall 8-bit data-byte transfer to and from the TPIC2801 interface bus. The logic state of the eight output drivers, Y0 through Y7, is latched into the shift register at time t0 on the high-to-low transition of SIOE. Therefore, the SO output data (DY0, DY1 . . . ) represent the conditions at the Y-driver outputs at time t0. The data at the SO output is updated on the low-to-high transition of SCLK. Input data present at the SI input is clocked into the shift register on the high-to-low transition of SCLK. As shown in Figure 6 on the SI input, input data DI7 is clocked at time t1, DI6 is clocked at time t2, etc. Eight SCLK pulses are used to serially load the eight bits of new data into the device. After all the new data is serially loaded, the low-to-high transition of SIOE parallel loads the new data to the eight driver output latches, which in turn directly control the eight Y-driver outputs. An unlimited amount of data can be shifted through the shift register (into the SI and out the SO), and this allows other devices to be cascaded in a daisy chain with the TPIC2801. Once the last data bit is shifted into the TPIC2801, the SIOE input is pulled high. The clock (SCLK) input is low at both transitions of the SIOE input to avoid any false clocking of the shift register. The SCLK input is gated by the SIOE input, so the SCLK input is ignored whenever SIOE is high. At the rising edge of SIOE, the shift register data is latched into the parallel latch and the output stages are actuated by the new data. An internal 100-µs delay timer is also started on this rising edge. During the time delay, the outputs are protected only by the analog current-limiting circuits, since the resetting of the parallel latches by fault conditions are inhibited during this time period. This allows the device to overcome any high switching currents that can flow during turn on. Once the delay ends, the output voltages are sensed by the comparators and any output voltages higher than nominally 1.8 V are latched off. Time t0 t1↑ t1↓ t2↑ t2↓ t3↑ t3↓ t4↑ t4↓ t5↑ t5↓ t6↑ t6↓ t7↑ t7↓ t8↑ t8↓ t9 H SIOE L H SCLK CP1 ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ SI SO Prior CP2 CP3 CP4 CP5 CP6 CP7 CP8 ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ L H DI7 DY7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 L DY6 DY5 DY4 DY3 DY2 DY1 DY0 H Hi -Z L Y0 Prior (old) H DI0 (new) L Y1 Prior (old) H DI1 (new) L Y7 Prior (old) H DI7 (new) L Figure 7. Data-Byte Transfer Timing • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • 2−11 SLIS008 − D3282, AUGUST 1989 − REVISED JUNE 1990 PRINCIPLES OF OPERATION fault-conditions check Open-circuit conditions on any output can be monitored or checked by programming that output off. After a short delay (microseconds), another control byte can be clocked into the device. If the diagnostic bit for that output comes back as a low, it indicates that the output is low and open circuited. A current overload condition can be detected by programming an output on. After waiting an appropriate length of time, another byte is clocked into the TPIC2801. The diagnostic bit clocked back from the TPIC2801 in the subsequent data transfer indicates a low output. If a high returns, a current overload is indicated. A quick overall check is done by clocking in a test control byte. After a sufficient time delay, clock in another control byte (same byte is used). The diagnostic data is exclusive ORed with the original control byte. If a fault condition exists, a high results from the subsequent exclusive OR. 2−12 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77001 • IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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