Preliminary SC3041B ® • Quartz SAW Frequency Stability • Fundamental Fixed Frequency • Excellent Jitter and Symmetry • Rugged, Miniature, Surface-Mount Case • Low-Voltage Power Supply (3.3 VDC) This digital clock is designed for use in abrizio’s chipset for Terabit Router applications. Fundamental-mode oscillation is made possible by surface-acoustic-wave (SAW) technology. The design results in low jitter, compact size, and low power consumption. Differential outputs provide a sine wave that is made to drive 50 Ω loads. Absolute Maximum Rating Power Supply Voltage (VCC at Terminal 1) Value Units 0 to +4.0 VDC Input Voltage (ENABLE at Terminal 8) 0 to +4.0 VDC -40 to +85 °C Case Temperature (Powered or Storage) 300.0 MHz Differential Sine-Wave Clock SMC-8 Case Electrical Characteristics Output Frequency Q and Q Output Characteristic Absolute Frequency Sym fO Tolerance from 286.0 MHz ∆fO Voltage into 50Ω (VSWR ≤ 1.2) VO Notes 1, 2 1, 3 Operating Load VSWR Symmetry 3, 4, 5 Harmonic Spurious Output (Disabled) Maximum 300.060 Units MHz ±200 ppm 4.5 2:1 49 -25 dBm 51 % -20 dBc -60 dBc 30 psP-P No Noise on VCC 3, 4, 6, 7 200 mVP-P from 1 MHz to ½ fO on 3, 4, 7, 8 35 psP-P 3, 9 75 mVP-P Amplitude into 50 Ω 3 Output DC Resistance (between Q & Q) ENABLE (Terminal 14) Input HIGH Voltage VIH Input LOW Voltage VIL Input HIGH Current IIH DC Power Supply Typical 0.5 3, 4, 6 Nonharmonic Spurious Q and Q Period Jitter Minimum 299.940 Input LOW Current IIL Propagation Delay tPD Operating Voltage VCC Operating Current ICC Operating Ambient Temperature 15 100 VCC-0.1 KΩ VCC 0.0 TA +3.13 V 5 mA -1 mA 1 ms +3.47 VDC 40 mA +70 °C 18 1, 3 Lid Symbolization (YY = Year, WW = Week) +3.30 0 V 0.20 3 3, 9 1, 3 VCC+0.1 RFM SC3041B 300.00 MHz YYWW CAUTION: Electrostatic Sensitive Device. Observe precautions for handling. NOTES: 1. 2. 3. 4. 5. Unless otherwise noted, all specifications include any combination of load VSWR, VCC, and TA. In addition, Q and Q are terminated into 50 Ω loads to ground. (See: Typical Test Circuit.) One or more of the following United States patents apply: 4,616,197; 4,670,681; 4,760,352. The design, manufacturing process, and specifications of this device are subject to change without notice. Only under the nominal conditions of 50 Ω load impedance with VSWR ≤ 1.2 and nominal power supply voltage. Symmetry is defined as the pulse width (in percent of total period) measured at the 50% points of Q or Q. (See: Timing Definitions.) 6. 7. 8. 9. Jitter and other spurious outputs induced by externally generated electrical noise on VCC or mechanical vibration are not included. Dedicated external voltage regulation and careful PCB layout are recommended for optimum performance. Applies to period jitter of Q and Q. Measurements are made with the Tektronix CSA803 signal analyzer with at least 1000 samples. Period jitter measured with a 200 mVP-P sine wave swept from 1 MHz to one-half of fO at the VCC power supply terminal. The outputs are enabled when Terminal 8 is at logic HIGH. Propagation delay is defined as the time from the 50% point on the rising edge of ENABLE to the 90% point on the rising edge of the output amplitude or as the fall time from the 50% point to the 10% point. (SEE: Timing Definitions.) RF Monolithics, Inc. Phone: (972) 233-2903 Fax: (972) 387-9148 RFM Europe Phone: 44 1963 251383 Fax: 44 1963 251510 ©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc. E-mail: [email protected] http://www.rfm.com SC3041B-113000 Page 1 of 2 300.0 MHz Differential Sine-Wave Clock Electrical Connections Footprint Actual size footprint: Terminal Number Connection 1 VCC 2 Ground 3 NC or Ground 4 Q Output 5 Q Output 1 8 2 7 3 6 4 5 Typical Printed Circuit Board Land Pattern A typical land pattern for a circuit board is shown below. Grounding of the metallic center pad is optional. TOP VIEW 6 Ground 7 8 ENABLE LID Ground Typically 0.01" to 0.05" or 0.25 mm to 1.25 mm (8 Places) Case Design (The optimum value of this dimension is dependent on the PCB assembly process employed.) All pads consist of 30 microinches (min) electroless gold on 50 microinches (min) electroless nickel over base metal. The metallic center pad was designed for mechanical support. Grounding of this pad is optional. Lid symbolization, including terminal 1 locator dot, are in contrasting ink. Symbolization varies by model number. For purposes of illustration, only terminal 1 dot is shown. . Typical Test Circuit 0.1 µF V cc B D C N (X8) F (X8) 50 Ω V cc A M G * Ch 1 Trigger Q Clock Under Test (X3) L Tektronix CSA 803 Digitizing Oscilloscope Sine-Wave Signal Generator 4.7 µH E 50 Ω * Ch 2 Q ENABLE H (X2) 50 Ω K J *Power Splitter, Mini-Circuits ZFSC2-4 Timing Definitions Propagation Delay: Dimensions Millimeters ENABLE Inches 50% Min Max Min Max A 13.46 13.97 0.530 0.550 B 9.14 9.66 0.360 0.380 C 2.05 Nominal 0.081 Nominal D 3.56 Nominal 0.141 Nominal E 2.24 Nominal 0.088 Nominal F 1.27 Nominal 0.050 Nominal G 2.54 Nominal 0.100 Nominal H 3.05 Nominal 0.120 Nominal J 1.93 Nominal 0.076 Nominal K 5.54 Nominal 0.218 Nominal L 4.32 Nominal 0.170 Nominal M 4.83 Nominal 0.190 Nominal N 0.50 Nominal 0.020 Nominal RF Monolithics, Inc. Phone: (972) 233-2903 Fax: (972) 387-9148 RFM Europe Phone: 44 1963 251383 Fax: 44 1963 251510 ©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc. 50% 90% Q or Q Output Amplitude Envelope 10% t PD t PD Symmetry: Q or Q Output 50% 50% Symmetry as % of Period 50% Symmetry as % of Period Period E-mail: [email protected] http://www.rfm.com SC3041B-113000 Page 2 of 2