TI CSD95373AQ5M

CSD95373AQ5M
www.ti.com
SLPS458 – DECEMBER 2013
Synchronous Buck NexFET™ Power Stage
FEATURES
APPLICATIONS
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1
23
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45 A Continuous Operating Current Capability
92.6% System Efficiency at 25 A
Ultra-Low Power Loss of 2.6 W at 25 A
High Frequency Operation (up to 2 MHz)
High Density – SON 5 x 6-mm Footprint
Ultra-Low Inductance Package
System Optimized PCB Footprint
3.3 V and 5 V PWM Signal Compatible
Diode Emulation Mode with FCCM
Analog Temperature Output
Input Voltages up to 14.5 V
Three-State PWM Input
Integrated Bootstrap Switch
Optimized Dead Time for Shoot Through
Protection
RoHS Compliant – Lead-Free Terminal Plating
Halogen Free
Multiphase Synchronous Buck Converter
– High Frequency Applications
– High Current, Low Duty Cycle Applications
Point-of-Load DC-DC Converters
Memory and Graphic Cards
Desktop and Server VR11.x and VR12.x for
VCore Synchronous Buck Converters
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ORDERING INFORMATION
Device
Package
Media
CSD95373AQ5M
SON 5 × 6-mm
Plastic Package
13-Inch
Reel
Qty
Ship
2500
Tape and
Reel
DESCRIPTION
VIN
VOUT
VCC
VCC
VOUT
PWM1
+Is1
-Is2
+NTC
-NTC
+Is2
-Is2
PWM2
VOUT
SS
RT
Efficiency (%)
CSD95373A
100
10
90
9
80
8
7
70
60
6
VDD = 5V
VIN = 12V
VOUT = 1.2V
LOUT = .22µH
fSW = 500kHz
TA = 25ºC
50
40
30
20
5
4
3
2
1
10
0
0
5
10
15
20
25
30
Output Current (A)
35
40
45
PGND
TPS53640
Controller
Power Loss (W)
The CSD95373AQ5M NexFET™ Power Stage is a highly optimized design for use in a high-power, high-density
synchronous buck converters. This product integrates the driver IC and NexFET technology to complete the
power stage switching function. The driver IC has a built-in selectable diode emulation function that enables
DCM operation to improve light load efficiency. This combination produces high current, high efficiency, and high
speed switching capability in a small 5 x 6 mm outline package. It also integrates the temperature sensing
functionality to simplify system design and improve accuracy. In addition, the PCB footprint has been optimized
to help reduce design time and simplify the completion of the overall system design.
0
G001
CSD95373A
Figure 1. Application Diagram
Figure 2. Efficiency and Power Loss
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NexFET is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
CSD95373AQ5M
SLPS458 – DECEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1)
TA = 25°C (unless otherwise noted)
VALUE
UNIT
MIN
MAX
VIN to PGND
–0.3
25
V
VIN to VSW
–0.3
25
V
VIN to VSW (<10 ns)
VSW to PGND
VSW to PGND (<10 ns)
–7
27
V
–0.3
20
V
–7
23
V
VDD to PGND
–0.3
7
V
ENABLE, PWM, FCCM, TAO to PGND (2)
–0.3
VDD + 0.3
V
BOOT to BOOT_R (2)
–0.3
VDD + 0.3
V
Human Body Model (HBM)
2000
V
Charged Device Model (CDM)
500
V
12
W
ESD Rating
Power Dissipation, PD
Operating Temperature Range, TJ
–55
150
°C
Storage Temperature Range, TSTG
–55
150
°C
(1)
(2)
Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating
Conditions" is not implied. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability.
Should not exceed 7 V
RECOMMENDED OPERATING CONDITIONS
TA = 25° (unless otherwise noted)
Parameter
Conditions
MIN
Gate Drive Voltage, VDD
4.5
Input Supply Voltage, VIN
Output Voltage, VOUT
Continuous Output Current, IOUT
Peak Output Current, IOUT-PK
(2)
VIN = 12 V, VDD = 5 V, VOUT = 1.8 V,
fSW = 500 kHz, LOUT = 0.22 µH (1)
Switching Frequency, fSW
CBST = 0.1 µF (min)
On Time Duty Cycle
fSW = 1 MHz
UNIT
5.5
V
14.5
V
5.5
V
45
A
67
A
2000
Minimum PWM On Time
20
Operating Temperature
–40
(1)
(2)
MAX
kHz
85
%
125
°C
ns
Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
System conditions as defined in Note 1. Peak Output Current is applied for tp = 50 µs
THERMAL INFORMATION
TA = 25°C (unless otherwise noted)
PARAMETER
RθJC
RθJB
(1)
(2)
2
Thermal Resistance, Junction-to-Case (Top of package) (1)
Thermal Resistance, Junction-to-Board
(2)
MIN
TYP
MAX
UNIT
15
°C/W
2
°C/W
RθJC is determined with the device mounted on a 1-inch² (6.45-cm²), 2-oz (.071-mm thick) Cu pad on a 1.5-inch x 1.5-inch, 0.06-inch
(1.52-mm) thick FR4 board.
RθJB value based on hottest board temperature within 1 mm of the package.
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CSD95373AQ5M
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SLPS458 – DECEMBER 2013
ELECTRICAL CHARACTERISTICS
TA = 25°C, VDD = POR to 5.5 V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
PLOSS
Power Loss (1)
VIN = 12 V, VDD = 5 V, VOUT = 1.2 V, IOUT = 25 A,
fSW = 500 kHz, LOUT = 0.22 µH , TJ = 25°C
2.6
W
Power Loss (2)
VIN = 12 V, VDD = 5 V, VOUT = 1.2 V, IOUT = 25 A,
fSW = 500 kHz, LOUT = 0.22 µH , TJ = 125°C
3.3
W
VIN
VIN Quiescent Current, IQ
ENABLE = 0, VDD = 5 V
10
µA
Standby Supply Current, IDD
ENABLE = 0, PWM = 0
250
µA
Operating Supply Current, IDD
ENABLE = 5 V, PWM = 50% Duty cycle,
fSW = 500 kHz
VDD
16
mA
POWER-ON RESET AND UNDER VOLTAGE LOCKOUT
Power-On Reset, VDD Rising
3.6
3.9
UVLO, VDD Falling
3.4
3.7
V
Hysteresis
100
250
mV
Startup Delay (3)
ENABLE = 5 V
6
V
µs
ENABLE
Logic Level High, VIH
2.0
V
Logic Level Low, VIL
Weak Low Down Impedance
0.8
Scmitt Trigger Input
See Figure 15
V
100
kΩ
Rising Propagation Delay, tPDH
3
µs
Falling Propagation Delay, tPDL
30
ns
FCCM
(2)
Logic Level High, VIH
Logic Level Low, VIL
2.0
V
Scmitt Trigger Input
See Figure 17 and Figure 18
0.8
Weak Pull-Up Current
V
5
µA
165
°C
25
°C
THERMAL SHUTDOWN (2)
Start Threshold
Temperature Hysteresis
(1)
(2)
(3)
150
Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins
Specified by design
POR to VSW Rising
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ELECTRICAL CHARACTERISTICS (continued)
TA = 25°C, VDD = POR to 5.5 V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
PWM
IPWMH
PWM = 5V
IPWML
PWM = 0
500
µA
–500
µA
PWM Logic Level High, VPWMH
2.3
2.5
2.7
V
PWM Logic Level Low, VPWML
0.7
0.9
1.1
V
PWM Three-State Open Voltage
PWM to VSW Propagation Delay, tPDLH and
tPDHL (4)
CPWM = 10 pF
1.5
V
50
ns
Three-State Shutdown Hold-off Time, t3HT (4)
30
Three-State Shutdown Propagation Delay, t3SD (4)
80
160
ns
Three-State Recovery Propagation Delay, t3RD (4)
50
80
ns
Diode Emulation Minimum On Time, tDEM
(4)
ns
150
ns
BOOTSTRAP SWITCH
Forward Voltage, VFBOOT
Reverse Leakage, IRBOOT
(5)
Measured from VDD to VBOOT, IF = 10 mA
200
360
mV
VBOOT – VDD = 20 V
0.15
1
µA
1.1
A
ZERO CROSSING COMPARATOR
LS FET Turn-off Current
Diode Emulation Mode Enabled
VOUT = 1.8 V, L = 150 nH
0
THERMAL ANALOG OUTPUT TAO
Output Voltage at 25°C
Output Voltage Temperature Coefficient
(4)
(5)
4
0.56
0.60
8
0.64
V
mV/°C
Specified by design
Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins
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SLPS458 – DECEMBER 2013
TYPICAL CHARACTERISTICS
TJ = 125°C, unless stated otherwise.
14
1.1
12
8
6
4
2
0
VIN = 12V
VDD = 5V
VOUT = 1.2V
fSW = 500kHz
LOUT = 0.22µH
1
0.9
0.8
0.7
Typ
Max
0
5
10
15
20
25
30
Output Current (A)
35
40
0.6
−50
45
Figure 3. Power Loss vs Output Current
Output Current (A)
Output Current (A)
VIN = 12V
VDD = 5V
VOUT = 1.2V
fSW = 500kHz
LOUT = 0.22µH
20
10
G001
0
10
20
30
25
20
VIN = 12V
VDD = 5V
VOUT = 1.2V
fSW = 500kHz
LOUT = 0.22µH
15
10
5
30
40
50
60
70
Ambient Temperature (ºC)
80
0
90
7.8
5.2
1.1
2.6
1
0.0
−2.6
2200
Figure 7. Normalized Power Loss vs Frequency
Copyright © 2013, Texas Instruments Incorporated
40
60
80
100
Board Temperature (ºC)
120
Figure 6. Typical Safe Operating Area
G001
3.1
1.08
2.6
2.1
1.06
1.6
1.04
1.0
1.02
0.5
1
0.0
0.98
G001
140
(1)
VDD = 5V
VOUT = 1.2V
LOUT = 0.22µH
fSW = 500kHz
IOUT = 45A
1.1
Power Loss, Normalized
10.4
1.2
1000
1400
1800
Switching Frequency (kHz)
20
1.12
SOA Temperature Adj (ºC)
VIN = 12V
VDD = 5V
VOUT = 1.2V
LOUT = 0.22µH
IOUT = 45A
0
G001
13.0
1.5
600
Min
Typ
35
Figure 5. Safe Operating Area – PCB Horizontal Mount (1)
Power Loss, Normalized
150
40
30
0.9
200
125
45
40
1.3
25
50
75
100
Junction Temperature (ºC)
50
400LFM
200LFM
100LFM
Nat Conv
50
1.4
0
Figure 4. Power Loss vs Temperature
60
0
−25
G001
3
5
7
9
11
Input Voltage (V)
13
15
17
SOA Temperature Adj (ºC)
Power Loss (W)
10
Power Loss, Normalized
VIN = 12V
VDD = 5V
VOUT = 1.2V
fSW = 500kHz
LOUT = 0.22µH
−0.5
G001
Figure 8. Normalized Power Loss vs Input Voltage
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TYPICAL CHARACTERISTICS (continued)
TJ = 125°C, unless stated otherwise.
1.6
VIN = 12V
VDD = 5V
VOUT = 1.2V
fSW = 500kHz
IOUT = 45A
1.07
20.9
15.7
1.4
10.5
1.2
5.2
0
1
Power Loss, Normalized
1.8
2.1
1.08
SOA Temperature Adj (ºC)
Power Loss, Normalized
VIN = 12V
VDD = 5V
fSW = 500kHz
LOUT = 0.22µH
IOUT = 45A
1.06
1.05
0
1
2
3
4
Output Voltage (V)
5
6
−5.2
1.3
1
1.03
0.8
1.02
0.5
1.01
0.3
0
0.99
100
120
G001
Figure 9. Normalized Power Loss vs Output Voltage
1.6
1.04
1
0.8
1.8
SOA Temperature Adj (ºC)
26.2
2
140
160
180
200
Output Inductance (nH)
220
−0.3
240
G001
Figure 10. Normalized Power Loss vs Output Inductance
70
Driver Current (mA)
60
50
VIN = 12V
VDD = 5V
VOUT = 1.2V
LOUT = 0.22µH
IOUT = 45A
40
30
20
10
0
200
600
1000
1400
1800
Switching Frequency (kHz)
2200
G000
Figure 11. Driver Current vs Frequency
1. The typical CSD95373AQ5M system characteristic curves are based on measurements made on a PCB design with
dimensions of 4.0 in. (W) x 3.5 in. (L) x 0.062 in. (T) and 6 copper layers of 1 oz. copper thickness. See the Application
Information section for detailed explanation.
6
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SLPS458 – DECEMBER 2013
PIN CONFIGURATION
NC
1
12
PWM
NC
2
11
TAO
ENABLE
3
10
FCCM
NC
4
9
BOOT
VDD
5
8
BOOT_R
VSW
6
7
VIN
13
PGND
Figure 12. Top View
Table 1. PIN DESCRIPTION
PIN
NO.
DESCRIPTION
NAME
1, 2, 4
NC
3
ENABLE
No Connect, must leave floating
Enables device operation. If ENABLE = logic HIGH, turns on device. If ENABLE = logic LOW, the device is turned off
and both MOSFET gates are actively pulled low. An internal 100 kΩ pulldown resistor pulls the ENABLE pin LOW if
left floating.
5
VDD
Supply Voltage to Gate Driver and internal circuitry
6
VSW
Phase node connecting the HS MOSFET Source and LS MOSFET Drain - pin connection to the output inductor
7
VIN
Input Voltage Pin. Connect input capacitors close to this pin.
8
BOOT_R
Return path for HS gate driver, connected to VSW internally
9
BOOT
Bootstrap capacitor connection. Connect a minimum of 0.1 µF 16 V X7R, ceramic capacitor from BOOT to BOOT_R
pins. The bootstrap capacitor provides the charge to turn on the Control FET. The bootstrap diode is integrated.
10
FCCM
This pin enables the Diode Emulation function. When this pin is held LOW, Diode Emulation Mode is enabled for Sync
FET. When FCCM is HIGH, the device operated in Forced Continuous Conduction Mode. An internal 5 µA current
source will pull the FCCM pin to VDD if left floating.
11
TAO/
FAULT
Temperature amplifier output. Reports a voltage proportional to the die temperature. An ORing diode is integrated in
the IC. When used in multiphase application, a single wire can be used to connect the TAO pins of all the ICs. Only
the highest temperature is reported. TAO is pulled up to 3 V if Thermal Shutdown occurs. TAO should be bypassed to
PGND with a 1 nF 16 V X6R ceramic capacitor.
12
PWM
Pulse width modulated 3-state input from external controller. Logic LOW sets Control FET gate low and Sync FET
gate high. Logic HIGH sets Control FET gate high and Sync FET gate low. Open or High Z sets both MOSFET gates
low if greater than the 3-State Shutdown Hold-off Time (t3HT)
13
PGND
Power Ground
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ENABLE (3) FCCM (10)
VDD (5)
−
NC (2)
+
NC (4)
POR
PWMH
PWML
+
−
HG
Gate Driver Logic
SW
PWMT
+
VSW (6)
Tri-State Logic
PWM (12)
BOOT (9)
BOOT_R (8)
VIN (7)
+
−
NC (1)
−
3V LDO
+
−
ZX
LG
Fault Detection
GND
PGND (13)
+
−
+
TAO (11)
Temperature Sense
Thermal Shutdown
−
Figure 13. Functional Block Diagram
FUNCTIONAL DESCRIPTION
POWERING CSD95373AQ5M AND GATE DRIVERS
An external VDD voltage is required to supply the integrated gate driver IC and provide the necessary gate drive
power for the MOSFETs. The gate driver IC is capable of supplying in excess of 4 A peak current into the
MOSFET gates to achieve fast switching. A 1 µF 10 V X5R or higher ceramic capacitor is recommended to
bypass VDD pin to PGND. A bootstrap circuit to provide gate drive power for the Control FET is also included. The
bootstrap supply to drive the Control FET is generated by connecting a 100 nF 16 V X5R ceramic capacitor
between BOOT and BOOT_R pins. An optional RBOOT resistor can be used to slow down the turn on speed of
the Control FET and reduce voltage spikes on the VSW node. A typical 1 to 4.7 Ω value is a compromise between
switching loss and VSW spike amplitude.
UNDERVOLTAGE LOCKOUT PROTECTION (UVLO)
The VDD supply is monitored for UVLO conditions and both Control FET and Sync FET gates are held low until
adequate supply is available. An internal comparator evaluates the VDD voltage level and if VDD is greater than
the Power On Reset threshold (VPOR), the gate driver becomes active. If VDD is less than the UVLO threshold,
the gate driver is disabled and the internal MOSFET gates are actively driven low. At the rising edge of the VDD
voltage, both Control FET and Sync FET gates are actively held low during VDD transitions between 1.0 V to
VPOR. This region is referred to as the Gate Drive Latch Zone (see Figure 14). In addition, at the falling edge of
the VDD voltage, both Control FET and Sync FET gates are actively held low during the UVLO to 1.0 V transition.
The Power Stage CSD95373AQ5M device must be powered up and enabled before the PWM signal is applied.
VDD
VPOR
Gate Drive
Latch Zone
1.0V
UVLO
1.0V
T0487-01
Figure 14. UVLO Operation
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ENABLE
The ENABLE pin is TTL compatible. The logic level thresholds are sustained under all VDD operating conditions
between VPOR to VDD. In addition, if this pin is left floating, a weak internal pulldown resistor of 100 kΩ pulls the
ENABLE pin below the logic level low threshold. The operational functions of this pin should follow the timing
diagram outlined in Figure 15. A logic level low actively holds both Control FET and Sync FET gates low and VDD
pin should typically draw less than 5 µA.
90%
tPDL
ENABLE
tPDH
10%
90%
VSW
10%
T0488-01
Figure 15. CSD95373AQ5M ENABLE Timing Diagram (VDD = PWM = 5V)
POWER UP SEQUENCING
If the ENABLE signal is used, it is necessary to ensure proper co-ordination with the ENABLE and soft-start
features of the external PWM controller in the system. If the CSD95373AQ5M was disabled through ENABLE
without sequencing with the PWM IC controller, the buck converter output will have no voltage or fall below
regulation set point voltage. As a result, the PWM controller IC delivers Max duty cycle on the PWM line. If the
Power Stage is re-enabled by driving the ENABLE pin high, there will be an extremely large input inrush current
when the output voltage builds back up again. The input inrush current might have undesirable consequences
such as inductor saturation, driving the input power supply into current limit or even catastrophic failure of the
CSD95373AQ5M device. Disabling the PWM controller is recommended when the CSD95373AQ5M is disabled.
The PWM controller should always be re-enabled by going through soft-start routine to control and minimize the
input inrush current and reduce current and voltage stress on all buck converter components. TI recommends
that the external PWM controller be disabled when CSD95373AQ5M is disabled or nonoperational because of
UVLO.
When ENABLE signal is toggled, there is an internal 3 µs hold-off time before the driver responds to PWM
events to ensure the analog sensing circuitry is properly powered and stable. This hold-off time should be
considered when designing the power-up sequencing of the controller IC and the Power Stage.
PWM
The input PWM pin incorporates a 3-state function. The Control FET and Sync FET gates are forced low if the
PWM pin is left floating for more than the 3-state Hold off time (t3HT). The 3-state mode can be entered by
actively driving the PWM input to the VT3 voltage, or the PWM input can be made high impedance and internal
current sources drive PWM to VT3. The PWM input can source up to IPWMH and sink down to IPWML current to
drive PWM to the VT3 voltage, but consumes no current when sitting at the VT3 voltage. Operation in and out of
3-state mode should follow the timing diagram outlined in Figure 16. Both VPWML and VPWMH threshold levels are
set to accommodate both 3.3 V and 5 V logic controllers. During typical operation, the PWM signal should be
driven to logic levels Low and High with a maximum of 500 Ω sink/source impedance respectively.
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PWM 3-State Window
VPWMH
PWM
VPWML
t3RD
VOUT
VSW
tPDLH
tPDHL
t3HT + t3SD
t3HT + t3SD
VOUT
t3RD
T0489-01
Figure 16. PWM Timing Diagram
FCCM
The input FCCM pin enables the Power Stage device to operate in either continuous current conduction mode or
diode emulation mode. When FCCM is driven above its high threshold, the Power Stage operates in continuous
conduction mode regardless of the polarity of the output inductor current. When FCCM is driven below its low
threshold, the Power Stage's internal zero-cross detection circuit is enabled. When the zero-cross detection
circuit is active, diode emulation mode is entered on the third consecutive PWM pulse in which a zero-crossing
event is detected. If FCCM is driven high after diode emulation mode has been enabled, continuous conduction
mode begins after the next PWM event. See Figure 17 and Figure 18 for FCCM timing
TAO/FAULT (THERMAL ANALOG OUTPUT/PROTECTION FLAG)
During typical operation, the output TAO pin is a highly accurate analog temperature measurement of the leadframe temperature of the Power Stage. Because the source junction of the Sync FET sits directly on the leadframe of the Power Stage, this output can be used as an accurate measurement of the junction temperature of
the Sync FET. The TAO pin should be bypassed to PGND using a 1 nF X7R ceramic capacitor to ensure accurate
temperature measurement.
This Power Stage device has built-in overtemperature protection (described in OVERTEMPERATURE), which is
flagged by pulling TAO to 3 V. The TAO pin also includes a built in ORing function. When connecting TAO pins
of more than one device together, the TAO bus automatically reads the highest TAO voltage among all devices.
This greatly simplifies the temperature sense and fault reporting design for multi-phase applications, where a
single line TAO/FAULT bus can be used to tie the TAO pins of all phases together and the system can monitor
the temperature of the hottest component.
OVERTEMPERATURE
An overtemperature fault occurs when the dies temperature reaches Thermal Shutdown Temperature (see the
ELECTRICAL CHARACTERISTICS). An overtemperature event is the only fault condition to which the Power
Stage automatically reacts. When the overtemperature event is detected, the Power Stage automatically turns off
both HS and LS MOSFETs and pulls TAO to 3.3 V. If the temperature falls below the overtemperature threshold
hysteresis band, the driver again responds to PWM commands and the TAO pin returns to typical operation. A
weak pulldown is used to pull TAO back from a fault event, so there is a significant delay before the TAO output
reports the correct temperature.
10
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SLPS458 – DECEMBER 2013
GATE DRIVERS
This Power Stage has an internal high-performance gate driver IC that is trimmed to achieve minimum dead-time
for lowest possible switching loss and switch-node ringing reduction. To eliminate the possibility of shoot-through
at light load conditions, the dead-time is adjusted to a longer period when the inductor current is negative prior to
a PWM HIGH input.
PWM
VSW
Vin
Vout
FCCM (OFF#)
LO GATE
During Diode Emulation Mode (DEM) the Lo Gate signal is latched off by the
zero-cross comparator and reset by rising edge of PWM. If FCCM is pulled high
after Lo Gate has been latched off, normal CCM operation does not begin until
after the next PWM pulse.
Figure 17. FCCM Rising Timing Diagram
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PWM
Vin
VSW
Vout
FCCM (OFF#)
LO GATE
Diode Emulation
Enabled
IL
Zero-Cross<1>
Zero-Cross<2>
Zero-cross detection is enabled by FCCM low. Diode-Emulation Mode is entered on the third
consecutive PWM pulse in which a zero-crossing event is detected. If at any time no zero-cross
event is detected when FCCM is low, the zero-cross counter is reset and diode-emulation mode is
not enabled. If FCCM remains low, diode-emulation mode will be re-enabled on the third
consecutive PWM pulse in which a zero-cross event is detected.
Figure 18. FCCM Falling Timing Diagram
12
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SLPS458 – DECEMBER 2013
APPLICATION INFORMATION
The Power Stage CSD95373AQ5M is a highly optimized design for synchronous buck applications using
NexFET devices with a 5 V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield
the lowest power loss and highest system efficiency. As a result, a rating method is used that is tailored towards
a more systems centric environment. The high-performance gate driver IC integrated in the package helps
minimize the parasitics and results in extremely fast switching of the power MOSFETs. System level
performance curves such as Power Loss, Safe Operating Area, and normalized graphs allow engineers to
predict the product performance in the actual application.
POWER LOSS CURVES
MOSFET centric parameters such as RDS(ON) and Qgd are primarily needed by engineers to estimate the loss
generated by the devices. To simplify the design process for engineers, TI has provided measured power loss
performance curves. Figure 3 plots the power loss of the CSD95373AQ5M as a function of load current. This
curve is measured by configuring and running the CSD95373AQ5M as it would be in the final application. The
measured power loss is the CSD95373AQ5M device power loss, which consists of both input conversion loss
and gate drive loss. Equation 1 is used to generate the power loss curve.
Power Loss = (VIN x IIN) + (VDD x IDD) – (VSW_AVG x IOUT)
(1)
The power loss curve in Figure 3 is measured at the maximum recommended junction temperature of
TJ = 125°C under isothermal test conditions.
SAFE OPERATING CURVES (SOA)
The SOA curves in the CSD95373AQ5M data sheet give engineers guidance on the temperature boundaries
within an operating system by incorporating the thermal resistance and system power loss. Figure 5 and Figure 6
outline the temperature and airflow conditions required for a given load current. The area under the curve
dictates the safe operating area. All the curves are based on measurements made on a PCB design with
dimensions of 4.0" (W) x 3.5" (L) x 0.062" (T) and 6 copper layers of 1 oz. copper thickness.
NORMALIZED CURVES
The normalized curves in the CSD95373AQ5M data sheet give engineers guidance on the Power Loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries adjust for a given set of systems conditions. The primary y-axis is the normalized change in power
loss and the secondary y-axis is the change is system temperature required in order to comply with the SOA
curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is
subtracted from the SOA curve.
CALCULATING POWER LOSS AND SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see the Design Example).
Though the Power Loss and SOA curves in this data sheet are taken for a specific set of test conditions, the
following procedure outlines the steps engineers should take to predict product performance for any set of
system conditions.
Design Example
Operating Conditions: Output Current (lOUT) = 30 A, Input Voltage (VIN ) = 7 V, Output Voltage (VOUT) = 1.5 V,
Switching Frequency (fSW) = 800 kHz, Output Inductor (LOUT) = 0.2 µH
Calculating Power Loss
•
•
•
•
•
•
Typical Power Loss at 30 A = 4.5 W (Figure 3)
Normalized Power Loss for switching frequency ≈ 1.07 (Figure 7)
Normalized Power Loss for input voltage ≈ 1.07 (Figure 8)
Normalized Power Loss for output voltage ≈ 1.06(Figure 9)
Normalized Power Loss for output inductor ≈ 1.02 (Figure 10)
Final calculated Power Loss = 4.5 W × 1.07 × 1.07 × 1.06 × 1.02 ≈ 5.6 W
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Calculating SOA Adjustments
•
•
•
•
•
SOA adjustment for switching frequency ≈ 1.9°C (Figure 7)
SOA adjustment for input voltage ≈ 1.9°C (Figure 8)
SOA adjustment for output voltage ≈ 1.5°C (Figure 9)
SOA adjustment for output inductor ≈ 0.4°C (Figure 10)
Final calculated SOA adjustment = 1.9 + 1.9 + 1.5 + 0.4 ≈ 5.7°C
Figure 19. Power Stage CSD95373AQ5M SOA
In the previous design example, the estimated power loss of the CSD95373AQ5M would increase to 5.6 W. In
addition, the maximum allowable board or ambient temperature, or both, would have to decrease by 5.7°C.
Figure 19 graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust the SOA board or ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 5.7°C. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board or ambient temperature.
14
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CSD95373AQ5M
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SLPS458 – DECEMBER 2013
RECOMMENDED SCHEMATIC OVERVIEW
There are several critical components that must be used in conjunction with this Power Stage device. Figure 20
shows a portion of a schematic with the critical components needed for proper operation.
• C1: Bootstrap capacitor
• R1: Bootstrap resistor
• C4: Bypass capacitor for TAO
• C3: Bypass capacitor for VDD
• C5: Bypass capacitor for VIN to help with ringing reduction
• C6: Bypass capacitor for VIN
5V
R1
0
C1
0.1µF
C3
1µF
PGND
3
FCCM
PWM
10
12
11
TAO
VDD
EN
FCCM
PWM
TAO/FAULT
NC
NC
NC
9
C6
10µF
C7
10µF
C8
10µF
C9
10µF
C10
10µF
C11
10µF
7
6
1
C16
DNP
13
1
2
4
C5
3300pF
PGND
VSW
C4
1000pF
PGND
VIN
PGND
EN
U1
BOOT
5
BOOT_R
8
12V
TP4 TP3 TP2 TP1
1
L1
2
VOUT
2
R2
DNP
C12
100µF
C13
100µF
C14
100µF
C15
100µF
PGND
PGND
Figure 20. Recommended Schematic
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CSD95373AQ5M
SLPS458 – DECEMBER 2013
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RECOMMENDED PCB DESIGN OVERVIEW
There are two key system-level parameters that can be addressed with a proper PCB design: electrical and
thermal performance. Properly optimizing the PCB layout yields maximum performance in both areas. A brief
description on how to address each parameter follows.
ELECTRICAL PERFORMANCE
The CSD95373AQ5M has the ability to switch at voltage rates greater than 10 kV/µs. Special care must be taken
with the PCB layout design and placement of the input capacitors, inductor, and output capacitors.
• The placement of the input capacitors relative to VIN and PGND pins of CSD95373AQ5M device should have
the highest priority during the component placement routine. It is critical to minimize these node lengths. As
such, ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see
Figure 21). The example in Figure 21 uses 1 x 3.3 nF 0402 50 V and 6 x 10 µF 1206 25 V ceramic capacitors
(TDK Part # C3216X7R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the
board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to
the Power Stage C5, C8 and C6, C19 should follow in order.
• The bootstrap cap CBOOT 0.1 µF 0603 16 V ceramic capacitor should be closely connected between BOOT
and BOOT_R pins
• The switching node of the output inductor should be placed relatively close to the Power Stage
CSD95373AQ5M VSW pins. Minimizing the VSW node length between these two components reduces the
PCB conduction losses and actually reduces the switching noise level. (1)
THERMAL PERFORMANCE
The CSD95373AQ5M has the ability to use the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that wicks down the via barrel:
• Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
• Use the smallest drill size allowed in your design. The example in Figure 21 uses vias with a 10 mil drill hole
and a 26 mil capture pad.
• Tent the opposite side of the via with solder-mask.
The number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
Figure 21. Recommended PCB Layout (Top-Down View)
(1)
16
Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
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CSD95373AQ5M
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SLPS458 – DECEMBER 2013
SENSING PERFORMANCE
The integrated temperature sensing technology built in the driver of the CSD95373AQ5M produces an analog
signal that is proportional to the temperature of the lead-frame of the device, which is almost identical to the
junction temperature of the Sync FET. To calculate the junction temperature based on the TAO voltage, use
Equation 2. TAO should be bypassed to PGND with a 1 nF X7R ceramic capacitor for optimal performance. The
TAO pin has limited sinking current capability to enable several power stages that are wire OR-ed together to
report only the highest temperature (or fault condition if present). To ensure accurate temperature reporting, the
TAO nets should be routed on a quiet inner layer between ground planes where possible. In addition, the TAO
bypass capacitor should have a PGND pour on the layer directly beneath to ensure proper decoupling. The TAO
net should always be shielded from VSW and VIN whenever possible.
TJ[C°] = (TAO[mV] - 400[mV]) / 8[mV/°C]
Copyright © 2013, Texas Instruments Incorporated
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CSD95373AQ5M
SLPS458 – DECEMBER 2013
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APPLICATION SCHEMATIC
PWM1
SKIP#-RAMP
BOOT_R
VSP
VSN
VDD
ENABLE
PGND
BOOT
5V
TPS53640
12V
VIN
LOAD
PGND
CSD95373A
PWM
FCCM
TAO/FAULT
VSW
OCP-I
CSP1
CSN1
COMP
VREF
F-IMAX
B-TMAX
BOOT_R
VDD
ENABLE
PGND
BOOT
5V
PWM2
12V
VIN
PGND
CSD95373A
O-USR
5V
CSP2
CSN2
PWM
FCCM
TAO/FAULT
VSW
ADDR
SLEW-MODE
PWM3
TSEN
CSP3
CSN3
BOOT_R
VDD
ENABLE
PGND
BOOT
5V
12V
VIN
PGND
CSD95373A
ISUM
IMON
5V
PWM
FCCM
TAO/FAULT
VSW
PWM4
VR_FAULT#
18
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VDD
ENABLE
PGND
12V
V12
V5
V3R3
12V
VIN
PGND
CSD95373A
5V
PWM
FCCM
TAO/FAULT
VSW
GND
ENABLE
5V
CSP4
CSN4
BOOT_R
{
I2C or
PMBUS
SCLK
ALERT#
SDIO
VR_RDY
VR_HOT#
PMB_CLK
PMB_ALERT#
PMB_DIO
ENABLE
VR_FAULT#
BOOT
{
To/From
CPU
Copyright © 2013, Texas Instruments Incorporated
CSD95373AQ5M
www.ti.com
SLPS458 – DECEMBER 2013
MECHANICAL DATA
Exposed tie clip may vary
c2
A
E1
E2
c1
Ɵ
K
d2
d1
L1
b3
b1
b2
E
D2
b
e
a1
DIM
0.300 x 45°
MILLIMETERS
L
d
INCHES
MIN
NOM
MAX
MIN
NOM
MAX
A
1.400
1.450
1.500
0.055
0.057
0.059
a1
0.000
0.000
0.050
0.000
0.000
0.002
b
0.200
0.250
0.320
0.008
0.010
0.013
b1
b2
2.750 TYP
0.200
b3
0.250
0.108 TYP
0.320
0.008
0.250 TYP
0.010
0.013
0.010 TYP
c1
0.150
0.200
0.250
0.006
0.008
0.010
D2
5.300
5.400
5.500
0.209
0.213
0.217
d
0.200
0.250
0.300
0.008
0.010
0.012
d1
0.350
0.400
0.450
0.014
0.016
0.018
d2
1.900
2.000
2.100
0.075
0.079
0.083
E
5.900
6.000
6.100
0.232
0.236
0.240
E1
4.900
5.000
5.100
0.193
0.197
0.201
E2
3.200
3.300
3.400
0.126
0.130
0.134
e
0.500 TYP
K
0.350 TYP
0.020 TYP
0.014 TYP
L
0.400
0.500
0.600
0.016
0.020
0.024
L1
0.210
0.310
0.410
0.008
0.012
0.016
θ
0.00
—
—
0.00
—
—
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CSD95373AQ5M
SLPS458 – DECEMBER 2013
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Recommended PCB Land Pattern
0.331(0.013)
0.370 (0.015)
0.410 (0.016)
1.000 (0.039)
0.550 (0.022)
0.300 (0.012)
2.800
(0.110)
5.300
(0.209)
6.300
(0.248)
0.500
(0.020)
5.639
(0.222)
0.300
(0.012)
R0.127 (R0.005)
3.400
(0.134)
5.900
(0.232)
Recommended Stencil Opening
0.350(0.014)
2.750
(0.108)
0.250
(0.010)
Notes:
1. Dimensions are shown in mm (inches) format
2. Stencil thickness is 100 µm
20
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Jan-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
CSD95373AQ5M
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SON
DQP
12
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Pb-Free (RoHS
Exempt)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-55 to 150
95373AM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jan-2014
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Dec-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CSD95373AQ5M
Package Package Pins
Type Drawing
SON
DQP
12
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
6.3
1.8
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Dec-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CSD95373AQ5M
SON
DQP
12
2500
367.0
367.0
35.0
Pack Materials-Page 2
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