TI CSD19506KCS

CSD19506KCS
www.ti.com
SLPS481 – DECEMBER 2013
80V N-Channel NexFET™ Power MOSFETs
Check for Samples: CSD19506KCS
FEATURES
1
•
•
•
•
•
•
•
2
Ultra-Low Qg and Qgd
Low Thermal Resistance
Avalanche Rated
Pb-Free Terminal Plating
RoHS Compliant
Halogen Free
TO-220 Plastic Package
PRODUCT SUMMARY
TA = 25°C
TYPICAL VALUE
Drain-to-Source Voltage
80
V
Qg
Gate Charge Total (10 V)
120
nC
Qgd
Gate Charge Gate to Drain
RDS(on)
Drain-to-Source On Resistance
VGS(th)
Threshold Voltage
APPLICATIONS
•
•
UNIT
VDS
20
nC
VGS = 6 V
2.2
mΩ
VGS = 10 V
2.0
mΩ
2.5
V
ORDERING INFORMATION
Secondary Side Synchronous Rectifier
Motor Control
Device
Package
Media
Qty
Ship
CSD19506KCS
TO-220 Plastic
Package
Tube
50
Tube
DESCRIPTION
This 80 V, 2.0 mΩ, TO-220 NexFET™ power
MOSFET is designed to minimize losses in power
conversion applications.
ABSOLUTE MAXIMUM RATINGS
TA = 25°C
VALUE
UNIT
VDS
Drain-to-Source Voltage
80
V
VGS
Gate-to-Source Voltage
±20
V
Continuous Drain Current (Package limited)
100
Continuous Drain Current (Silicon limited),
TC = 25°C
273
Continuous Drain Current (Silicon limited),
TC = 100°C
193
IDM
Pulsed Drain Current (1)
236
A
PD
Power Dissipation
375
W
TJ,
TSTG
Operating Junction and Storage
Temperature Range
–55 to 175
°C
EAS
Avalanche Energy, single pulse
ID = 129 A, L = 0.1 mH, RG = 25 Ω
832
mJ
Pin Out Drawing
Drain (Pin 2)
ID
Gate
(Pin 1)
A
(1) Pulse duration ≤ 300 μs, Duty cycle ≤ 1%
Source (Pin 3)
RDS(on) vs VGS
GATE CHARGE
10
TC = 25°C, I D = 100A
TC = 125°C, I D = 100A
9
VGS - Gate-to-Source Voltage (V)
RDS(on) - On-State Resistance (mΩ)
10
8
7
6
5
4
3
2
1
0
0
2
4
6
8
10
12
14
16
VGS - Gate-to- Source Voltage (V)
18
20
G001
ID = 100A
VDS = 40V
9
8
7
6
5
4
3
2
1
0
0
20
40
60
80
100
Qg - Gate Charge (nC)
120
140
G001
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NexFET is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
CSD19506KCS
SLPS481 – DECEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static Characteristics
BVDSS
Drain-to-Source Voltage
VGS = 0 V, ID = 250 μA
IDSS
Drain-to-Source Leakage Current
VGS = 0 V, VDS = 64 V
IGSS
Gate-to-Source Leakage Current
VDS = 0 V, VGS = 20 V
VGS(th)
Gate-to-Source Threshold Voltage
VDS = VGS, ID = 250 μA
RDS(on)
Drain-to-Source On Resistance
gfs
Transconductance
80
2.1
V
1
μA
100
nA
2.5
3.2
V
2.2
2.8
mΩ
VGS = 10 V, ID = 100 A
2.0
2.3
mΩ
VDS = 8 V, ID = 100 A
297
VGS = 6 V, ID = 100 A
S
Dynamic Characteristics
Ciss
Input Capacitance
9380
12200
pF
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
2260
2940
pF
42
55
RG
pF
Series Gate Resistance
1.3
2.6
Ω
Qg
Gate Charge Total (10 V)
120
156
nC
Qgd
Gate Charge Gate to Drain
Qgs
Gate Charge Gate to Source
Qg(th)
Gate Charge at Vth
Qoss
Output Charge
td(on)
VGS = 0 V, VDS = 40 V, f = 1 MHz
VDS = 40 V, ID = 100 A
20
nC
37
nC
25
nC
345
nC
Turn On Delay Time
19
ns
tr
Rise Time
11
ns
td(off)
Turn Off Delay Time
30
ns
tf
Fall Time
10
ns
VDS = 40 V, VGS = 0 V
VDS = 40 V, VGS = 10 V,
IDS = 100 A, RG = 0 Ω
Diode Characteristics
VSD
Diode Forward Voltage
ISD = 100 A, VGS = 0 V
0.9
Qrr
Reverse Recovery Charge
525
nC
trr
Reverse Recovery Time
VDS= 40 V, IF = 100 A,
di/dt = 300 A/μs
1.1
V
107
ns
THERMAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
MAX
UNIT
RθJC
Thermal Resistance Junction to Case
PARAMETER
0.4
°C/W
RθJA
Thermal Resistance Junction to Ambient
62
°C/W
2
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MIN
TYP
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: CSD19506KCS
CSD19506KCS
www.ti.com
SLPS481 – DECEMBER 2013
TYPICAL MOSFET CHARACTERISTICS
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
TEXT ADDED FOR SPACING
200
180
180
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
TEXT ADDED FOR SPACING
200
160
140
120
100
80
60
VGS =10V
VGS =8V
VGS =6V
40
20
0
0
0.1
0.2
0.3
0.4
VDS - Drain-to-Source Voltage (V)
0.5
VDS = 5V
160
140
120
100
80
60
TC = 125°C
TC = 25°C
TC = −55°C
40
20
0
0
G001
Figure 2. Saturation Characteristics
1
2
3
4
5
6
VGS - Gate-to-Source Voltage (V)
7
Product Folder Links: CSD19506KCS
G001
Figure 3. Transfer Characteristics
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Copyright © 2013, Texas Instruments Incorporated
8
3
CSD19506KCS
SLPS481 – DECEMBER 2013
www.ti.com
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
100000
ID = 100A
VDS = 40V
9
8
10000
C − Capacitance (pF)
VGS - Gate-to-Source Voltage (V)
10
7
6
5
4
3
1000
100
2
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
10
1
0
0
20
40
60
80
100
Qg - Gate Charge (nC)
120
1
140
0
10
20
30
40
50
60
VDS - Drain-to-Source Voltage (V)
G001
Figure 4. Gate Charge
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
2.7
2.5
2.3
2.1
1.9
1.7
1.5
RDS(on) - On-State Resistance (mΩ)
VGS(th) - Threshold Voltage (V)
2.9
1.1
−75 −50 −25
TC = 25°C, I D = 100A
TC = 125°C, I D = 100A
9
8
7
6
5
4
3
2
1
0
0
25 50 75 100 125 150 175 200
TC - Case Temperature (ºC)
G001
Figure 6. Threshold Voltage vs. Temperature
0
2
4
6
8
10
12
14
16
VGS - Gate-to- Source Voltage (V)
18
20
G001
Figure 7. On-State Resistance vs. Gate-to-Source Voltage
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
2.4
100
VGS = 6V
VGS = 10V
ISD − Source-to-Drain Current (A)
Normalized On-State Resistance
G001
10
ID = 250uA
1.3
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
−75 −50 −25
TC = 25°C
TC = 125°C
10
1
0.1
0.01
0.001
ID =60A
0
25 50 75 100 125 150 175 200
TC - Case Temperature (ºC)
G001
Figure 8. Normalized On-State Resistance vs. Temperature
4
80
Figure 5. Capacitance
3.1
2.2
70
0.0001
0
0.2
0.4
0.6
0.8
VSD − Source-to-Drain Voltage (V)
1
G001
Figure 9. Typical Diode Forward Voltage
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Product Folder Links: CSD19506KCS
CSD19506KCS
www.ti.com
SLPS481 – DECEMBER 2013
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1000
1000
10us
100us
1ms
10ms
DC
IAV - Peak Avalanche Current (A)
IDS - Drain-to-Source Current (A)
5000
100
10
1
Single Pulse
Max RthetaJC = 0.4ºC/W
0.1
0.1
1
10
100
VDS - Drain-to-Source Voltage (V)
1000
TC = 25ºC
TC = 125ºC
100
10
0.01
G001
Figure 10. Maximum Safe Operating Area
0.1
TAV - Time in Avalanche (mS)
1
G001
Figure 11. Single Pulse Unclamped Inductive Switching
TEXT ADDED FOR SPACING
IDS - Drain- to- Source Current (A)
120
100
80
60
40
20
0
−50 −25
0
25
50
75 100 125 150 175 200
TC - Case Temperature (ºC)
G001
Figure 12. Maximum Drain Current vs. Temperature
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Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: CSD19506KCS
5
CSD19506KCS
SLPS481 – DECEMBER 2013
www.ti.com
MECHANICAL DATA
KCS Package Dimensions
Table 1. Pin Configuration
Position
6
Designation
Pin 1
Gate
Pin 2 / Tab
Drain
Pin 3
Source
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Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: CSD19506KCS
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
CSD19506KCS
ACTIVE
Package Type Package Pins Package
Drawing
Qty
TO-220
KCS
3
50
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Pb-Free
(RoHS)
CU SN
N / A for Pkg Type
Op Temp (°C)
Device Marking
(4/5)
-55 to 175
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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5-Feb-2014
Addendum-Page 2
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