CSD43301Q5M www.ti.com SLPS380A – DECEMBER 2012 – REVISED DECEMBER 2012 NexFET™ Smart Synchronous Rectifier FEATURES DESCRIPTION • • • • • • • • • The CSD43301Q5M NexFET™ Smart Synchronous Rectifier is a highly optimized design for secondary synchronous rectification in a high power high density DC/DC converter. This product integrates the driver IC and an ultra low Ron Power MOSFET to complete the synchronous rectification function. In addition, the PCB footprint has been optimized to help reduce design time and simplify the completion of the overall system design. 1 2 Typical Ron of 0.55 mΩ at 4.5 VDD Integrated FET Driver Max Rated Current 80A High Density – SON 5-mm × 6-mm Footprint Ultra Low Inductance Package System Optimized PCB Footprint TTL IN signal Compatible Halogen Free RoHS Compliant – Lead Free Terminal Plating Halogen Free APPLICATIONS • Secondary Synchronous Rectification for DC/DC Converters ORDERING INFORMATION Device Package Media CSD43301Q5M SON 5-mm × 6-mm Plastic Package 13-Inch Reel Qty Ship 2500 Tape and Reel spacer . . Figure 1. Application Diagram 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NexFET is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated CSD43301Q5M SLPS380A – DECEMBER 2012 – REVISED DECEMBER 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) TA = 25°C (unless otherwise noted) VALUE DRAIN to PGND DRAIN to PGND (10ns) UNIT MIN MAX -0.3 12 V -7 14 V VDD to PGND –0.3 8 V IN, SD to PGND (2) –0.3 VDD + 0.3 V Human Body Model (HBM) 2000 V Charged Device Model (CDM) 500 V 12 W ESD Rating Power Dissipation (PD) Operating Temperature Range, (TJ) -40 150 °C Storage Temperature Range, (TSTG) –65 150 °C (1) (2) Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability. Must not exceed 8V RECOMMENDED OPERATING CONDITIONS TA = 25° (unless otherwise noted) Parameter Conditions MIN MAX 4.5 6 V Input Supply Voltage (VIN) 9.6 V Continuous Output Current (IOUT) 80 A Peak Output Current, ( IOUT-PK) (1) 120 A 1500 kHz 125 °C Bias Voltage (VDD) Switching Frequency, (fSW) Minimum IN Pulse Width 48 Operating Temperature –40 (1) UNIT ns Peak Output Current is applied for tp = 50µs. THERMAL INFORMATION TA = 25°C (unless otherwise noted) PARAMETER RθJC RθJB (1) 2 Thermal Resistance, Junction-to-Case (Top of package) Thermal Resistance, Junction-to-Board (1) MIN TYP MAX UNIT 20 °C/W 2 °C/W RθJB value based on hottest board temperature within 1mm of the package. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated CSD43301Q5M www.ti.com SLPS380A – DECEMBER 2012 – REVISED DECEMBER 2012 ELECTRICAL CHARACTERISTICS TA = 25°C, VDD = 5V (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT ID = 50A, , TJ = 25°C 0.55 0.70 mΩ ID = 50A, TJ = 125°C 0.70 0.88 mΩ Standby Supply Current ( IDD) SD = VDD = 5V 153 300 µA Operating Supply Current (IDD) SD = 0V, IN = 50% Duty Cycle, fSW = 300kHz 29.5 Device On Resistance Ron VDD mA POWER-ON RESET AND UNDER VOLTAGE LOCKOUT TA = 25°C 3.9 4.2 4.5 V TA = -40°C to 140°C 3.7 4.2 4.65 V UVLO (VDD Falling) 3.45 3.9 4.35 V Hysteresis 200 300 500 mV Power on Reset (VDD Rising) IN IN Logic Level High (VINH) 2.0 V IN Logic Level Low (VINL) 0.8 V IN Input Hysteresis 0.8 V IN to DRAIN Propagation Delay (tPDLH) 32 ns IN to DRAIN Propagation Delay (tPDHL) VDD = 5V, SD = 0, ID = 25A (See Figure 4) 80 Minimum Pulse Width Changes Output 36 ns 48 ns SD SD Logic Level High Threshold (VIH ) 2.0 V SD Logic Level Low Threshold (VIL ) 0.8 V Hysteresis 0.8 V SD to DRAIN Propagation Delay (tPDLH) 80 ns 32 ns SD to DRAIN Propagation Delay (tPDHL) VDD = 5V, IN = VDD, ID = 25A (See Figure 5) Dynamic Characteristics Output Capacitance (CO) Output Charge (QO) VDRAIN = 6V 10 13 54 nF nC Body Diode Forward Voltage (VF) Reverse Recovery Charge (QRR) Reverse Recovery Time Delay (tRR) Copyright © 2012, Texas Instruments Incorporated ID = 40A ID = 40A, VDRAIN = 6V, di/dt = 150A/µs 0.75 0.85 V 161 nC 72 ns Submit Documentation Feedback 3 CSD43301Q5M SLPS380A – DECEMBER 2012 – REVISED DECEMBER 2012 www.ti.com PIN CONFIGURATION Figure 2. Pin Configuration PIN DESCRIPTION PIN NO. DESCRIPTION NAME 1,2,4, 8, 10,11 NC No connect. These should not be used for any electrical connection. These pins should not be connected to each other. Connect to dead copper only. 3 VDD Supply Voltage for IC DRAIN Drain terminal of internal MOSFET 7 PGND Power Ground and source terminal of the internal MOSFET. Needs to be connected to Pin 13 on PCB 5,6 9 SD Shut Down Pin: Logic High disables the Device 12 IN Input for Gate Driver 13 PGND Power Ground and source terminal of the internal MOSFET. Needs to be connected to Pin 7 on PCB Figure 3. Functional Block Diagram 4 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated CSD43301Q5M www.ti.com SLPS380A – DECEMBER 2012 – REVISED DECEMBER 2012 TYPICAL DEVICE CHARACTERISTICS TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING Figure 4. IN Switching Waveforms Figure 5. SD Switching Waveform TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 1.5 Normalized On-State Resistance Co − Output Capacitance (nF) 18 15 12 9 6 3 0 0 2 4 6 8 Drain Voltage (V) Figure 6. Output Capacitance Copyright © 2012, Texas Instruments Incorporated 10 12 G000 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 −50 −25 0 25 50 75 100 Temperature (°C) 125 150 175 G000 Figure 7. Normalized On Resistance Ron Submit Documentation Feedback 5 CSD43301Q5M SLPS380A – DECEMBER 2012 – REVISED DECEMBER 2012 www.ti.com TYPICAL DEVICE CHARACTERISTICS CONTINUED TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 40 TC = 25ºC TC = 125ºC 0.75 VIN = 6V fSW = 300kHz 38 IDD - Supply Current (mA) Ron - On-State Resistance (mΩ) 0.8 0.7 0.65 0.6 0.55 0.5 0.45 36 34 32 30 28 26 24 22 0.4 4.5 4.8 5.1 5.4 VDD - Supply Voltage (V) 5.7 6 20 4.4 4.6 4.8 5 5.2 5.4 5.6 VDD - Supply Voltage (V) G000 Figure 8. On Resistance vs. Supply Voltage 5.8 6 6.2 G000 Figure 9. Supply Current vs. Supply Voltage TEXT ADDED FOR SPACING 160 VDRAIN =0V VDD = 5V IDD - Supply Current (mA) 140 120 100 80 60 40 20 0 200 400 600 800 1000 1200 fSW - Switching Frequency (kHz) 1400 1600 G000 Figure 10. Supply Current vs. Switching Frequency 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated CSD43301Q5M www.ti.com SLPS380A – DECEMBER 2012 – REVISED DECEMBER 2012 Application Information VDD and Under-Voltage Lockout (UVLO) The driver IC in the CSD43301Q5M has an internal UVLO protection feature on the VDD pin. Whenever the driver is in the UVLO condition (i.e. when VDD voltage is less than VON during power up and when VDD voltage is less than VOFF during power down), this circuit holds the gate of the integrated MOSFET LOW, regardless of the status of IN and SD. The UVLO is typically 4.2V with 300-mV typical hysteresis. This hysteresis helps prevent chatter when low VDD supply voltages have noise from the power supply and also when there are droops in the VDD bias voltage when the system commences switching and there is a sudden increase in IDD. This provides the capability to operate at low voltage levels (below 5V), along with best-in-class switching characteristics. For example, at power up, the MOSFET remains OFF until the VDD voltages reaches the UVLO threshold. This prevents operating the MOSFET in the linear region and conducting a large load current at the same time, which often results in device overheating and can potentially damage the device. Since the driver draws current from the VDD pin to bias all internal circuits, for the best high-speed circuit performance, Multi-Layer Ceramic Capacitor (MLCC) bypass capacitors are recommended to prevent noise problems. A 1 µF MLCC type capacitor should be located as close as possible to the VDD to GND pins of the gate driver. Operating Supply Current The driver IC in the CSD43301Q5M has a low quiescent current in normal operation. IDDQ is less than 0.2mA when the device is disabled (SD = 0). The operating current vs. supply voltage is shown in Figure 9, and the operating current vs. frequency is shown in Figure 10. Input Stage The input pins (IN and SD) of the CSD43301Q5M are based on a TTL/CMOS compatible input threshold logic that is independent of the VDD supply voltage. With a typical high threshold of 2.2V and a typical low threshold of 1.2 V, the logic level thresholds can be conveniently driven with PWM control signals derived from 3.3-V or 5-V digital power controllers. Wider hysteresis (typical of 0.8 V) offers enhanced noise immunity compared to traditional TTL logic implementations, where the hysteresis is typically less than 0.5V. These devices also feature tight control of the input pin threshold voltage levels which eases system design considerations and ensures stable operation across temperature. The very low input capacitance on these pins reduces loading and increases switching speed. The device features an important safety function wherein, whenever any of the input pins are in a floating condition, the output of the respective channel is held in the low state. This is achieved using a VDD pull-up resistor on the SD input or a GND pull-down resistor on the IN input. This can be seen in the block diagram in Figure 3. Power Dissipation Power Dissipation of the CSD43301Q5M used in secondary rectification is given by the following: PLOSS = PDRV + PCOND + PSW (1) where driver loss is given by PDRV = VDD × IDD (2) and conduction loss is given by PCOND = I²D_RMS ×RON (3) Switching losses consist of body diode conduction losses during dead time, body diode reverse recovery losses, and output charge losses, given by the following: PSW = ID × VF × (DTR + DTF) × FSW + QRR × VDRAIN × FSW + ½QOSS × VDRAIN × FSW Copyright © 2012, Texas Instruments Incorporated (4) Submit Documentation Feedback 7 CSD43301Q5M SLPS380A – DECEMBER 2012 – REVISED DECEMBER 2012 www.ti.com Recommended PCB Design Overview The CSD43301Q5M features extremely low nominal RON. In order to maximize the performance of this device, some simple layout guidelines should be followed. • The DRAIN pins of the CSD43301Q5M should be placed as close as possible to the inductor and connected with a short wide trace. This reduces PCB conduction losses and reduce switching noise level. (1) • The GND pin (pin 7) must be connected into the thermal pad (pin 13) on the bottom of the device via a copper pour (without thermal spokes) for maximum performance. • The CSD43301Q5M has the ability to use the GND planes as the primary thermal path. As such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of solder attach that will wick down via the barrel: – Intentionally space out the vias from each other to avoid a cluster of holes in a given area. – Use the smallest drill size allowed in your design. The example in Figure 11 uses vias with a 10 mil drill hole and a 16 mil capture pad. – Tent the opposite side of the via with a solder mask. In the end, the number and size of the thermal vias should align with the end user's PCB design rules and manufacturing types. Figure 11. Recommended PCB Layout (Top Down View) (1) 8 Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of Missouri – Rolla Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated CSD43301Q5M www.ti.com SLPS380A – DECEMBER 2012 – REVISED DECEMBER 2012 MECHANICAL DATA DIM MILLIMETERS INCHES Min Nom Max Min Nom Max A 1.400 1.450 1.500 0.055 0.057 0.059 A1 0.000 0.000 0.050 0.000 0.000 0.002 b 0.200 0.250 0.350 0.008 0.010 0.013 b1 2.750 TYP 0.108 TYP b2 3.250 TYP 0.128 TYP c1 0.150 0.200 0.250 0.006 0.008 0.010 D1 5.900 6.000 6.100 0.232 0.236 0.240 D2 4.890 4.990 5.090 0.192 0.196 0.200 E 5.900 6.000 6.100 0.232 0.236 0.240 E1 4.900 5.000 5.100 0.193 0.197 0.201 E2 3.200 3.300 3.400 0.126 0.130 0.134 e 0.500 TYP 0.020 TYP K 0.450 TYP 0.018 TYP K1 0.225 TYP 0.009 TYP L 0.300 0.400 0.500 0.012 0.016 0.020 L1 0.150 0.250 0.350 0.006 0.010 0.014 θ 0.00 — — 0.00 — — Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 9 CSD43301Q5M SLPS380A – DECEMBER 2012 – REVISED DECEMBER 2012 www.ti.com Recommended PCB Pattern NOTE: Dimensions are in mm (inches). Recommended Stencil NOTE: Dimensions are in mm (inches). 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated CSD43301Q5M www.ti.com SLPS380A – DECEMBER 2012 – REVISED DECEMBER 2012 REVISION HISTORY Changes from Original (December 2012) to Revision A • Page Changed Figure 3 ................................................................................................................................................................. 4 Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 11 PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 PACKAGING INFORMATION Orderable Device Status (1) CSD43301Q5M ACTIVE Package Type Package Pins Package Qty Drawing SON DQP 12 2500 Eco Plan Lead/Ball Finish (2) Pb-Free (RoHS Exempt) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) CU NIPDAU Level-2-260C-1 YEAR (4) -55 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device CSD43301Q5M Package Package Pins Type Drawing SON DQP 12 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 6.3 1.8 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD43301Q5M SON DQP 12 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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