SECOS SSD30N10-50D

SSD30N10-50D
26A, 100V, RDS(ON) 50mΩ
N-Ch Enhancement Mode Power MOSFET
Elektronische Bauelemente
RoHS Compliant Product
A suffix of “-C” specifies halogen free
TO-252(D-Pack)
DESCRIPTION
These miniature surface mount MOSFETs utilize a high
cell density trench process to provide low RDS(on) and to
ensure minimal power loss and heat dissipation.
FEATURES




Low RDS(on) provides higher efficiency and extends
battery life
Low thermal impedance copper leadframe TO-252
saves board space
Fast switching speed
High performance trench technology
A
B
C
D
GE
APPLICATION
K
DC-DC converters and power management in portable
and battery-powered products such as computers, printers,
PCMCIA cards, cellular and cordless telephones.
M
Package
MPQ
LeaderSize
TO-252
2.5K
13’ inch
N
O
P
J
REF.
A
B
C
D
E
F
G
H
PACKAGE INFORMATION
HF
Millimeter
Min.
Max.
6.4
6.8
5.20
5.50
2.20
2.40
0.45
0.58
6.8
7.3
2.40
3.0
5.40
6.2
0.8
1.20
Millimeter
Min.
Max.
2.30 REF.
0.70
0.90
0.50
1.1
0.9
1.6
0
0.15
0.43
0.58
REF.
J
K
M
N
O
P

Drain

Gate

Source
ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise specified)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current
1
TC=25℃
2
Continuous Source Current (Diode Conduction)
Power Dissipation
1
1
TC=25℃
Operating Junction and Storage Temperature Range
Symbol
Ratings
Unit
VDS
100
V
VGS
±20
V
ID
20
A
IDM
36
A
IS
30
A
PD
50
W
TJ, TSTG
-55 ~ 175
°C
Thermal Resistance Ratings
Maximum Thermal Resistance Junction-Ambient 1
RθJA
50
°C / W
Maximum Thermal Resistance Junction-Case
RθJC
3.0
°C / W
Notes:
1. Surface Mounted on 1” x 1” FR4 Board.
2. Pulse width limited by maximum junction temperature.
http://www.SeCoSGmbH.com/
04-Mar-2011 Rev. A
Any changes of specification will not be informed individually.
Page 1 of 2
SSD30N10-50D
26A, 100V, RDS(ON) 50mΩ
N-Ch Enhancement Mode Power MOSFET
Elektronische Bauelemente
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Test conditions
Static
Gate-Source Threshold Voltage
Gate-Body Leakage
VGS(th)
1.0
-
-
V
VDS=VGS, ID=250μA
IGSS
-
-
±100
nA
VDS=0, VGS=20V
-
-
1
-
-
25
34
-
-
-
-
50
-
-
59
4.4
-
S
VDS=40V, ID=5.5A
1.1
-
V
IS=9A, VGS=0
Zero Gate Voltage Drain Current
IDSS
On-State Drain Current 1
ID(ON)
Drain-Source On-Resistance 1
RDS(ON)
Forward Transconductance 1
gfs
-
Diode Forward Voltage
VSD
Dynamic
Qg
-
25
-
Gate-Source Charge
Qgs
-
5
-
Gate-Drain Change
Qgd
-
19
-
Turn-on Delay Time
Td(on)
-
9
-
Tr
-
15
-
Td(off)
-
45
-
Tf
-
39
-
Turn-off Delay Time
Fall Time
μA
A
mΩ
VDS=80V, VGS=0,
TJ=55°C
VDS=5V, VGS=10V
VGS=10V, ID=9.2A
VGS=4.5V, ID=6.1A
2
Total Gate Charge
Rise Time
VDS=80V, VGS=0
nC
ID= 9 A
VDS= 25 V
VGS= 10 V
nS
VDD=100V
ID= 9A
RL= 25
VGEN= 10V
Notes:
1. Pulse test: PW ≦ 300 us duty cycle ≦ 2%.
2. Guaranteed by design, not subject to production testing.
http://www.SeCoSGmbH.com/
04-Mar-2011 Rev. A
Any changes of specification will not be informed individually.
Page 2 of 2