TI SN74HSTL162822DGG

SN74HSTL162822
14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
SCES091A – DECEMBER 1996 – REVISED APRIL 1997
D
D
D
D
DGG PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
Inputs Meet JEDEC HSTL Standard
JESD8-6
All Outputs Have Equivalent 25-Ω Series
Resistors
Packaged in Plastic Thin Shrink
Small-Outline Package
1Q2
2Q1
1Q1
GND
D1
D2
D3
VCC
D4
D5
D6
GND
D7
1LE
VCC
VREF
GND
GND
2LE
D8
GND
D9
D10
D11
VCC
D12
D13
D14
GND
1Q14
2Q14
1Q13
description
This 14-bit to 28-bit D-type latch is designed for
3.15-V to 3.45-V VCC operation. HSTL levels are
expected on the inputs. LVTTL levels are driven
on the Q outputs.
All outputs are designed to sink up to 12 mA and
include 25-Ω series resistors to reduce overshoot
and undershoot.
The SN74HSTL162822 is particularly suitable for
driving an address bus to two banks of memory.
Each bank of 14 outputs is controlled with its own
latch-enable (LE) input.
Each of the 14 data (D) inputs is tied to the inputs
of two D-type latches, which provide true data at
the outputs. While LE is low, the outputs (Q) of the
corresponding 14 latches follow the D inputs.
When LE is taken high, the Q outputs are latched
at the levels set up at the D inputs.
The SN74HSTL162822 is characterized for
operation from –40°C to 90°C.
1
64
2
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
11
54
12
53
13
52
14
51
15
50
16
49
17
48
18
47
19
46
20
45
21
44
22
43
23
42
24
41
25
40
26
39
27
38
28
37
29
36
30
35
31
34
32
33
2Q2
1Q3
GND
2Q3
1Q4
VCC
2Q4
1Q5
GND
2Q5
1Q6
VCC
2Q6
1Q7
GND
2Q7
2Q8
GND
1Q8
2Q9
VCC
1Q9
2Q10
GND
1Q10
2Q11
VCC
1Q11
2Q12
GND
1Q12
2Q13
FUNCTION TABLE
INPUTS
LE
D
OUTPUT
Q
L
H
H
L
L
H
X
L
Q0†
† Output level before the
indicated steady-state input
conditions were established
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74HSTL162822
14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
SCES091A – DECEMBER 1996 – REVISED APRIL 1997
logic diagram (positive logic)
14
1LE
5
D1
1D
3
1Q1
C1
19
1D
2LE
2
2Q1
C1
To 13 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 4)
MIN
MAX
UNIT
3.45
V
0.9
V
1.5
V
VCC
VREF
Supply voltage
3.15
Reference voltage
0.68
VI
VIH
Input voltage
High-level input voltage
All pins
VIL
IOH
Low-level input voltage
All pins
High-level output current
VREF–100 mV
–12
IOL
TA
Low-level output current
12
0
Operating free-air temperature
–40
POST OFFICE BOX 655303
0.75
VREF+100 mV
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
2
NOM
• DALLAS, TEXAS 75265
V
90
V
mA
°C
SN74HSTL162822
14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
SCES091A – DECEMBER 1996 – REVISED APRIL 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VOH
VCC = 3.15 V,
VCC = 3.15 V,
II = –18 mA
IOH = –12 mA
VOL
VCC = 3.15 V,
IOL = 12 mA
VI = 0 or 1.5 V
Control inputs
II
Data inputs
VCC = 3.45 V
Ci
Control inputs
Data inputs
TYP†
UNIT
–1.2
V
V
0.8
V
5
5
µA
90
VCC = 3.45 V,
VCC = 0 or 3.3 V,
VI = 0 or 1.5 V
VI = 0 or 3.3 V
50
VCC = 0 or 3.3 V,
VCC = 0,
VI = 0 or 3.3 V
VO = 0
2
Co
Outputs
† All typical values are at VCC = 3.3 V, TA = 25°C.
MAX
2.2
VI = 0 or 1.5 V
VREF = 0.68 V or 0.9 V
VREF
ICC
MIN
100
2
mA
pF
4
pF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 3.3 V
± 0.15 V
MIN
UNIT
MAX
tw
tsu
Pulse duration, LE low
3
ns
Setup time, D before LE↑
2
ns
th
Hold time, D after LE↑
1
ns
switching characteristics over recommended operating free-air temperature range, VREF = 0.75 V
PARAMETER
tpd
d
FROM
(INPUT)
TO
(OUTPUT)
D
Q
LE
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC = 3.3 V
± 0.15 V
MIN
UNIT
MAX
1.6
5
1.7
5.7
ns
3
SN74HSTL162822
14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH
SCES091A – DECEMBER 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
1.25 V
VREF
LE
From Output
Under Test
0.25 V
CL = 80 pF
(see Note A)
tsu
500 Ω
th
1.25 V
Data Input
VREF
VREF
0.25 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
(see Note B)
1.25 V
VREF
VREF
0.25 V
tPLH
tw
tPHL
1.25 V
Input
VREF
VREF
VOH
Output
1.5 V
0.25 V
VOL
VOLTAGE WAVEFORMS
PULSE DURATION
NOTES: A.
B.
C.
D.
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 1 ns, tf ≤ 1 ns.
The outputs are measured one at a time with one transition per measurement.
tPHL and tPLH are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
4
1.5 V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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