Si52142 PCI-E XPRESS G EN 1, G EN 2 & G EN 3 C L O C K TW O O UTPUT G ENERAT OR WITH 25 MH Z R EFERENCE C L O C K Features Wireless access point Routers Description The Si52142 is a spread-controlled PCIe clock generator that can source two PCIe clocks and a 25 MHz reference clock. The device has three hardware output enable control inputs for enabling the respective outputs on the fly while powered on along with the hardware input for spread spectrum and frequency control on outputs. In addition to the hardware control pins, I2C programmability is also available to promptly achieve optimum clock signal integrity through skew and edge rate control on true, compliment, or both differential outputs as well as amplitude control. 24 23 SCLK SDATA Network attached storage Multi-function printer 22 21 20 19 VDD_REF 1 1 18 OE_DIFF1 17 VDD_DIFF REF 2 OE_REF1 3 VSS_REF 4 1 5 VDD_DIFF 6 OE_DIFF0 16 DIFF1 25 GND 15 DIFF1 14 DIFF0 13 DIFF0 7 8 9 10 Notes: 1. Internal 100 kohm pull-up. 2. Internal 100 kohm pull-down. 11 12 NC VDD_DIFF XOUT Pin Assignments Applications VDD_CORE Ordering Information: See page 18 NC XIN/CLKIN NC I2C support with readback capabilities Triangular spread spectrum profile for maximum electromagnetic interference (EMI) reduction Industrial temperature –40 to 85 oC 3.3 V power supply 24-pin QFN package VSS_CORE 25 MHz crystal input or clock input SS12 PCI-Express Gen 1, Gen 2 & Gen 3 compliant Low power push-pull type differential output buffers Integrated resistors on differential clocks Dedicated output enable hardware pin for each clock Hardware selectable spread control Two PCI-Express clocks 25 MHz reference clock SS02 Patents pending Functional Block Diagram REF XIN/CLKIN XOUT DIFF0 PLL1 (SSC) Divider DIFF1 SCLK SDATA Control & Memory OE_REF OE [1:0] Control RAM SS [1:0] Preliminary 0.1 12/11 Copyright © 2011 by Silicon Laboratories Si52142 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si52142 2 Preliminary 0.1 Si52142 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1. Crystal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2. OE Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.3. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.4. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.5. SS[1:0] Clarification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.1. Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5. Pin Descriptions: 24-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Preliminary 0.1 3 Si52142 1. Electrical Specifications Table 1. DC Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit 3.3 V Operating Voltage VDD core 3.3 ± 5% 3.135 3.3 3.465 V 3.3 V Input High Voltage VIH Control input pins 2.0 — VDD + 0.3 V 3.3 V Input Low Voltage VIL Control input pins VSS – 0.3 — 0.8 V Input High Voltage VIHI2C SDATA, SCLK 2.2 — — V Input Low Voltage VILI2C SDATA, SCLK — — 1.0 V Input High Leakage Current IIH Except internal pull-down resistors, 0 < VIN < VDD — — 5 A Input Low Leakage Current IIL Except internal pull-up resistors, 0 < VIN < VDD –5 — — A 3.3 V Output High Voltage (SE) VOH IOH = –1 mA 2.4 — — V 3.3 V Output Low Voltage (SE) VOL IOL = 1 mA — — 0.4 V High-impedance Output Current IOZ –10 — 10 µA Input Pin Capacitance CIN 1.5 — 5 pF — 6 pF — — 7 nH — — 40 mA Output Pin Capacitance Pin Inductance Dynamic Supply Current 4 COUT LIN IDD_3.3V All outputs enabled. Differential clocks with 5” traces and 2 pF load. Preliminary 0.1 Si52142 Table 2. AC Electrical Specifications Parameter Symbol Condition Min Typ Max Unit LACC Measured at VDD/2 differential — — 250 ppm TDC Measured at VDD/2 47 — 53 % CLKIN Rise and Fall Times TR/TF Measured between 0.2 VDD and 0.8 VDD 0.5 — 4.0 V/ns CLKIN Cycle to Cycle Jitter TCCJ Measured at VDD/2 — — 250 ps CLKIN Long Term Jitter TLTJ Measured at VDD/2 — — 350 ps Input High Voltage VIH XIN/CLKIN pin 2 — VDD+0.3 V Input Low Voltage VIL XIN/CLKIN pin — — 0.8 V Input High Current IIH XIN/CLKIN pin, VIN = VDD — — 35 µA Input Low Current IIL XIN/CLKIN pin, 0 < VIN <0.8 –35 — — µA TDC Measured at 0 V differential 45 — 55 % TSKEW(win Measured at 0 V differential — — 50 ps TCCJ Measured at 0 V differential — 35 50 ps Output PCIe Gen1 REFCLK Phase Jitter RMSGEN1 Includes PLL BW 1.5–22 MHz, ζ = 0.54, Td=10 ns, Ftrk=1.5 MHz with BER = 1E-12 0 40 108 ps Output PCIe Gen2 REFCLK Phase Jitter RMSGEN2 Includes PLL BW 8–16 MHz, Jitter Peaking = 3 dB, ζ = 0.54, Td=12 ns, Low Band, F < 1.5 MHz 0 2 3.0 ps Output PCIe Gen2 REFCLK Phase Jitter RMSGEN2 Includes PLL BW 8–16 MHz, Jitter Peaking = 3 dB, ζ = 0.54, Td=12 ns, High Band, 1.5 MHz < F < Nyquist 0 2 3.1 ps Output Phase Jitter Impact— PCIe Gen3 RMSGEN3 Includes PLL BW 2 – 4 MHz, CDR = 10 MHz) 0 0.5 1.0 ps LACC Measured at 0 V differential — — 100 ppm DIFF Rising/Falling Slew Rate TR / TF Measured differentially from ±150 mV 1 — 8 V/ns Voltage High VHIGH — — 1.15 V Voltage Low VLOW –0.3 — — V VOX 300 — 550 mV Crystal Long-term Accuracy Clock Input CLKIN Duty Cycle DIFF at 0.7 V DIFF Duty Cycle Any DIFF Clock Skew from the earliest bank to the latest bank DIFF Cycle to Cycle Jitter DIFF Long Term Accuracy Crossing Point Voltage at 0.7 V Swing dow) Preliminary 0.1 5 Si52142 Table 2. AC Electrical Specifications (Continued) Parameter Symbol Condition Min Typ Max Unit TDC Measurement at 1.5 V 45 — 55 % TR / TF Measured between 0.8 and 2.0 V 1.0 — 4.0 V/ns Cycle to Cycle Jitter TCCJ Measurement at 1.5 V — — 300 ps Long Term Accuracy LACC Measured at 1.5 V — — 100 ppm REF(25 MHz) at 3.3 V Duty Cycle Rising and Falling Edge Rate Enable/Disable and Set-Up Clock Stabilization from Power-up TSTABLE — — 1.8 ms Stopclock Set-up Time TSS 10.0 — — ns Table 3. Absolute Maximum Conditions Parameter Symbol Condition Min Typ Max Unit VDD_3.3V Functional — — 4.6 V Input Voltage VIN Relative to VSS –0.5 — 4.6 VDC Temperature, Storage TS Non-functional –65 — 150 °C Temperature, Operating Ambient TA Functional –40 — 85 °C Temperature, Junction TJ Functional — — 150 °C Dissipation, Junction to Case ØJC JEDEC (JESD 51) — — 35 °C/W Dissipation, Junction to Ambient ØJA JEDEC (JESD 51) — — 37 °C/W ESDHBM JEDEC (JESD 22-A114) 2000 — — V UL-94 UL (Class) V–0 MSL JEDEC (J-STD-020) 2 Main Supply Voltage ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required. 6 Preliminary 0.1 Si52142 2. Functional Description 2.1. Crystal Recommendations The clock device requires a parallel resonance crystal. Substituting a series resonance crystal causes the clock device to operate at the wrong frequency and violates the ppm specification. For most applications there is a 300 ppm frequency shift between series and parallel crystals due to incorrect loading. Table 4. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap 25 MHz AT Parallel 12–15 pF Shunt Cap (max) Motional (max) Tolerance (max) Stability (max) Aging (max) 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm 2.1.1. Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, use the total capacitance the crystal sees to calculate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using the two trim capacitors. It is important that the trim capacitors are in series with the crystal. It is not true that load capacitors are in parallel with the crystal and are approximately equal to the load capacitance of the crystal. Figure 1. Crystal Capacitive Clarification 2.1.2. Calculating Load Capacitors In addition to the standard external trim capacitors, consider the trace capacitance and pin capacitance to calculate the crystal loading correctly. Again, the capacitance on each side is in series with the crystal. The total capacitance on both side is twice the specified crystal load capacitance (CL). Trim capacitors are calculated to provide equal capacitive loading on both sides. Figure 2. Crystal Loading Example Preliminary 0.1 7 Si52142 Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 x CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) CL: Crystal load capacitance Actual loading seen by crystal using standard value trim capacitors Ce: External trim capacitors Cs: Stray capacitance (terraced) Ci : Internal capacitance (lead frame, bond wires, etc.) CLe: 2.2. OE Clarification The OE pins are active high inputs used to enable and disable the output clocks. To enable the output clock, the OE pin needs to be logic high and the I2C output enable bit needs to be logic high. There are two methods to disable the output clocks: the OE is pulled to a logic low, or the I2C enable bit is set to a logic low. The OE pins is required to be driven at all time and even though it has an internally 100 k resistor. 2.3. OE Assertion The OE signals are active high input used for synchronous stopping and starting the output clocks respectively while the rest of the clock generator continues to function. The assertion of the OE signal by making it logic high causes stopped respective output clocks to resume normal operation. No short or stretched clock pulses are produced when the clock resumes. The maximum latency from the assertion to active outputs is no more than two to six output clock cycles. 2.4. OE Deassertion When the OE pin is deasserted by making its logic low, the corresponding output clocks are stopped cleanly, and the final output state is driven low. 2.5. SS[1:0] Clarification SS[1:0] are active inputs used to select differential output frequency and enable spread of –0.5% on all DIFF outputs as per Table 5. Table 5. SS0 and SS1 Frequency/Spread Selection 8 SS1 SS0 Differential Frequency Differential Spread Configuration 0 0 100 MHz Spread Off Default 0 1 100 MHz –0.50% 1 0 125 MHz Spread Off 1 1 200 MHz Spread Off Preliminary 0.1 Si52142 3. Test and Measurement Setup This diagram shows the test load configuration for the differential clock signals. M e a s u re m e n t P o in t L1 O UT+ 50 2 pF L1 = 5" O UT- M e a s u re m e n t P o in t L1 50 2 pF Figure 3. 0.7 V Differential Load Configuration Figure 4. Differential Measurement for Differential Output Signals (for AC Parameters Measurement) Preliminary 0.1 9 Si52142 VMIN = –0.30V VMIN = –0.30V Figure 5. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement) L1 = 0.5", L2 = 5" SE Clocks L1 33 Measurement 50 L2 Point 4 pF Figure 6. Single-ended Clocks with Single Load Configuration Figure 7. Single-ended Output Signal (for AC Parameter Measurement) 10 Preliminary 0.1 Si52142 4. Control Registers 4.1. Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers are individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting at power-up. The use of this interface is optional. Clock device register changes are normally made at system initialization, if any are required. The interface cannot be used during system operation for power management functions. 4.2. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, access the bytes in sequential order from lowest to highest (most significant bit first) with the ability to stop after any complete byte is transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code described in Table 1 on page 4. The block write and block read protocol is outlined in Table 6 while Table 7 outlines byte write and byte read protocol. The slave receiver address is 11010110 (D6h). Table 6. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 Description Start Slave address—7 bits Block Read Protocol Bit 1 8:2 Description Start Slave address—7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code—8 bits 18:11 Command Code—8 bits 19 Acknowledge from slave 19 Acknowledge from slave Byte Count—8 bits 20 Repeat start 27:20 28 36:29 37 45:38 Acknowledge from slave 27:21 Slave address—7 bits Data byte 1—8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 2—8 bits 46 Acknowledge from slave .... Data Byte /Slave Acknowledges .... Data Byte N—8 bits .... Acknowledge from slave .... Stop 37:30 38 46:39 47 55:48 Byte Count from slave—8 bits Acknowledge Data byte 1 from slave—8 bits Acknowledge Data byte 2 from slave—8 bits 56 Acknowledge .... Data bytes from slave/Acknowledge .... Data Byte N from slave–8 bits .... NOT Acknowledge .... Stop Preliminary 0.1 11 Si52142 Table 7. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 Description Start Slave address–7 bits Byte Read Protocol Bit 1 8:2 Start Slave address–7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 19 27:20 Command Code–8 bits 18:11 Command Code–8 bits Acknowledge from slave 19 Acknowledge from slave Data byte–8 bits 20 Repeated start 28 Acknowledge from slave 29 Stop 27:21 Slave address–7 bits 28 Read 29 Acknowledge from slave 37:30 12 Description Data from slave–8 bits 38 NOT Acknowledge 39 Stop Preliminary 0.1 Si52142 Control Register 0. Byte 0 Bit D7 D6 D5 D4 D3 D1 D0 R/W R/W R/W REF_OE Name Type D2 R/W R/W R/W R/W R/W Reset settings = 00000100 Bit Name Function 7:3 Reserved 2 REF_OE Output Enable for REF. 0: Output disabled. 1: Output enabled. 1:0 Reserved Control Register 1. Byte 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W Name Type Reset settings = 00000000 Bit Name 7:0 Reserved Function Preliminary 0.1 13 Si52142 Control Register 2. Byte 2 Bit D7 D6 Name DIFF0_OE DIFF1_OE Type R/W R/W D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W D2 D1 D0 Reset settings = 11000000 Bit Name 7 DIFF0_OE Function Output Enable for DIFF0. 0: Output disabled. 1: Output enabled. 6 DIFF1_OE Output Enable for DIFF1. 0: Output disabled. 1: Output enabled. 5:0 Reserved Control Register 3. Byte 3 Bit D7 D6 D4 D3 Rev Code[3:0] Name Type D5 R/W R/W R/W Vendor ID[3:0] R/W R/W R/W R/W R/W D3 D2 D1 D0 R/W R/W R/W R/W Reset settings = 00001000 Bit Name Function 7:4 Rev Code[3:0] Program Revision Code. 3:0 Vendor ID[3:0] Vendor Identification Code. Control Register 4. Byte 4 Bit D7 D6 D5 D4 BC[7:0] Name Type R/W R/W R/W R/W Reset settings = 00000110 14 Bit Name 7:0 BC[7:0] Function Byte Count Register. Preliminary 0.1 Si52142 Control Register 5. Byte 5 Bit D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W Name DIFF_Amp_Sel DIFF_Amp_Cntl[2] DIFF_Amp_Cntl[1] DIFF_Amp_Cntl[0] Type R/W R/W R/W R/W Reset settings = 11011000 Bit Name 7 DIFF_Amp_Sel Function Amplitude Control for DIFF Differential Outputs. 0: Differential outputs with Default amplitude. 1: Differential outputs amplitude is set by Byte 5[6:4]. 6 DIFF_Amp_Cntl[2] 5 DIFF_Amp_Cntl[1] 4 DIFF_Amp_Cntl[0] 3:0 Reserved DIFF Differential Outputs Amplitude Adjustment. 000: 300 mV 001: 400 mV 010: 500 mV 100: 700 mV 101: 800 mV 110: 900 mV Preliminary 0.1 011: 600 mV 111: 1000 mV 15 Si52142 VSS_CORE XIN/CLKIN XOUT VDD_CORE SDATA SCLK 5. Pin Descriptions: 24-Pin QFN 24 23 22 21 20 19 VDD_REF 1 1 18 OE_DIFF1 REF 2 17 VDD_DIFF OE_REF1 3 VSS_REF 4 OE_DIFF01 5 VDD_DIFF 6 16 DIFF1 25 GND 15 DIFF1 14 DIFF0 7 8 9 10 11 12 SS02 SS12 NC NC NC VDD_DIFF 13 DIFF0 Notes: 1. Internal 100 kohm pull-up. 2. Internal 100 kohm pull-down. Table 8. Si52142 24-Pin QFN Descriptions Pin # Name 1 VDD_REF 2 REF 3 OE_REF I,PU 3.3 V input to disable REF Clock (internal 100 k pull-up). Refer to Table 1 on page 4 for OE specifications. 4 VSS_REF GND Ground 5 OE_DIFF0 I,PU 3.3 V input to disable DIFF0 (internal 100 k pull-up). Refer to Table 1 on page 4 for OE specifications. 6 VDD_DIFF PWR 3.3 V Power Supply 7 SS0 I, PD 8 SS1 I, PD 9 NC NC No Connect 10 NC NC No Connect 16 Type Description PWR 3.3 V Power Supply O, SE 3.3 V, 25 MHz crystal reference clock 3.3 V tolerant latch-input for enabling Frequency/ Spread selection on DIFF0 and DIFF1 outputs. Refer to Table 1 on page 4 for SS[1:0] specifications. Preliminary 0.1 Si52142 Table 8. Si52142 24-Pin QFN Descriptions (Continued) Pin # Name Type Description 11 NC NC 12 VDD_DIFF 13 DIFF0 O, DIF 0.7 V, 100 MHz differential clock 14 DIFF0 O, DIF 0.7 V, 100 MHz differential clock 15 DIFF1 O, DIF 0.7 V, 100 MHz differential clock 16 DIFF1 O, DIF 0.7 V, 100 MHz differential clock 17 VDD_DIFF PWR 3.3 V power supply 18 OE_DIFF1 I,PU 19 SCLK I 20 SDATA I/O 21 VDD_CORE 22 XOUT O 25.00 MHz Crystal output, Float XOUT if using only CLKIN (Clock input) 23 XIN/CLKIN I 25.00 MHz Crystal input or 3.3 V, 25 MHz Clock Input 24 VSS_CORE GND Ground 25 GND GND Ground for bottom pad of the IC No Connect PWR 3.3 V power supply 3.3 V input to disable DIFF1 (internal 100 k pull-up). Refer to Table 1 on page 4 for OE specifications. SMBus compatible SCLOCK SMBus compatible SDATA PWR 3.3 V power supply Preliminary 0.1 17 Si52142 6. Ordering Guide Part Number Package Type Temperature Si52142-A01AGM 24-pin QFN Industrial, –40 to 85 C Si52142-A01AGMR 24-pin QFN—Tape and Reel Industrial, –40 to 85 C Lead-free 18 Preliminary 0.1 Si52142 7. Package Outline Figure 8 illustrates the package details for the Si52142. Table 9 lists the values for the dimensions shown in the illustration. Figure 8. 24-Pin Quad Flat No Lead (QFN) Package Table 9. Package Diagram Dimensions Symbol Millimeters Min Nom Max A 0.70 0.75 0.80 A1 0.00 0.025 0.05 b 0.20 0.25 0.30 D D2 4.00 BSC 2.60 e 2.70 2.80 0.50 BSC E 4.00 BSC E2 2.60 2.70 2.80 L 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.07 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VGGD-8. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Preliminary 0.1 19 Si52142 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 20 Preliminary 0.1