TI TPS7A8101DRBR

TPS7A8101
www.ti.com
SBVS179A – DECEMBER 2011 – REVISED APRIL 2012
Low-Noise, Wide-Bandwidth, High PSRR,
Low-Dropout 1-A Linear Regulator
FEATURES
DESCRIPTION
•
•
•
The TPS7A8101 low-dropout linear regulator (LDO)
offers very good performance in noise and powersupply rejection ratio (PSRR) at the output. This LDO
uses an advanced BiCMOS process and a
PMOSFET pass device to achieve very low noise,
excellent transient response, and excellent PSRR
performance.
1
2
•
•
•
•
•
•
•
Low-Dropout 1-A Regulator with Enable
Adjustable Output Voltage: 0.8 V to 6.0 V
Wide-Bandwidth High PSRR:
– 80 dB at 1 kHz
– 60 dB at 100 kHz
– 54 dB at 1 MHz
Low Noise: 23.5 μVRMS typical (100 Hz to
100 kHz)
Stable with a 4.7-μF Capacitance
Excellent Load/Line Transient Response
3% Overall Accuracy (over
Load/Line/Temperature)
Over-Current and Over-Temperature
Protection
Very Low Dropout: 170 mV Typical at 1 A
Package: 3-mm × 3-mm SON-8
The TPS7A8101 is stable with a 4.7-μF ceramic
output capacitor, and uses a precision voltage
reference and feedback loop to achieve a worst-case
accuracy of 3% over all load, line, process, and
temperature variations.
This device is fully specified over the temperature
range of TJ = –40°C to +125°C and is offered in a 3mm × 3-mm, SON-8 package with a thermal pad.
Typical Application Circuit
VIN
IN
CIN
APPLICATIONS
•
•
•
R1
TPS7A8101
EN
GND
Telecom Infrastructure
Audio
High-Speed I/F (PLL/VCO)
VOUT
OUT
FB
NR
CNR
CBYPASS
R2
COUT
VEN
DRB PACKAGE
3mm x 3mm SON
(TOP VIEW)
TYPICAL POWER-SUPPLY RIPPLE REJECTION
100
1
8
IN
OUT
2
7
IN
FB/SNS
3
6
NR
GND
4
5
EN
90
80
PSRR (dB)
OUT
70
60
50
40
IOUT= 10 mA
IOUT= 100 mA
IOUT= 750 mA
IOUT= 1 A
30
20
10
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
G103
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
TPS7A8101
SBVS179A – DECEMBER 2011 – REVISED APRIL 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PRODUCT
TPS7A8101yyyz
(1)
VOUT
YYY is package designator.
Z is package quantity.
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted). (1)
VALUE
Voltage
Current
Temperature
Electrostatic discharge (ESD) rating (3)
(1)
(2)
(3)
2
MIN
MAX
UNIT
IN
–0.3
+7.0
V
FB, NR
–0.3
+3.6
V
EN
–0.3
(2)
V
OUT
–0.3
+7.0
V
OUT
VIN + 0.3
Internally Limited
A
Operating virtual junction, TJ
–55
+150
°C
Storage, Tstg
–55
+150
°C
2
kV
500
V
Human body model (HBM)
QSS 009-105 (JESD22-A114A)
Charged device model (CDM)
QSS 009-147 (JESD22-C101B.01)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum-rated conditions for extended periods my affect device reliability.
VEN absolute maximum rating is VIN + 0.3 V or +7.0 V, whichever is smaller.
ESD testing is performed according to the respective JESD22 JEDEC standard.
Copyright © 2011–2012, Texas Instruments Incorporated
TPS7A8101
www.ti.com
SBVS179A – DECEMBER 2011 – REVISED APRIL 2012
THERMAL INFORMATION
TPS7A8101
THERMAL METRIC (1) (2)
DRB (3)
UNITS
8 PINS
Junction-to-ambient thermal resistance (4)
θJA
(5)
45.7
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (6)
21.3
ψJT
Junction-to-top characterization parameter (7)
0.9
ψJB
Junction-to-board characterization parameter (8)
21.4
θJCbot
Junction-to-case (bottom) thermal resistance (9)
5.2
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
53.2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
Thermal data for the DRB package are derived by thermal simulations based on JEDEC-standard methodology as specified in the
JESD51 series. The following assumptions are used in the simulations:
(a) The exposed pad is connected to the PCB ground layer through a 2×2 thermal via array.
(b) The top and bottom copper layers are assumed to have a 5% thermal conductivity of copper representing a 20% copper coverage.
(c) This data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, refer to the Power Dissipation and Estimating Junction
Temperature sections.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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TPS7A8101
SBVS179A – DECEMBER 2011 – REVISED APRIL 2012
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ELECTRICAL CHARACTERISTICS
Over the operating temperature range of TJ = –40°C to +125°C, VIN = VOUT(TYP) + 0.5 V or 2.2 V (whichever is greater),
IOUT = 1 mA, VEN = 2.2 V, COUT = 4.7 μF, CNR = 0.01 μF, and CBYPASS = 0 μF, unless otherwise noted. TPS7A8101 is tested at
VOUT = 0.8 V and VOUT = 6.0 V. Typical values are at TJ = +25°C.
TPS7A8101
PARAMETER
VIN
Input voltage range (1)
VNR
Internal reference
TEST CONDITIONS
Output accuracy (2)
V
V
0.8
6.0
V
VOUT + 0.5 V ≤ VIN ≤ 6.0 V, VIN ≥ 2.5 V,
100 mA ≤ IOUT ≤ 500 mA, 0°C ≤ TJ ≤ 85°C
-2.0
+2.0
%
VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.2 V,
100 mA ≤ IOUT ≤ 1 A
–3.0
+3.0
%
VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.2 V,
IOUT = 100 mA
ΔVO(ΔIL)
Load regulation
100 mA ≤ IOUT ≤ 1 A
ILIM
Output current limit
IGND
Ground pin current
VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.5 V,
IOUT = 750 mA, VFB = GND or VSNS = GND
350
mV
VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.5 V,
IOUT = 1 A, VFB = GND or VSNS = GND
500
mV
1400
2000
mA
60
100
μA
350
μA
VOUT = 0.85 × VOUT(NOM), VIN ≥ 3.3 V
IOUT = 1 A
VIN = 6.5 V, VFB = 0.8 V
VIN = 4.3 V, VOUT = 3.3 V,
IOUT = 750 mA
1.0
μA
dB
dB
f = 10 kHz
78
dB
f = 100 kHz
60
dB
f = 1 MHz
54
dB
BW = 100 Hz to 100 kHz,
VIN = 3.8 V, VOUT = 3.3 V,
IOUT = 100 mA, CNR = CBYPASS = 470 nF
VEN(LO)
Enable low (shutdown)
RL = 1 kΩ
IEN(HI)
Enable pin current, enabled
VIN = VEN = 6.5 V
tSTR
Startup time
VOUT(NOM) = 3.3 V, VOUT = 0% to 90% VOUT(NOM),
RL = 3.3 kΩ, COUT = 10 μF, CNR = 470 nF
Undervoltage lockout
VIN rising, RL = 1 kΩ
Hysteresis
VIN falling, RL = 1 kΩ
4
0.02
82
Enable high (enabled)
(3)
μA
f = 1 kHz
VEN(HI)
(1)
(2)
2
80
Output noise voltage
Operating junction temperature
0.20
f = 100 Hz
Vn
TJ
1100
IOUT = 1 mA
Feedback pin current
Thermal shutdown temperature
μV/mA
mV
IFB
TSD
μV/V
150
250
Shutdown current (IGND)
UVLO
±0.3
2
ISHDN
Power-supply rejection ratio
0.800
VOUT + 0.5 V ≤ VIN ≤ 6.5 V, VIN ≥ 2.2 V,
IOUT = 500 mA, VFB = GND or VSNS = GND
VEN ≤ 0.4 V, VIN ≥ 2.2 V, RL = 1 kΩ,
0°C ≤ TJ ≤ 85°C
PSRR
UNIT
0.810
0.790
Line regulation
Dropout voltage (3)
MAX
6.5
ΔVO(ΔVI)
VDO
TYP
2.2
Output voltage range
VOUT
MIN
μVRMS
23.5
2.2 V ≤ VIN ≤ 3.6 V, RL = 1 kΩ
1.2
3.6 V < VIN ≤ 6.5 V, RL = 1 kΩ
1.35
V
V
0
0.02
0.4
V
1.0
μA
80
1.86
2
ms
2.10
V
75
mV
Shutdown, temperature increasing
+160
°C
Reset, temperature decreasing
+140
–40
°C
+125
°C
Minimum VIN = VOUT + VDO or 2.2 V, whichever is greater.
The TPS7A8101 does not include external resistor tolerances and it is not tested at this condition: VOUT = 0.8 V, 4.5V ≤ VIN ≤ 6.5 V, and
750 mA ≤ IOUT ≤ 1 A because the power dissipation is greater than the maximum rating of the package.
VDO is not measured for fixed output voltage devices with VOUT < 1.7 V because minimum VIN = 2.2 V.
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TPS7A8101
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SBVS179A – DECEMBER 2011 – REVISED APRIL 2012
FUNCTIONAL BLOCK DIAGRAM
OUT
IN
Current
Limit
EN
Thermal
Shutdown
UVLO
1.20 V
Bandgap
FB
33 kW
Quick-Start
NR
33 kW
225 kW
0.8 V
15 pF
Adjustable
58.7 kW
TPS7A8101
GND
Figure 1. Functional Block Diagram
PIN CONFIGURATION
DRB PACKAGE
3mm x 3mm SON-8
(TOP VIEW)
OUT
1
8
IN
OUT
2
7
IN
FB/SNS
3
6
NR
GND
4
5
EN
PIN DESCRIPTIONS
PIN
NAME
EN
NO.
DESCRIPTION
5
Driving this pin high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. Refer
to the Shutdown section for more details. EN must not be left floating and can be connected to IN if not
used.
This pin is the input to the control-loop error amplifier and is used to set the output voltage of the device.
FB
3
GND
4, pad
IN
7, 8
NR
6
OUT
1, 2
Ground
Unregulated input supply
Connect an external capacitor between this pin and ground to reduce output noise to very low levels. The
capacitor also slows down the VOUT ramp (RC softstart).
Regulator output. A 4.7-μF or larger capacitor of any type is required for stability.
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TYPICAL CHARACTERISTICS: TPS7A8101
At VOUT(TYP) = 3.3 V, VIN = VOUT(TYP) + 0.5 V or 2.2 V (whichever is greater), IOUT = 100 mA, VEN = VIN, CIN = 1 μF, COUT = 4.7 μF, and
CNR = 0.01 μF; all temperature values refer to TJ, unless otherwise noted.
LOAD REGULATION
LOAD REGULATION UNDER LIGHT LOADS
3.399
3.399
+125°C
+85°C
+25°C
0°C
-40°C
3.366
3.333
VOUT (V)
VOUT (V)
3.333
+125°C
+85°C
+25°C
0°C
-40°C
3.366
3.3
3.267
3.3
3.267
3.234
3.234
NOTE: Y axis shows 1% VOUT per division
NOTE: Y axis shows 1% VOUT per division
3.201
3.201
0
100 200 300 400 500 600 700 800 900 1000
IOUT (mA)
0
5
10
Figure 2.
0.816
VOUT = 0.8V
IOUT = 750mA
+125°C
+85°C
+25°C
0°C
-40°C
0.816
VOUT = 0.8V
IOUT = 5mA
+125°C
+85°C
+25°C
0°C
-40°C
0.808
VOUT (V)
VOUT (V)
25
LINE REGULATION UNDER LIGHT LOADS
0.824
0.818
0.8
0.792
0.8
0.792
0.784
0.784
NOTE: Y axis shows 1% VOUT per division
NOTE: Y axis shows 1% VOUT per division
0.776
0.776
2.2
2.6
3
3.4
3.8
4.2 4.6
VIN (V)
Figure 4.
6
20
Figure 3.
LINE REGULATION
0.824
15
IOUT (mA)
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5
5.4
5.8
6.2
6.6
2.2
2.6
3
3.4
3.8
4.2 4.6
VIN (V)
5
5.4
5.8
6.2
6.6
Figure 5.
Copyright © 2011–2012, Texas Instruments Incorporated
TPS7A8101
www.ti.com
SBVS179A – DECEMBER 2011 – REVISED APRIL 2012
TYPICAL CHARACTERISTICS: TPS7A8101 (continued)
At VOUT(TYP) = 3.3 V, VIN = VOUT(TYP) + 0.5 V or 2.2 V (whichever is greater), IOUT = 100 mA, VEN = VIN, CIN = 1 μF,
COUT = 4.7 μF, and CNR = 0.01 μF; all temperature values refer to TJ, unless otherwise noted.
DROPOUT VOLTAGE vs INPUT VOLTAGE
500
IOUT = 1A
450
+125°C
+85°C
+25°C
0°C
-40°C
400
350
300
250
200
IOUT = 750mA
450
+125°C
+85°C
+25°C
0°C
-40°C
400
350
VDO (V)
VDO (V)
DROPOUT VOLTAGE vs INPUT VOLTAGE
500
300
250
200
150
150
100
100
50
50
0
0
2
2.5
3
3.5
4
4.5
VIN (V)
5
5.5
6
2
6.5
2.5
3
3.5
Figure 6.
+125°C
+85°C
+25°C
0°C
-40°C
400
350
300
250
200
VIN = 3.6V
450
6
6.5
+125°C
+85°C
+25°C
0°C
-40°C
400
350
VDO (V)
VDO (V)
5.5
DROPOUT VOLTAGE vs LOAD CURRENT
500
IOUT = 500mA
450
5
Figure 7.
DROPOUT VOLTAGE vs INPUT VOLTAGE
500
4
4.5
VIN (V)
300
250
200
150
150
100
100
50
50
0
0
2
2.5
3
3.5
4
4.5
VIN (V)
5
5.5
6
6.5
0
100 200 300 400 500 600 700 800 900 1000
IOUT (mA)
Figure 8.
Figure 9.
DROPOUT VOLTAGE vs TEMPERATURE
500
VIN = 3.6V
450
IOUT = 1000mA
IOUT = 750mA
IOUT = 5mA
400
VDO (V)
350
300
250
200
150
100
50
0
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 10.
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TYPICAL CHARACTERISTICS: TPS7A8101 (continued)
At VOUT(TYP) = 3.3 V, VIN = VOUT(TYP) + 0.5 V or 2.2 V (whichever is greater), IOUT = 100 mA, VEN = VIN, CIN = 1 μF,
COUT = 4.7 μF, and CNR = 0.01 μF; all temperature values refer to TJ, unless otherwise noted.
GROUND PIN CURRENT vs LOAD CURRENT
300
250
250
200
200
IGND (mA)
IGND (mA)
GROUND PIN CURRENT vs INPUT VOLTAGE
300
150
+125°C
+85°C
+25°C
0°C
-40°C
100
50
0
VOUT = 0.8V
IOUT = 750mA
2.2
2.6
3
150
+125°C
+85°C
+25°C
0°C
-40°C
100
50
0
3.4
3.8
4.2 4.6
VIN (V)
5
5.4
5.8
6.2
0
6.6
100 200 300 400 500 600 700 800 900 1000
IOUT (mA)
Figure 11.
Figure 12.
SHUTDOWN CURRENT vs TEMPERATURE
CURRENT LIMIT vs TEMPERATURE
2
1.8
1.6
VIN = 2.2V
VIN = 2.5V
VIN = 3V
VIN = 3.3V
VIN = 5V
VIN = 5.5V
VIN = 6V
VIN = 6.6V
1600
1400
1200
1.2
ICL (mA)
ISHDN (mA)
1.4
1800
1
0.8
800
600
0.6
VIN = 2.2V
VIN = 3.8V
VIN = 5.5V
VIN = 6.5V
400
0.4
200
0.2
VEN = 0.4V
0
-40 -25 -10
5
20 35 50 65
Temperature (°C)
Figure 13.
8
1000
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80
95
110 125
0
VOUT = VIN - 0.5V
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 14.
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SBVS179A – DECEMBER 2011 – REVISED APRIL 2012
TYPICAL CHARACTERISTICS: TPS7A8101 (continued)
POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY
POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY
100
100
90
90
80
80
70
70
PSRR (dB)
PSRR (dB)
At VOUT(TYP) = 3.3 V, VIN = VOUT(TYP) + 0.5 V or 2.2 V (whichever is greater), IOUT = 100 mA, VEN = VIN, CIN = 1 μF,
COUT = 4.7 μF, and CNR = 0.01 μF; all temperature values refer to TJ, unless otherwise noted.
60
50
60
50
40
40
30
VIN − VOUT = 1.0 V
VIN − VOUT = 0.5 V
VIN − VOUT = 0.3 V
20
10
10
100
1k
10k
100k
Frequency (Hz)
20
10
10M
10
100
1k
G100
VIN − VOUT = 1.0 V
CIN = 0 F, COUT = 10 µF
CNR = CBYPASS = 470 nF
10k
100k
Frequency (Hz)
1M
10M
G101
Figure 15.
Figure 16.
POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY
POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY
100
100
VIN − VOUT = 0.5 V
CIN = 0 F, COUT = 10 µF
CNR = CBYPASS = 470 nF
90
80
90
80
70
70
PSRR (dB)
PSRR (dB)
1M
IOUT= 10 mA
IOUT= 100 mA
IOUT= 750 mA
IOUT= 1 A
30
IOUT = 100 mA
CIN = 0 F, COUT = 10 µF
CNR = CBYPASS = 470 nF
60
50
60
50
40
40
IOUT= 10 mA
IOUT= 100 mA
IOUT= 750 mA
IOUT= 1 A
30
20
10
10
100
1k
IOUT= 10 mA
IOUT= 100 mA
IOUT= 750 mA
IOUT= 1 A
30
20
10k
100k
Frequency (Hz)
1M
10
10M
10
100
1k
G102
Figure 17.
VIN − VOUT = 1.0 V
CIN = 0 F, COUT = 100 µF
CNR = CBYPASS = 470 nF
10k
100k
Frequency (Hz)
1M
10M
G103
Figure 18.
POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY
100
90
PSRR (dB)
80
70
60
50
40
IOUT= 10 mA
IOUT= 100 mA
IOUT= 750 mA
IOUT= 1 A
30
20
10
10
100
1k
VIN − VOUT = 0.5 V
CIN = 0 F, COUT = 100 µF
CNR = CBYPASS = 470 nF
10k
100k
Frequency (Hz)
1M
10M
G104
Figure 19.
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TYPICAL CHARACTERISTICS: TPS7A8101 (continued)
At VOUT(TYP) = 3.3 V, VIN = VOUT(TYP) + 0.5 V or 2.2 V (whichever is greater), IOUT = 100 mA, VEN = VIN, CIN = 1 μF,
COUT = 4.7 μF, and CNR = 0.01 μF; all temperature values refer to TJ, unless otherwise noted.
POWER-SUPPLY RIPPLE REJECTION
vs DROPOUT VOLTAGE
90
90
IOUT = 100mA
No CIN
80
70
70
60
60
50
40
f = 1kHz
f = 10kHz
f = 100kHz
f = 1MHz
30
20
f = 1kHz
f = 10kHz
f = 100kHz
f = 1MHz
20
0.5
1
1.5
2
VDO (V)
2.5
3
Output Spectral Noise Density (µV/ Hz)
0.1
CNR = CBYPASS = 100 nF
CNR = CBYPASS = 470 nF
100
1k
Frequency (Hz)
10k
100k
3
RMS Noise (100 Hz to 100 kHz)
25.89 µVRMS (VOUT = 1.8 V)
23.54 µVRMS (VOUT = 2.5 V)
23.54 µVRMS (VOUT = 3.3 V)
VIN − VOUT = 0.5 V
CIN = 10 µF, COUT = 10 µF
CNR = 470 nF, CBYPASS = 470 nF
10
1
0.1
0.01
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
10
100
1k
Frequency (Hz)
10k
Figure 23.
OUTPUT SPECTRAL NOISE DENSITY
vs FREQUENCY
OUTPUT SPECTRAL NOISE DENSITY
vs FREQUENCY
10
1
IOUT = 100 mA
IOUT = 750 mA
IOUT = 1 A
100
1k
Frequency (Hz)
Figure 24.
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10k
100k
G202
100k
G201
Figure 22.
RMS Noise (100 Hz to 100 kHz)
23.54 µVRMS (IOUT = 100 mA)
23.71 µVRMS (IOUT = 750 mA)
22.78 µVRMS (IOUT = 1 A)
VIN − VOUT = 0.5 V
CIN = 10 µF, COUT = 10 µF
CNR = 470 nF, CBYPASS = 470 nF
3.5
100
G200
100
10
2.5
OUTPUT SPECTRAL NOISE DENSITY
vs FREQUENCY
1
0.01
1.5
2
VDO (V)
OUTPUT SPECTRAL NOISE DENSITY
vs FREQUENCY
10
0.1
1
Figure 21.
RMS Noise (100 Hz to 100 kHz)
24.09 µVRMS (CNR = CBYPASS = 100 nF)
23.54 µVRMS (CNR = CBYPASS = 470 nF)
VIN − VOUT = 0.5 V
CIN = 10 µF
COUT = 10 µF
10
0.5
Figure 20.
100
0.01
0
3.5
Output Spectral Noise Density (µV/ Hz)
Output Spectral Noise Density (µV/ Hz)
40
10
0
Output Spectral Noise Density (µV/ Hz)
50
30
10
10
IOUT = 750mA
No CIN
80
PSRR (dB)
PSRR (dB)
POWER-SUPPLY RIPPLE REJECTION
vs DROPOUT VOLTAGE
100
RMS Noise (100 Hz to 100 kHz)
23.54 µVRMS (COUT = 10 µF)
23.91 µVRMS (COUT = 22 µF)
22.78 µVRMS (COUT = 100 µF)
VIN − VOUT = 0.5 V
CIN = 10 µF, COUT = 10 µF
CNR = 470 nF, CBYPASS = 470 nF
10
1
0.1
0.01
COUT = 10 µF
COUT = 22 µF
COUT = 100 µF
10
100
1k
Frequency (Hz)
10k
100k
G203
Figure 25.
Copyright © 2011–2012, Texas Instruments Incorporated
TPS7A8101
www.ti.com
SBVS179A – DECEMBER 2011 – REVISED APRIL 2012
TYPICAL CHARACTERISTICS: TPS7A8101 (continued)
At VOUT(TYP) = 3.3 V, VIN = VOUT(TYP) + 0.5 V or 2.2 V (whichever is greater), IOUT = 100 mA, VEN = VIN, CIN = 1 μF,
COUT = 4.7 μF, and CNR = 0.01 μF; all temperature values refer to TJ, unless otherwise noted.
STARTUP TIME
vs NOISE REDUCTION CAPACITANCE
LINE TRANSIENT RESPONSE
1000
7
3.333
VIN (V), 0.5V/div
6
100
10
1
3.3165
5.5
3.30825
VIN = 3.8V ® 4.8V ® 3.8V (1V/div)
5
3.29175
4.5
3.2835
4
10
100
CNR = CBYPASS (nF)
3.27525
IOUT = 500mA
3.267
3
50ms/div
1000
G300
Figure 26.
Figure 27.
LOAD TRANSIENT RESPONSE
ENABLE PULSE RESPONSE(1)
4.5
3.85
3.8
3.75
4
VIN (for reference)
3.5
3.7
VOUT
2.5
2
3.3
IOUT = 100mA ® 1A ® 100mA (1A/ms)
1.5
1
3.2
2
1.5
1
0.5
0
0.5
3.15
3.15
OUT
2.5
IOUT (A)
3.25
EN
3
VEN, VOUT (V)
3.35
3.3
3.5
Using same value of CNR and CBYPASS
in X axis
VIN, VOUT (V)
3.32475
VOUT
VOUT (V), 0.25% of 3.3V/div
EN↑ to 90%VOUT (ms)
6.5
RLOAD = 33 Ω
CIN = 10 µF
COUT = 10 µF
CNR = 470nF
CBYPASS = 470 nF
−0.5
0
50ms/div
Time (50 ms/div)
Figure 28.
G005
Figure 29.
POWER-UP/POWER-DOWN RESPONSE(1)
7
6
VIN, VOUT (V)
5
VIN = VEN
4
VOUT
3
2
1
0
−1
RLOAD = 33 Ω
CIN = 10 µF
COUT = 10 µF
CNR = 470nF
CBYPASS = 470 nF
Time (50 ms/div)
G006
Figure 30.
(1)
The internal reference requires approximately 80 ms of rampup time (see STARTUP) from the enable event;
therefore, VOUT fully reaches the target output voltage of 3.3 V in 80 ms from starup.
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TPS7A8101
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www.ti.com
APPLICATION INFORMATION
OVERVIEW
The TPS7A8101 belongs to a family of new generation LDO regulators that use innovative circuitry to achieve
wide bandwidth and high loop gain, resulting in extremely high PSRR (over a 1-MHz range) at very low
headroom (VIN – VOUT). A noise reduction capacitor (CNR) at the NR pin and a bypass capacitor (CBYPASS) bypass
noise generated by the bandgap reference in order to improve PSRR, while a quick-start circuit fast-charges the
noise reduction capacitor. This family of regulators offers sub-bandgap output voltages, current limit, and thermal
protection, and is fully specified from –40°C to +125°C.
Recommended Component Values
Table 1. Recommended Capacitor Values
SYMBOL
NAME
VALUE
CIN
Input capacitor
10 µF
COUT
Output capacitor
10 µF
CNR
Noise reduction capacitor between NR and GND
470 nF
CBYPASS
Noise reduction capacitor across R1
470 nF
Table 2. Recommended Feedback Resistor Values for Common Output Voltages
VOUT
R1
R2
0.8 V
0 Ω (Short)
10.0 kΩ
1.0 V
2.49 kΩ
10.0 kΩ
1.2 V
4.99 kΩ
10.0 kΩ
1.5 V
8.87 kΩ
10.0 kΩ
1.8 V
12.5 kΩ
10.0 kΩ
2.5 V
21.0 kΩ
10.0 kΩ
3.3 V
30.9 kΩ
10.0 kΩ
5.0 V
52.3 kΩ
10.0 kΩ
TYPICAL APPLICATION CONFIGURATION
Figure 31 illustrates the connections for the device.
VIN
IN
CIN
VOUT
OUT
R1
TPS7A8101
EN
GND
FB
NR
CNR
CBYPASS
R2
COUT
VEN
Figure 31. Typical Application Circuit
(Adjustable Voltage Version)
The voltage on the FB pin sets the output voltage and is determined by the values of R1 and R2. The values of
R1 and R2 can be calculated for any voltage using the formula given in Equation 1:
(R + R2 )
VOUT = 1
x 0.800
R2
(1)
Table 2 shows sample resistor values for common output voltages. In Table 2, E96 series resistors are used,
and all values meet 1% of the target VOUT, assuming resistors with zero error. For the actual design, pay
attention to any resistor error factors. Using lower values for R1 and R2 reduces the noise injected from the FB
pin.
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INPUT AND OUTPUT CAPACITOR REQUIREMENTS
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to
1.0-μF low equivalent series resistance (ESR) capacitor across the input supply near the regulator. This
capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple
rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or if
the device is located several inches from the power source. If source impedance is not sufficiently low, a 0.1-μF
input capacitor may be necessary to ensure stability.
The TPS7A8101 is designed to be stable with standard ceramic capacitors of capacitance values 4.7 μF or
larger. This device is evaluated using a 10-μF ceramic capacitor of 10-V rating, 10% tolerance, X5R type, and
0805 size (2.0 mm x 1.25 mm).
X5R- and X7R-type capacitors are highly recommended because they have minimal variation in value and ESR
over temperature. Maximum ESR should be less than 1.0 Ω.
OUTPUT NOISE
In most LDOs, the bandgap is the dominant noise source. If a noise reduction capacitor (CNR) is used with the
TPS7A8101, the bandgap does not contribute significantly to noise. Instead, noise is dominated by the output
resistor divider and the error amplifier input. If a bypass capacitor (CBYPASS) across the high-side feedback
resistor (R1) is used with the TPS7A8101 in addition to CNR, noise from these other sources can also be
significantly reduced.
To maximize noise performance in a given application, use a 0.47-μF noise-reduction capacitor plus a 0.47-μF
bypass capacitor.
BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE
To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the
board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the
GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the
GND pin of the device.
INTERNAL CURRENT LIMIT
The TPS7A8101 internal current limit helps protect the regulator during fault conditions. During current limit, the
output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, the
device should not be operated in a current limit state for extended periods of time.
The PMOS pass element in the TPS7A8101 has a built-in body diode that conducts current when the voltage at
OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is
anticipated, external limiting may be appropriate.
SHUTDOWN
The enable pin (EN) is active high and is compatible with standard and low voltage, TTL-CMOS levels. When
shutdown capability is not required, EN can be connected to IN.
DROPOUT VOLTAGE
The TPS7A8101 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the
dropout voltage (VDO), the PMOS pass device is in its linear region of operation and the input-to-output
resistance is the RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the
PMOS device in dropout behaves the same way as a resistor.
As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout.
This effect is shown in Figure 20 and Figure 21 in the Typical Characteristics section.
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TPS7A8101
SBVS179A – DECEMBER 2011 – REVISED APRIL 2012
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STARTUP
Through a lower resistance, the bandgap reference can quickly charge the noise reduction capacitor (CNR). The
TPS7A8101 has a quick-start circuit to quickly charge CNR, if present; see the Functional Block Diagrams. At
startup, this quick-start switch is closed, with only 33 kΩ of resistance between the bandgap reference and the
NR pin. The quick-start switch opens approximately 100 ms after any device enabling event, and the resistance
between the bandgap reference and the NR pin becomes higher in value (approximately 250 kΩ) to form a very
good low-pass (RC) filter. This low-pass filter achieves very good noise reduction for the reference voltage.
Inrush current can be a problem in many applications. The 33-kΩ resistance during the startup period is
intentionally put there to slow down the reference voltage ramp up, thus reducing the inrush current. For
example, the capacitance of connecting the recommended CNR value of 0.47 μF along with the 33-kΩ resistance
causes approximately 80-ms RC delay. Startup time with the other CNR values can be calculated as:
tSTR (s) = 170,000 x CNR (F)
(2)
Although the noise reduction effect is nearly saturated at 0.47 μF, connecting a CNR value greater than 0.47 μF
can help reduce noise slightly more; however, startup time will be extremely long because the quick-start switch
opens after approximately 100 ms. That is, if CNR is not fully charged during this 100-ms period, CNR finishes
charging through a higher resistance of 250 kΩ, and takes much longer to fully charge.
Note that a low leakage CNR should be used; most ceramic capacitors are suitable.
TRANSIENT RESPONSE
As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but
increases duration of the transient response. Line transient performance can be improved by using a larger noise
reduction capacitor (CNR) and/or bypass capacitor (CBYPASS).
UNDERVOLTAGE LOCK-OUT (UVLO)
The TPS7A8101 uses an undervoltage lock-out circuit to keep the output shut off until the internal circuitry is
operating properly. The UVLO circuit has a de-glitch feature so that it typically ignores undershoot transients on
the input if they are less than 50-μs duration.
MINIMUM LOAD
The TPS7A8101 is stable and well-behaved with no output load. Traditional PMOS LDO regulators suffer from
lower loop gain at very light output loads. The TPS7A8101 employs an innovative low-current mode circuit to
increase loop gain under very light or no-load conditions, resulting in improved output voltage regulation
performance down to zero output current.
THERMAL INFORMATION
Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing
the device to cool. When the junction temperature cools to approximately +140°C the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage
because of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to +125°C maximum. To estimate the
margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should
trigger at least +35°C above the maximum expected ambient condition of your particular application. This
configuration produces a worst-case junction temperature of +125°C at the highest expected ambient
temperature and worst-case load.
The internal protection circuitry of the TPS7A8101 has been designed to protect against overload conditions. It
was not intended to replace proper heatsinking. Continuously running the TPS7A8101 into thermal shutdown
degrades device reliability.
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TPS7A8101
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SBVS179A – DECEMBER 2011 – REVISED APRIL 2012
Power Dissipation
Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad
is critical to avoiding thermal shutdown and ensuring reliable operation.
Power dissipation of the device depends on input voltage and load conditions and can be calculated using
Equation 3:
P D + ǒVIN * VOUTǓ
I OUT
(3)
Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input
voltage necessary to achieve the required output voltage regulation.
On the SON (DRB) package, the primary conduction path for heat is through the exposed pad to the printed
circuit board (PCB). The pad can be connected to ground or be left floating; however, it should be attached to an
appropriate amount of copper PCB area to ensure the device does not overheat. The maximum junction-toambient thermal resistance depends on the maximum ambient temperature, maximum device junction
temperature, and power dissipation of the device and can be calculated using Equation 4:
(+125°C - TA)
RqJA =
PD
(4)
Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heatsinking can
be estimated using Figure 32.
160
140
qJA (°C/W)
120
100
80
60
40
20
0
0
Note:
1
2
4
5
7
3
6
Board Copper Area (in2)
8
9
10
θJA value at board size of 9 in2 (that is, 3 in × 3 in) is a JEDEC standard.
Figure 32. θJA vs Board Size
Figure 32 shows the variation of θJA as a function of ground plane copper area in the board. It is intended only as
a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate
actual thermal performance in real application environments.
NOTE: When the device is mounted on an application PCB, it is strongly recommended to use ΨJT and ΨJB, as
explained in the Estimating Junction Temperature section.
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TPS7A8101
SBVS179A – DECEMBER 2011 – REVISED APRIL 2012
www.ti.com
Estimating Junction Temperature
Using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature can
be estimated with corresponding formulas (given in Equation 5). For backwards compatibility, an older θJC,Top
parameter is listed as well.
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
(5)
Where PD is the power dissipation shown by Equation 4, TT is the temperature at the center-top of the IC
package, and TB is the PCB temperature measured 1 mm away from the IC package on the PCB surface (as
Figure 33 shows).
TT on top
of IC surface
TB
TB on PCB
TT
1mm
1mm
Figure 33. Measuring Points for TT and TB
NOTE: Both TT and TB can be measured on actual application boards using an infrared thermometer.
For more information about measuring TT and TB, see the application note SBVA025, Using New Thermal
Metrics, available for download at www.ti.com.
By looking at Figure 34, the new thermal metrics (ΨJT and ΨJB) have very little dependency on board size. That
is, using ΨJT or ΨJB with Equation 5 is a good way to estimate TJ by simply measuring TT or TB, regardless of the
application board size.
20
18
YJB
YJT and YJB (°C/W)
16
14
12
10
8
6
YJT
4
2
0
0
1
2
3
4
5
6
7
8
9
10
Board Copper Area (in2)
Figure 34. ΨJT and ΨJB vs Board Size
For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics,
refer to application report SBVA025, Using New Thermal Metrics, available for download at www.ti.com. For
further information, refer to application report SPRA953, IC Package Thermal Metrics, also available on the TI
website.
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TPS7A8101
www.ti.com
SBVS179A – DECEMBER 2011 – REVISED APRIL 2012
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (December 2011) to Revision A
•
Page
Added new footnote 2 to Thermal Information table, changed footnote 3 ........................................................................... 3
Copyright © 2011–2012, Texas Instruments Incorporated
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17
PACKAGE OPTION ADDENDUM
www.ti.com
14-Apr-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
TPS7A8101DRBR
ACTIVE
SON
DRB
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TPS7A8101DRBT
ACTIVE
SON
DRB
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS7A8101DRBR
SON
DRB
8
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS7A8101DRBT
SON
DRB
8
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS7A8101DRBR
SON
DRB
8
3000
367.0
367.0
35.0
TPS7A8101DRBT
SON
DRB
8
250
210.0
185.0
35.0
Pack Materials-Page 2
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