ST ST8008 80 Output LCD Segment Driver IC PRELIMINARY Notice: Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. specification. Some parameters are subject to change. This is not a final DESCRIPTION The ST8008 is a 80-output segment driver IC suitable for driving small/medium scale dot matrix LCD panels, and is used in PDA or electronic dictionary. The ST8008 is good as a segment driver, and it can create a low power consuming, high-resolution LCD. FEATURES Number of LCD drive outputs: 80 Supply voltage for LCD drive: Max +16V Supply voltage for the logic system: +2.5 to +5.5 V Low power consumption Package: 96-pin COB. (Segment mode) Shift clock frequency - 20 MHz (MAX.): VDD = +5.0 ± 0.5 V - 15 MHz (MAX.): VDD = +3.0 to + 4.5 V - 12 MHz (MAX.): VDD = +2.5 to + 3.0 V Adopts a data bus system 4-bit parallel / serial input modes are selectable with a mode (P/S) pin Automatic transfer function of an enable signal Automatic counting function which, in the chip selection mode, causes the internal clock to be stopped by automatically counting 80 bits of input data Line latch circuits are reset when XDISPOFF active V0.3 1/ 21 2004/04/05 ST8008 Pad Arrangement Chip size: 3800(µm)X1560(µm) Pad size: 80(µm)X80(µm) Pin Pitch: 100(µm)~120(µm) Origin: chip center(0,0) Chip Thiclness:19 mil SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 8 7 6 5 4 3 2 1 96 97 92 93 24 37 36 35 34 33 32 31 30 29 28 27 26 25 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 39 38 42 41 40 43 44 88 89 45 47 46 48 PIN1 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 2004/04/05 2/21 V0.3 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Substrate Connect to Vss. ST8008 Pad Location Coordinates Pad No Function X Y Pad No Function X Y 1 CS[70] 1785 665 37 CS[9] -1785 665 2 CS[71] 1665 665 38 CS[10] -1785 555 3 CS[72] 1555 665 39 CS[11] -1785 450 4 CS[73] 1450 665 40 CS[12] -1785 350 5 CS[74] 1350 665 41 CS[13] -1785 250 6 CS[75] 1250 665 42 CS[14] -1785 150 7 CS[76] 1150 665 43 CS[15] -1785 50 8 CS[77] 1050 665 44 CS[16] -1785 -50 9 CS[78] 950 665 45 CS[17] -1785 -150 10 CS[79] 850 665 46 CS[18] -1785 -250 11 V0 750 665 47 CS[19] -1785 -350 12 V2 650 665 48 CS[20] -1785 -450 13 V3 550 665 49 CS[21] -1785 -555 14 ED[3] 450 665 50 CS[22] -1785 -665 15 ED[2] 350 665 51 CS[23] -1665 -665 16 ED[1] 250 665 52 CS[24] -1555 -665 17 ED[0] 150 665 53 CS[25] -1450 -665 18 EIO1 50 665 54 CS[26] -1350 -665 19 EIO2 -50 665 55 CS[27] -1250 -665 20 XCKPAD -150 665 56 CS[28] -1150 -665 21 FRPAD -250 665 57 CS[29] -1050 -665 22 LPPAD -350 665 58 CS[30] -950 -665 23 VDD -450 665 59 CS[31] -850 -665 24 LRPAD -450 517.15 60 CS[32] -750 -665 25 XDISPAD -550 665 61 CS[33] -650 -665 26 PSPAD -650 665 62 CS[34] -550 -665 27 VSS -750 665 63 CS[35] -450 -665 28 CS[0] -850 665 64 CS[36] -350 -665 29 CS[1] -950 665 65 CS[37] -250 -665 30 CS[2] -1050 665 66 CS[38] -150 -665 31 CS[3] -1150 665 67 CS[39] -50 -665 32 CS[4] -1250 665 68 CS[40] 50 -665 33 CS[5] -1350 665 69 CS[41] 150 -665 34 CS[6] -1450 665 70 CS[42] 250 -665 35 CS[7] -1555 665 71 CS[43] 350 -665 36 CS[8] -1665 665 72 CS[44] 450 -665 V0.3 3/21 2004/04/05 ST8008 Pad No Function X Y 73 CS[45] 550 -665 74 CS[46] 650 -665 75 CS[47] 750 -665 76 CS[48] 850 -665 77 CS[49] 950 -665 78 CS[50] 1050 -665 79 CS[51] 1150 -665 80 CS[52] 1250 -665 81 CS[53] 1350 -665 82 CS[54] 1450 -665 83 CS[55] 1555 -665 84 CS[56] 1665 -665 85 CS[57] 1785 -665 86 CS[58] 1785 -555 87 CS[59] 1785 -450 88 CS[60] 1785 -350 89 CS[61] 1785 -250 90 CS[62] 1785 -150 91 CS[63] 1785 -50 92 CS[64] 1785 50 93 CS[65] 1785 150 94 CS[66] 1785 250 95 CS[67] 1785 350 96 CS[68] 1785 450 97 CS[69] 1785 555 V0.3 4/21 2004/04/05 ST8008 PIN DESCRIPTION SYMBOL I/O DESCRIPTION No of Num SEG0-SEG79 O LCD drive output 80 V0,V2,V3 P Power supply for LCD drive 3 XDISPOFF I Control input for output of non-select level 1 VDD P Power supply for logic system (+2.5 to +5.5 V) 1 EIO2, EIO1 I/O Input/output for chip selection at segment mode and FLM input output function at com/seg mix mode or common mode 2 DI0-DI3 I Display data input at segment mode 4 XCK I Clock input for taking display data at segment mode 1 L/R I Display data shift direction selection I Latch pulse input for display data at segment mode/ LP FR Shift clock input for shift register at common mode I AC-converting signal input for LCD drive waveform 1 1 This is the parallel data input/serial data input switch terminal. P/S I P/S=”H”: Parallel data input. 1 P/S=”L”: Serial data input. VSS V0.3 P Ground (0 V) 1 5/21 2004/04/05 ST8008 BLOCK DIAGRAM V0.3 6/21 2004/04/05 ST8008 INPUT/OUTPUT CIRCUITS V DD I T o In te rn a l C irc u it A p p lic a b le P in s X D IS P O F F , D I 3 ~ D I 0 , L P , F R , P /S ,L /R V s s (0 V ) Input Circuit V DD To Internal Circuit I /O Control Signal Vss (0V) Vss (0V) V DD Output Signal Application Pins EIO 1 , EIO 2 Control Signal Vss (0V) Input/Output Circuit V0.3 7/21 2004/04/05 ST8008 FUNCTIONAL DESCRIPTION Pin Functions SYMBOL FUNCTION VDD Logic system power supply pin, connected to +2.5 to +5.5 V. VSS Ground pin, connected to 0 V. This is a multi-level power supply for the liquid crystal drive. The voltage Supply applied is determined by the liquid crystal cell, and is changed through the use of a resistive voltage divided or V0 V2 V3 through changing the impedance using an op. amp. Voltage levels are determined based on VSS, and must maintain the relative magnitudes shown below. V0 ≧V2 ≧V3≧Vss Input pins for display data In 4-bit parallel input mode, input data into the 4 pins, DI3-DI0. DI3-DI0 In serial input mode, input data into the 1 pin DI0. Connect DI3-DI1 to VSS or VDD Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. XCK LP Clock input pin for taking display data * Data is read at the falling edge of the clock pulse. Latch pulse input pin for display data Data is latched at the falling edge of the clock pulse. Control input pin for output of non-select level The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. When set to VSS level "L", the LCD drive output pins (SEG0~SEG79) are set to level Vss. XDISPOFF When set to "L", the contents of the line latch are reset, but the display data are read in the data latch regardless of the condition of /DISPOFF. When the XDISPOFF function is canceled, the driver outputs non-select level (V2 or V3), then outputs the contents of the data latch at the next falling edge of the LP. At that time, if XDISPOFF removal time does not correspond to what is shown in AC characteristics, it cannot output the reading data correctly. Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. AC signal input pin for LCD drive waveform The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. FR Normally it inputs a frame inversion signal. The LCD drive output pins' output voltage levels can be set using the line latch output signal and the FR signal. Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. P/S V0.3 Interface Mode selection pin When P/S is “H” then parallel data input mode. 8/21 2004/04/05 ST8008 When P/S is “L” the serial data input mode, Input pin for selecting the reading direction of display data. Default value is LOW When set to VSS level "L", data is read sequentially from SEG79 to SEG0. L/R When set to VDD level "H", data is read sequentially from SEG0 to SEG79. Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Input/output pins for chip selection. AT segment mode: When L/R input is at VSS level "L", ElO1 is set for output, and EIO2 is set for input(connect to Vss). When L/R input is at VDD level "H", ElO1 is set for input(connect to Vss), and EIO2 is set for ElO1, EIO2 output. During output, set to "H" while LP • XCK is "H" and after 80 bits of data have been read, set to "L” for one cycle (from falling edge to failing edge of XCK), after which it returns to "H". During input, the chip is selected while El is set to "L" after the LP signal is input. The chip is non-selected after 80 bits of data have been read. LCD drive output pins SEG0–SEG79 Corresponding directly to each bit of the data latch, one level (V0, V2, V3, and Vss) is selected and output. Table of truth values is shown in "TRUTH TABLE" in Functional Operations. Functional Operations LCD DRIVE OUTPUT VOLTAGE LEVEL FR LATCH DATA /DISPOFF L L H V3 L H H Vss H L H V2 H H H V0 X X L Vss (SEG0-SEG79) TRUTH TABLE NOTES: L : VSS (0 V), H : VDD (+2.5 to +5.5 V), "Don't care" should be fixed to "H" or "L", avoiding floating. There are two kinds of power supply (logic level voltage and LCD drive voltage) for the LCD driver. Supply regular voltage that is assigned by specification for each power pin. V0.3 9/21 2004/04/05 ST8008 RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS (A) 4-bit Parallel Input Mode L/R L EIO1 EIO2 DATA INPUT 20 CLOCK 19 CLOCK 18 CLOCK … 3 CLOCK 2 CLOCK 1 CLOCK DI0 SEG0 SEG4 SEG8 … SEG68 SEG72 SEG76 Dl1 SEG1 SEG5 SEG9 … SEG69 SEG73 SEG77 DI2 SEG2 SEG6 SEG10 … SEG70 SEG74 SEG78 DI3 SEG3 SEG7 SEG11 … SEG71 SEG75 SEG79 DI0 SEG79 SEG75 SEG71 … SEG11 SEG7 SEG3 Dl1 SEG78 SEG74 SEG70 … SEG10 SEG6 SEG2 DI2 SEG77 SEG73 SEG69 … SEG9 SEG5 SEG1 DI3 SEG76 SEG72 SEG68 … SEG8 SEG4 SEG0 3 CLOCK 2 CLOCK 1 CLOCK Output Input H Input NUMBER OF CLOCKS Output (B) Serial Input Mode L/R EIO1 EIO2 L Output Input H Input Output DATA NUMBER OF CLOCKS INPUT 80 CLOCK 79 CLOCK 78 CLOCK … DI0 SEG0 SEG1 SEG2 … SEG77 SEG78 SEG79 Dl1 X X X X X X X DI2 X X X X X X X DI3 X X X X X X X DI0 SEG79 SEG78 SEG77 … SEG2 SEG1 SEG0 Dl1 X X X X X X X DI2 X X X X X X X DI3 X X X X X X X NOTES: L : VSS (0 V), H : VDD (+2.5 to +5.5 V), X : Don't care "Don't care" should be fixed to "H" or "L", avoiding floating. V0.3 10/21 2004/04/05 ST8008 (A) Connection examples of plural segment drivers When L/R = “L” Top data Last data Data flow SEG79 SEG0 EIO2 EIO1 SEG79 SEG0 SEG79 EIO2 EIO1 L/R SEG0 EIO2 EIO1 L/R L/R DI3-DI0 FR FR LP FR LP XCK LP XCK DI3-DI0 XCK DI3-DI0 FR LP XCK XCK LP FR DI3-DI0 4 VSS (B) When L/R = “H” VDD XCK LP FR DI3-DI0 4 Data flow EIO1 SEG0 EIO2 SEG79 SEG79 Last data Top data V0.3 L/R EIO2 SEG79 SEG0 DI3-DI0 EIO1 FR L/R EIO2 LP SEG0 XCK EIO1 DI3-DI0 DI3-DI0 FR LP XCK L/R Vss 11/21 2004/04/05 ST8008 Timing chart of 4-device cascade connection of segment drivers FR LP XCK TOP DATA DI3 - DI0 n* 1 2 LAST DATA n* device A 1 2 n* 1 2 device B n* device C 1 2 n* 1 2 device D EI (device A) EO (device A) EO (device B) EO (device C) *n = 20 in 4-bit parallel input mode *n = 80 in serial input mode V0.3 12/21 2004/04/05 ST8008 PRECAUTIONS Precautions when connecting or disconnecting the power supply This IC has a high-voltage LCD driver, so a high current that may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating may permanently damage it. The details are as follows, When connecting the power supply, connect the LCD drive power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD drive power And when connecting the logic power supply, the logic condition of this IC inside is insecure. Therefore connect the LCD drive power supply after resetting logic condition of this IC inside on XDISPOFF function. After that, cancel the XDISPOFF function after the LCD drive power supply has become stable. Furthermore, when disconnecting the power, set the LCD drive output pins to level Vss on XDISPOFF function. Then disconnect the logic system power after disconnecting the LCD drive power. When connecting the power supply, follow the recommended sequence shown here VDD VDD VSS VDD XDISPOFF VSS VDD V0 VSS V0.3 13/21 2004/04/05 ST8008 Application Timing Block: Example 160X80 Frame and Lp falling edge (or rising edge) must >10ns Parallel vs. Serial Interface Diagram S1 S2 S3 S4 S5 S6 S7 S8 S15 S158 7 1 2 3 4 5 6 7 8 157 158 S15 S16 9 0 159 160 LP D3 D2 D1 D0 D0 V0.3 1 5 9 13 145 149 153 157 1 5 9 2 6 10 14 146 150 154 158 2 6 10 3 7 11 15 147 151 155 159 3 7 11 4 8 12 16 148 152 156 160 4 8 12 1 2 3 4 7 8 158 159 5 6 14/21 157 160 2004/04/05 ST8008 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL APPLICABLE PINS RATING UNIT VDD VDD -0.3~+7.0 V V2 V2 VDD-10~ VDD+0.3 V3 V3 -0.3~V5S+10 V -0.3 to VDD+0.3 V -45 to +125 °C Supply voltage (1) Input voltage Storage temperature VI D14-DI0, XCK, LP, L/R, FR, EIO1, EIO2, XDISPOFF TSTG NOTE 1,2 NOTES: 1. TA = +25 °C 2. The maximum applicable voltage on any pin with respect to VSS (0 V). RECOMMENDED OPERATING Conditions PARAMETER SYMBOL APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE Supply voltage (1) VDD VDD +2.5 +5.5 V Supply voltage (2) V0 V0 +6.0 +16.0 V Operating temperature TOPR -20 +85 °C 1, 2 NOTES: 1. The applicable voltage on any pin with respect to VSS (0 V). 2. Ensure that voltages are set such that V2 ≧V3 ≧VSS. V0.3 15/21 2004/04/05 ST8008 ELECTRICAL CHARACTERISTICS DC Characteristics (VSS = 0 V, VDD = +2.5 to +5.5 V, V0 = + 6.0 to +15.0 V, TOPR = -20 to +85°C) PARAMETER Input "Low" voltage SYMBOL CONDITIONS VIL APPLICABLE PINS VIH Output "Low" voltage VOL IOL = +0.4 mA Output "High" voltage VOH IOH = -0.4 mA ILIL VI = VSS ILIH VI = VDD Input leakage current |∆VON| V0 = 30 TYP. MAX. UNIT NOTE DI3-DI0, XCK, LP, L/R 0.2VD FR, EIO1, EIO2, D XDISPOFF Input "High" voltage MIN. 0.8VDD V +0.4 EIO1, EIO2 VDD-0.4 V V DI3-DI0, XCK, LP, LIR, FR, EIO1, EIO2, XDISPOFF µA +10 µA 2.0 kΩ RON Standby current ISTB VSS 50 µA 1 ISS VSS 2.0 mA 2 I0 V0 0.9 mA 4 Supply current (1) (Non-selection) Supply current (2) V 1.5 -10 Output resistance =0.5V SEG0-SEG79 V NOTES: 1. VDD = +3.0 V, V0 = +12.0 V 2. VDD = +3.0 V, V0 = +12.0 V, fXCK = 8 MHz, no-load, El = VDD. The input data is turned over by data taking clock (4-bit parallel input mode). 3. VDD = +3.0 V, V0 = +12.0 V, fXCK = 8 MHz, no-load, El = VSS. The input data is turned over by data taking clock (4-bit parallel input mode). 4. VDD = +3.0 V, V0 = +12.0 V, fXCK = 8MHz, fLP = 19.2 kHz, fFR = 80 Hz, no-load. The input data is turned over by data taking clock (4-bit parallel input mode). V0.3 16/21 2004/04/05 ST8008 AC Characteristics (VSS = 0 V, VDD = +2.5 to +3.0 V, V0 = + 6.0 to +15.0 V, TOPR = -20 10+85 °C) PARAMETER SYMBOL CONDITIONS MIN TYP. Shift clock period tWCK tR,tF ≤ 11ns 125 Shift clock "H" pulse width tWCKH 51 Shift clock "L" pulse width tWCKL 51 Data setup time tDS 30 Data hold time tDH 40 Latch pulse "H" pulse width tWLPH 51 Shift clock rise to latch pulse rise time tLD 0 Shift clock fall to latch pulse fall time tSL 51 Latch pulse rise to shift clock rise time tLS 51 Latch pulse fall to shift clock fall time tLH 51 Latch pulse fall to shift clock rise time tLSW 50 Enable setup time tS 36 Input signal rise time tR Input signal fall time tF DISPOFF removal time tSD 100 DISPOFF "L" pulse width tWDL 1.2 Output delay time (1) tD CL = 15 pF Output delay time (2) tPD1, t PD2 CL = 15 pF Output delay time (3) t PD3 CL = 15 pF NOTES: 1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation. MAX. 50 50 78 1.2 1.2 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns µs µs NOTE 1 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns µs µs NOTE 1 2 2 (VSS = 0 V, VDD = +5.0±0.5 V, V0 = + 6.0 to +15.0 V, TOPR = -20 to +85 °C) PARAMETER SYMBOL CONDITIONS Shift clock period tWCK tR,tF ≤ 10ns Shift clock "H" pulse width tWCKH Shift clock "L” pulse width tWCKL Data setup time tDS Data hold time tDH Latch pulse "H" pulse width tWLPH Shift clock rise to latch pulse rise time tLD Shift clock fall to latch pulse fall time tSL Latch pulse rise to shift clock rise time tLS Latch pulse fall to shift clock fall time tLH Latch pulse fall to shift clock rise time tLSW Enable setup time tS Input signal rise time tR Input signal fall time tF DISPOFF removal time tSD DISPOFF "L" pulse width tWDL Output delay time (1) tD CL = 15 pF Output delay time (2) tPD1, tPD2 CL = 15 pF Output delay time (3) tPD3 CL = 15 pF NOTES:1. Takes the cascade connection into consideration. MIN. 66 23 23 15 23 30 0 50 30 30 50 15 TYP. MAX. 50 50 100 1.2 41 1.2 1.2 2 2 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation. V0.3 17/21 2004/04/05 ST8008 (VSS = 0 V, VDD = +3.0 to +4.5 V, V0 = + 6.0 to +15.0 V, TOPR = -20 10+85 °C) PARAMETER SYMBOL CONDITIONS Shift clock period tWCK tR,tF ≤ 10ns Shift clock "H" pulse width tWCKH Shift clock "L” pulse width tWCKL Data setup time tDS Data hold time tDH Latch pulse "H" pulse width tWLPH Shift clock rise to latch pulse rise time tLD Shift clock fall to latch pulse fall time tSL Latch pulse rise to shift clock rise time tLS Latch pulse fall to shift clock fall time tLH Latch pulse fall to shift clock rise time tLSW Enable setup time tS Input signal rise time tR Input signal fall time tF DISPOFF removal time tSD DISPOFF "L" pulse width tWDL Output delay time (1) tD CL = 15 pF Output delay time (2) tPD1, t PD2 CL = 15 pF Output delay time (3) t PD3 CL = 15 pF NOTES:1. Takes the cascade connection into consideration. MIN. 82 28 28 20 23 30 0 51 30 30 50 15 TYP. MAX. 50 50 100 1.2 57 1.2 1.2 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns µs µs NOTE 1 2 2 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation. V0.3 18/21 2004/04/05 ST8008 Timing Chart of Segment Mode tWLPH LP tLD tSL tLH tLS tWCKH tWCKL XCK tR tF tWCK DI4 - DI0 tDS LAST DATA tDH TOP DATA tWDL tSD XDISPOFF FR tPD1 LP tPD2 XDISPOFF tPD3 SEG0 - SEG79 V0.3 19/21 2004/04/05 ST8008 Application Circuit (a) When use one ST8009 and two ST8008 (160X96) (b) When use one ST8009 and one ST8008 (112X64) V0.3 20/21 2004/04/05 ST8008 ST8008 Serial Specification Revision History ST8008 Serial Specification Revision History Version Date Description 0.0 2004/01/05 Preliminary version 0.1 2004/04/05 Add application timing block diagram 0.2 2004/09/08 Define timing of segment mode . 0.3 2005/02/14 Revise graph of ST8008(SID, SCLK) The above information is the exclusive intellectual property of Sitronix Technology Corp. and shall not be disclosed, distributed or reproduced without permission from Sitronix. V0.3 21/21 2004/04/05