SONY CXG1214UR

High Power 3P3T Switch with Logic Control
CXG1214UR
Description
The CXG1214UR is a 3P3T(Triple Pole Triple Throw) switch and suitable for wireless communication systems,
for example, W-CDMA handsets.
This IC has on-chip logic for operation with 3 CMOS control inputs.
Low insertion loss and on-chip logic circuit are realized by the Sony JPHEMT process.
(Applications: Antenna switch for cellular handsets, triple band W-CDMA)
Features
‹ Low insertion loss: [email protected]
‹ 3 CMOS compatible control line
Package
Small package size: 20-pin UQFN
Structure
GaAs JPHEMT MMIC
Absolute Maximum Ratings
(Ta = 25°C)
Š Bias voltage
VDD
7
V
Š Control voltage
Vctl
5
V
Š Operating temperature
Topr
–35 to +85
°C
Š Storage temperature
Tstg
–65 to +150
°C
This IC is ESD sensitive device. Special handling precautions are required.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license
by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating
the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E06133
CXG1214UR
20
F12
ANT2
19
18
17
RF2 (Band3)
GND
CRF
CRF
EXT
GND4
GND3
Block Diagram and Recommended Circuit
16
F13
F8
1
F4
CRF
15
F3
GND
2
RF3 (Band1)
14
F6
GND2 (Band 3)
F11
CRF
F9
F5
3
GND
13
GND
F2
GND1(Band1)
F10
4
RF1 (Band6)
F1
12
CRF
F7
ANT1
5
11
GND
CRF
9
10
Cbypass
(100pF)
VDD
CTLC
8
CTLB
7
CTLA
GND
6
When using this IC, the following external components should be used:
CRF: This capacitor is used for RF decoupling and must be used for all applications.
Cbypass: This capacitor is used for DC line filtering.
Truth Table
State CTLA CTLB CTLC
ON path
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10 F11 F12 F13
1
H
L
H
RF1 – ANT1 ON OFF OFF OFF OFF OFF OFF ON ON OFF OFF ON ON
2
L
H
H
RF2 – ANT2 OFF OFF ON OFF OFF OFF ON OFF ON OFF ON OFF ON
3
L
L
H
RF3 – ANT2 OFF OFF OFF OFF ON OFF ON ON OFF ON OFF OFF ON
4
H
L
L
RF1 – EXT OFF ON OFF OFF OFF OFF OFF ON ON OFF ON ON OFF
5
L
H
L
RF2 – EXT OFF OFF OFF ON OFF OFF ON OFF ON OFF ON ON OFF
6
L
L
L
RF3 – EXT OFF OFF OFF OFF OFF ON ON ON OFF ON ON ON OFF
DC Bias Conditions
(Ta = 25°C)
Item
Min.
Typ.
Max.
Unit
Vctl (H)
2.2
2.85
3.2
V
Vctl (L)
0
—
0.4
V
2.6
2.85
3.2
V
VDD
-2-
CXG1214UR
Electrical Characteristics
(Ta = 25°C)
Item
Insertion loss
Symbol
State
Path
1
2
3
RF1 – ANT1
RF2 – ANT2
RF3 – ANT2
IL
4
5
6
4
5
6
1
Isolation
Condition
RF1 – EXT
RF2 – EXT
RF3 – EXT
RF1 – ANT1
RF2 – ANT2
RF3 – ANT2
RF1 – EXT
ISO
2
3
RF2 – EXT
RF3 – EXT
Min.
Typ.
Max.
Unit
830 to 885MHz
0.35
0.50
dB
1749.9 to 1880MHz
0.45
0.65
dB
1920 to 1980MHz
0.47
0.67
dB
2110 to 2170MHz
0.50
0.75
dB
830 to 885MHz
0.40
0.55
dB
1749.9 to 1880MHz
0.53
0.73
dB
1920 to 1980MHz
0.55
0.75
dB
2110 to 2170MHz
0.60
0.85
dB
830 to 885MHz
25
35
dB
1749.9 to 1880MHz
20
30
dB
1920 to 2170MHz
20
30
dB
830 to 885MHz
25
35
dB
1749.9 to 1880MHz
20
30
dB
1920 to 2170MHz
20
30
dB
830 to 885MHz
20
27
dB
1749.9 to 1880MHz
17
23
dB
1920 to 2170MHz
15
21
dB
830 to 885MHz
20
30
dB
1749.9 to 1880MHz
20
27
dB
1920 to 2170MHz
19
25
dB
VSWR
VSWR
Switching
speed
TSW
1dB
compression
input power
P1dB
VDD = 2.85V
ACLR1
±5MHz, 3.84MHz BW*1
–50
dBc
ACLR2
±10MHz, 3.84MHz BW*1
–55
dBc
2fo
*1
–45
dBm
3fo
*1
–45
dBm
Bias current
Idd
VDD = 2.85V
200
330
μA
Control current
Ictl
Vctl(H) = 2.85V
30
50
μA
ACLR
Harmonics
*1
50Ω
1.2
5
10
32
dBm
Pin = 25dBm, 0/2.85V control, VDD = 2.85V, 830 to 840MHz, 1749.9 to 1785MHz, 1920 to 1980MHz,
Mesurement system noise level : ACLR(±5MHz) <–60dBc, (±10MHz) <–65dBc, 2nd Harmonics <–75dBm,
3rd Harmonics <–75dBm
-3-
CXG1214UR
Package Outline
(Unit: mm)
20PIN UQFN (PLASTIC)
x4
0.1
S
C
A-B
0.4 ± 0.1
1.3
0.55 ± 0.05
2.7
4-R0.3
15
C
11
10
20
6
A
B
2.7
16
26
0.14
1
0.
5
0.4
PIN 1 INDEX
0.18
0.07
0.25
0.05 M
S
C
A-B
0.05
S
MAX0.02
S
Solder Plating
+ 0.09
0.25 – 0.03
+ 0.09
0.14 – 0.03
S
TERMINAL SECTION
PACKAGE STRUCTURE
Note:Cutting burr of lead are 0.05mm MAX.
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LEAD MATERIAL
COPPER ALLOY
JEDEC CODE
PACKAGE MASS
0.02g
SONY CODE
UQFN-20P-01
LEAD PLATING SPECIFICATIONS
ITEM
-4-
SPEC.
LEAD MATERIAL
COPPER ALLOY
SOLDER COMPOSITION
Sn-Bi Bi:1-4wt%
PLATING THICKNESS
5-18µm
Sony Corporation