TS3V712EL www.ti.com SCDS303A – AUGUST 2010 – REVISED SEPTEMBER 2010 7-CHANNEL VIDEO SWITCH WITH INTEGRATED LEVEL SHIFTERS Check for Samples: TS3V712EL FEATURES APPLICATIONS • • • • • 29 28 30 VDD GND SEL VDD GND 3 25 4 24 5 23 GND 6 22 7 21 8 20 9 19 10 18 11 17 H1 H2 V1 V2 VDD R1 R2 G1 G2 B1 B2 16 • 27 26 15 • 1 2 14 • H0 V0 GND VDD R0 G0 B0 N.C. SCL0 SDA0 GND 31 • • RTG PACKAGE (TOP VIEW) 32 • 12 • Notebook Computers Docking Stations KVM Switches 13 Supports 7-Channel VGA Signals (R, G, B, HSYNC, VSYNC, DDC CLK, and DDC DAT) Integrated Level-Shifting Buffers for HSYNC and VSYNC Channels Operating Voltage – VDD = 3.3 V ±10% – VDD_5 = 5 V ±10% High Bandwidth of 1.3 GHz (–3 dB) Low ON-State Resistance and Input/Output Capacitance – rON = 4 Ω (Typ) – CON = 8 pF (Typ) Voltage Clamping NMOS Switches for SCL and SDA Channels ESD Performance (Pins 12–15, 17–22, 24–27) – ±2-kV Contact Discharge (IEC61000-4-2) – 7-kV Human Body Model (to GND) ESD Performance (All Pins) – 3-kV Human Body Model (JESD22-A114E) 32-Pin Quad Flat Pack No-Lead [QFN (RTG)] Package SCL1 SCL2 SDA1 SDA2 VDD_5 1 The exposed center pad must be connected to GND. DESCRIPTION/ORDERING INFORMATION The TS3V712EL is a high bandwidth, 7-channel video demultiplexer for switching between a single VGA source and one of two end points. The device is designed for ensuring video signal integrity and minimizing video signal attenuation by providing high bandwidth of 1.3 GHz. The TS3V712EL has integrated level shifting buffers for the HSYNC and VSYNC signals which provide voltage level translation between 3.3 V and 5 V logic. The SCL and SDA lines use NMOS switches which clamp the output voltage to 1 V below VDD. The video signals are protected against ESD with integrated diodes to VDD and GND that support levels up to ±2-kV Contact Discharge (IEC61000-4-2) and 7-kV Human Body Model (JESD22-A114E). ORDERING INFORMATION (1) TA –40°C to 85°C (1) (2) PACKAGE QFN – RTG (2) Tape and reel ORDERABLE PART NUMBER TS3V712ELRTGR TOP-SIDE MARKING TF712EL For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TS3V712EL SCDS303A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com TYPICAL APPLICATION DIAGRAM 3.3V 5V 0.1 mF 0.1 mF 2.2 k 2 .2 k VDD R GPU G B R0 VSYNC VGA Connector G0 B0 VDD_5 H1 V1 R1 G1 B1 SCL1 SDA1 H0 V0 HSYNC 2.2 k 2.2 k TS3V712EL SDA SCL0 SCL SDA0 GPIO SEL 2.2 k 2.2 k H2 V2 R2 G2 B2 SCL2 SDA2 GND Docking Station Connector 2 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TS3V712EL TS3V712EL www.ti.com SCDS303A – AUGUST 2010 – REVISED SEPTEMBER 2010 LOGIC DIAGRAM VDD_5 (See Note A) H0 H1 V0 V1 H2 V2 R0 R1 G0 G1 B0 B1 R2 G2 B2 (See Note B) SCL0 SCL1 SDA0 SDA1 SCL2 SDA2 SEL A. Supply for HSYNC and VSYNC translators B. Output clamped to VDD – 1 V Control Logic FUNCTION TABLE FUNCTION SEL R0, G0, B0, H0, V0, SCL0, SDA0 Hi-Z L R1, G1, B1, H1, V1, SCL1, SDA1 R2, G2, B2, H2, V2, SCL2, SDA2 H R2, G2, B2, H2, V2, SCL2, SDA2 R1, G1, B1, H1, V1, SCL1, SDA1 3 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TS3V712EL TS3V712EL SCDS303A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VDD VDD_5 Supply voltage range MIN MAX –0.5 4.6 –0.5 6.5 UNIT V VI/O Analog voltage range (2) (3) R, G, B, SCL, SDA –0.5 VDD + 0.5 VIN Digital input voltage range (2) (3) SEL, H, V –0.5 6.5 V II/OK Analog port diode current VI/O < 0 V –50 mA IIK Digital input clamp current VIN < 0 V II/O ON-state switch current R, G, B, SCL, SDA IDD IGND Continuous current through VDD or GND qJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) V –50 mA –128 128 mA –100 100 mA 39.2 °C/W 150 °C RTG package (4) –65 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to ground, unless otherwise specified. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-1. RECOMMENDED OPERATING CONDITIONS (1) MIN MAX 3 3.6 UNIT V 4.5 5.5 V SEL, H, V 0 5.5 V SEL, H, V 2 VDD Supply voltage VDD_5 Supply voltage for H and V channels VIN Digital control input voltage VIH High-level control input voltage VIL Low-level control input voltage SEL, H, V 0.8 V IOH High-level output current H, V –8 mA IOL Low-level output current H, V 8 mA TA Operating free-air temperature 85 °C (1) –40 V All unused control inputs of the device must be held at VDD or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TS3V712EL TS3V712EL www.ti.com SCDS303A – AUGUST 2010 – REVISED SEPTEMBER 2010 ELECTRICAL CHARACTERISTICS (1) over recommended operating free-air temperature range, VDD = 3.3 V ±0.3 V, VDD_5 = 5 V ±0.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN V 3 6 4 9 rON(fl ON-state resistance flatness (3) R, G, B VDD = 3.6 V, VDD_5 = 5.5 V, VI/O = 1.5 V and VDD, II/O = –40 mA 0.2 1 Ω ΔrON ON-state resistance match between channels (4) R, G, B VDD = 3.6 V, VDD_5 = 5.5 V, 0 V ≤ VI/O ≤ VDD, II/O = –40 mA 0.2 1 Ω IIH Digital input high leakage current SEL, H, V VDD = 3.6 V, VDD_5 = 5.5 V, VIN = VDD ±1 mA IIL Digital input low leakage current SEL, H, V VDD = 3.6 V, VDD_5 = 5.5 V, VIN = GND ±1 mA IOFF Leakage under power off conditions All outputs VDD = 0 V, VDD_5 = 0 V, VI/O = 0 to 3.6 V, ±1 mA CIN Digital input capacitance SEL, H, V f = 10 MHz VIN = 0, COFF Switch OFF capacitance R, G, B f = 10 MHz VI/O = 0 V, Output open, Switch OFF 3 CON Switch ON capacitance R, G, B f = 10 MHz VI/O = 0 V, Output open, Switch ON 8 VOH High-level output voltage H, V VIN = VIH, IOH = –8 mA VOL Low-level output voltage H, V VIN = VIH, IOL = 8 mA VHYS Voltage hysteresis H, V SCL, SDA SCL, SDA II/O = –40 mA –1.2 ON-state resistance at) 0 V ≤ VI/O ≤ VDD, –0.8 rON SCL, SDA VDD = 3.6 V, VDD_5 = 5.5 V, UNIT VIK R, G, B IIN = –18 mA MAX Digital input clamp voltage SEL, H, V VDD = 3.6 V, VDD_5 = 5.5 V, TYP (2) VIN = 0 to 5.5 V 4 Ω pF pF 3 pF 8 3.8 V 0.5 V 200 300 mV 200 500 mA 50 mA T IDD VDD supply current IDD_5 VDD_5 supply current (1) (2) (3) (4) VDD = 3.6 V, VDD_5 = 5.5 V, VIN = VDD or GND, II/O = 0 mA, VDD = 3.6 V, VDD_5 = 5.5 V, VIN = VDD or GND, II/O = 0 mA, VI, VO, II, and IO refer to I/O pins. VIN refers to the control inputs. All typical values are at VDD = 3.3V, VDD_5 = 5V (unless otherwise noted), TA = 25°C. rON(flat) is the difference of rON in a given channel at specified voltages. ΔrON is the difference of rON from center port to any other ports. SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, VDD = 3.3 V ±0.3 V, VDD_5 = 5 V ±0.5 V (unless otherwise noted) PARAMETER tpd (1) tPHZ, tPLZ (1) (2) (2) FROM (INPUT) TO (OUTPUT) R0,G0,B0 R1, G1, B1 or R2, G2, B2 0.25 SCL0, SDA0 SCL1, SDA1 or SCL2, SDA2 0.25 H0,V0 H1, V1 or H2, V2 SEL R1, G1, B1, SCL1, SDA1 or R2, G2, B2, SCL2, SDA2 0.5 11 SEL H1, V1 or H2, V2 0.5 13 MIN TYP 3 MAX UNIT ns 7 ns The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance when driven by an ideal voltage source (zero output impedance). Line disable time: SEL to input, output; also called SEL to switch turn off time. 5 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TS3V712EL TS3V712EL SCDS303A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com SWITCHING CHARACTERISTICS (continued) over recommended operating free-air temperature range, VDD = 3.3 V ±0.3 V, VDD_5 = 5 V ±0.5 V (unless otherwise noted) PARAMETER tPZH, tPZL (3) (4) (5) (3) FROM (INPUT) TO (OUTPUT) MIN SEL R1, G1, B1, SCL1, SDA1 or R2, G2, B2, SCL2, SDA2 0.5 11 SEL H1, V1 or H2, V2 0.5 13 TYP MAX UNIT ns tsk(o) (4) R, G, B 0.05 0.1 ns tsk(p) (5) R, G, B 0.05 0.1 ns Line enable time: SEL to input, output; also called SEL to switch turn on time. Output skew between center channel to any other channel. Skew between opposite transitions of the same output. |tPHL – tPLH| DYNAMIC CHARACTERISTICS over recommended operating free-air temperature range, VDD = 3.3 V ±0.3 V, VDD_5 = 5 V ±0.5 V (unless otherwise noted) PARAMETER (1) TEST CONDITIONS TYP (1) UNIT XTALK R, G, B RL = 50 Ω, f = 250 MHz, –47 OIRR R, G, B RL = 50 Ω, f = 250 MHz, –38 dB BW R, G, B RL = 50 Ω, Switch ON 1.3 GHz dB All typical values are at VDD = 3.3 V, VDD_5 = 5 V (unless otherwise noted), TA = 25°C. 6 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TS3V712EL TS3V712EL www.ti.com SCDS303A – AUGUST 2010 – REVISED SEPTEMBER 2010 TYPICAL CHARACTERISTICS Off Isolation Insertion Loss -20 -1 -30 Attenuation - dB Gain - dB -2 -3 -4 -5 -40 -50 -60 -6 -70 -7 -80 -8 1 10 100 1k f - Frequency - MHz -90 10k 1 Figure 1. Gain vs Frequency 10 100 1k f - Frequency - MHz 10k Figure 2. Off Isolation vs Frequency R,G,B Switches Crosstalk 2.8 -35 2.7 -45 RON - W Attenuation - dB 2.6 -55 -65 2.5 2.4 -75 2.3 -85 2.2 -95 -105 1 10 100 1k f - Frequency - MHz 10k 2.1 0.02 0.62 1.22 1.82 2.42 3.02 3.62 VO - Output Voltage - V Figure 3. Crosstalk vs Frequency Figure 4. RON vs VOUT 7 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TS3V712EL TS3V712EL SCDS303A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) SCL, SDA Switches 40 3.5 30 3 VO - Output Voltage - V 35 RON - W 25 20 15 2.5 2 1.5 1 10 VOUT - V 0.5 5 0 0.12 R, G, B Switches 4 0.57 1.02 0 0.12 1.47 1.92 2.37 2.82 3.27 3.57 VI - Input Voltage - V 0.57 1.02 Figure 5. RON vs VIN Figure 6. VOUT vs VIN SCL, SDA Switches H, V Switches 6 2.5 5 VO - Output Voltage - V VO - Output Voltage - V 2 1.5 1 0.5 0 0.12 1.47 1.92 2.37 2.82 3.27 3.57 VI - Input Voltage - V 4 3 2 1 0.57 1.02 1.47 1.92 2.37 2.82 3.27 3.57 VI - Input Voltage - V 0 0.1 0.5 Figure 7. VOUT vs VIN 1 1.4 1.9 2.3 VI - Input Voltage - V 2.8 3.2 3.5 Figure 8. VOUT vs VIN 8 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TS3V712EL TS3V712EL www.ti.com SCDS303A – AUGUST 2010 – REVISED SEPTEMBER 2010 PARAMETER MEASUREMENT INFORMATION (Enable and Disable Times) VDD Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT DUT 2 × VDD Input Generator Open GND 50 Ω CL (see Note A) 50 Ω VG2 TEST RL VO VI S1 VDD VDD_5 RL S1 RL Vin CL V∆ 200 Ω or 1 kΩ* GND 10 pF 0.3 V VDD 10 pF 0.3 V t PLZ/t PZL 5 V± 0.5 V 3.3 V± 0.3 V 2 × VDD t PHZ/t PZH 5 V± 0.5 V 3.3 V± 0.3 V GND *RL = 200 Ω applies to all switch outputs RL = 1 kΩ applies to all buffer outputs VI VO VDD Output Control (VIN) VDD/2 VDD/2 0V Output Waveform 1 S1 at 2 x VDD (see Note B) t PZL t PLZ VOH VDD/2 VOL +10% t PZH VO Output Waveform 2 S1 at GND (see Note B) VOL t PHZ VDD/2 VOH -10% VOH VOL VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low , except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. Figure 9. Test Circuit and Voltage Waveforms 9 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TS3V712EL TS3V712EL SCDS303A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION (Propagation Delay and Skew) VDD Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT DUT 2 × VDD Input Generator RL VO VI S1 Open GND 50 Ω CL (see Note A) 50 Ω VG2 RL TEST VDD VDD_5 S1 RL Vin CL t sk(o) 3.3 V ± 0.3 V 5 V ± 0.5 V Open VDD or GND 10 pF t sk(p) 3.3 V ± 0.3 V 5 V ± 0.5 V Open 200 Ω* or 1 kΩ VDD or GND 10 pF *RL = 200 Ω applies to all switch outputs RL = 1 kΩ applies to all buffer outputs (1) VI VDD VDD/2 0V Data In at Ax or A y t PLHx VO t PHLx VOH (VOH + VOL)/2 VOL Data Out at XB 1 or XB 2 t sk(o) VO (1) VDD VDD/2 0V Input t sk(o) VOH (VOH + VOL)/2 VOL Data Out at YB 1 or YB 2 t PLHy t PHLy t PLH VOH (VOH + VOL)/2 VOL Output t sk(o) = t PLHy − tPLHx or t PHLy − tPHLx VOLTAGE WAVEFORMS OUTPUT SKEW (t sk(o)) t PHL t sk(p) = t PHL − tPLH VOLTAGE WAVEFORMS PULSE SKEW [t sk(p)] NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low , except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. (1) 2 V ± 0.2 V for SCL, SDA Figure 10. Test Circuit and Voltage Waveforms 10 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TS3V712EL TS3V712EL www.ti.com SCDS303A – AUGUST 2010 – REVISED SEPTEMBER 2010 PARAMETER MEASUREMENT INFORMATION EXT TRIGGER BIAS VBIAS Network Analyzer (HP8753ES) P1 P2 VDD 0B 1 A0 SEL DUT CL = 10 pF (see Note A) VSEL A. CL includes probe and jig capacitance. Figure 11. Test Circuit for Frequency Response (BW) Frequency response is measured at the output of the ON channel. For example, when VSEL = 0 and A0 is the input, the output is measured at 0B1. All unused analog I/O ports are left open. HP8753ES Setup Average = 4 RBW = 3 kHz VBIAS = 0.35 V ST = 2 s P1 = 0 dBM 11 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TS3V712EL TS3V712EL SCDS303A – AUGUST 2010 – REVISED SEPTEMBER 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) EXT TRIGGER BIAS VBIAS Network Analyzer (HP8753ES) P1 P2 VDD A0 0B 1 RL = 50 Ω A1 1B 1 0B 2 DUT A2 1B 2 2B 1 RL = 50 Ω A3 3B 1 2B 2 3B 2 SEL VSEL A. CL includes probe and jig capacitance. B. A 50-Ω termination resistor is needed to match the loading of the network analyzer. Figure 12. Test Circuit for Crosstalk (XTALK) Crosstalk is measured at the output of the nonadjacent ON channel. For example, when VSEL = 0 and A1 is the input, the output is measured at A3 . All unused analog input (A) ports are connected to GND, and the output (B) ports are left open. HP8753ES Setup Average = 4 RBW = 3 kHz VBIAS = 0.35 V ST = 2 s P1 = 0 dBM 12 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TS3V712EL TS3V712EL www.ti.com SCDS303A – AUGUST 2010 – REVISED SEPTEMBER 2010 PARAMETER MEASUREMENT INFORMATION (continued) EXT TRIGGER BIAS VBIAS Network Analyzer (HP8753ES) P1 P2 VDD A0 0B 1 RL = 50 Ω A1 1B 1 DUT 0B 2 1B 2 SEL VSEL A. CL includes probe and jig capacitance. B. A 50-Ω termination resistor is needed to match the loading of the network analyzer. Figure 13. Test Circuit for Off Isolation (OIRR) Off isolation is measured at the output of the OFF channel. For example, when VSEL = GND and As is the input, the output is measured at 1B2 . All unused analog input (A) ports are connected to GND, and the output (B) ports are left open. HP8753ES Setup Average = 4 RBW = 3 kHz VBIAS = 0.35 V ST = 2 s P1 = 0 dBM 13 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TS3V712EL PACKAGE OPTION ADDENDUM www.ti.com 17-Sep-2010 PACKAGING INFORMATION Orderable Device TS3V712ELRTGR Status (1) ACTIVE Package Type Package Drawing WQFN RTG Pins Package Qty 32 3000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) Request Free Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TS3V712ELRTGR Package Package Pins Type Drawing WQFN RTG 32 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 16.4 Pack Materials-Page 1 3.3 B0 (mm) K0 (mm) P1 (mm) 6.3 1.0 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TS3V712ELRTGR WQFN RTG 32 3000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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