TPIC5423L 4-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS045 – NOVEMBER 1994 • • • • • • Low rDS(on) . . . 0.32 Ω Typ Voltage Output . . . 60 V Input Protection Circuitry . . . 18 V Pulsed Current . . . 4 A Per Channel Extended ESD Capability . . . 4000 V Direct Logic-Level Interface DW PACKAGE (TOP VIEW) DRAIN1 DRAIN1 GATE1 GND SOURCE1 SOURCE1 SOURCE2 SOURCE2 GND GATE2 DRAIN2 DRAIN2 description The TPIC5423L is a monolithic gate-protected logic-level power DMOS array that consists of four electrically isolated independent N-channel enhancement-mode DMOS transistors. Each transistor features integrated high-current zener diodes (ZCXa and ZCXb) to prevent gate damage in the event that an overstress condition occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using the humanbody model of a 100-pF capacitor in series with a 1.5-kΩ resistor. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 DRAIN3 DRAIN3 GATE3 GND SOURCE3 SOURCE3 SOURCE4 SOURCE4 GND GATE4 DRAIN4 DRAIN4 The TPIC5423L is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation over the case temperature of – 40°C to 125°C. schematic DRAIN1 1, 2 23, 24 Q3 Q1 GATE1 D1 3 DRAIN2 5, 6 D3 22 Z3 Z1 ZC1b SOURCE1 ZC1a ZC3a SOURCE2 11, 12 SOURCE3 DRAIN4 Q4 10 7, 8 19, 20 13, 14 15 ZC2b GATE3 ZC3b Q2 GATE2 DRAIN3 Z2 D2 D4 Z4 ZC4a ZC2a GATE4 ZC4b 17, 18 SOURCE4 4, 9, 16, 21 GND NOTE A: For correct operation, no terminal may be taken below GND. Copyright 1994, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1 TPIC5423L 4-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS045 – NOVEMBER 1994 absolute maximum ratings over operating case temperature range (unless otherwise noted)† Drain-to-source voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V Source-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V Drain-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V Gate-to-source voltage range, VGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 9 V to 18 V Continuous drain current, each output, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 A Continuous source-to-drain diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 A Pulsed drain current, each output, Imax, TC = 25°C (see Note 1 and Figure 15) . . . . . . . . . . . . . . . . . . . . . 4 A Continuous gate-to-source zener-diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Pulsed gate-to-source zener-diode current, TC = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 500 mA Single-pulse avalanche energy, EAS, TC = 25°C (see Figures 4 and 16) . . . . . . . . . . . . . . . . . . . . . . . . 96 mJ Continuous total dissipation, TC = 25°C (see Figure 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.39 W Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Pulse duration = 10 ms, duty cycle = 2% 2–2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TPIC5423L 4-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS045 – NOVEMBER 1994 electrical characteristics, TC = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS ID = 250 µA, ID = 1 mA, See Figure 5 TYP MAX Drain-to-source breakdown voltage VGS(th) Gate-to-source threshold voltage V(BR)GS V(BR)SG Gate-to-source breakdown voltage Source-to-gate breakdown voltage IGS = 250 µA ISG = 250 µA V(BR) Reverse drain-to-GND breakdown voltage Drain-to-GND current = 250 µA VDS(on) Drain-to-source on-state voltage ID = 1.25 A, See Notes 2 and 3 VF(SD) Forward on-state voltage, source-to-drain IS = 1.25 A, VGS = 0 (Z1, Z2, Z3, Z4), See Notes 2 and 3 and Figure 12 VF Forward on-state voltage, GND-to-drain ID = 1.25 A (D1, D2, D3, D4), See Notes 2 and 3 IDSS Zero gate voltage drain current Zero-gate-voltage VDS = 48 V,, VGS = 0 TC = 25°C TC = 125°C IGSSF IGSSR Forward-gate current, drain short circuited to source VGS = 15 V, VSG = 5 V, VDS = 0 VDS = 0 Leakage current, current drain-to-GND drain to GND VDGND = 48 V TC = 25°C TC = 125°C 0.5 10 TC = 25°C 0.32 0.375 drain to source on-state on state resistance Static drain-to-source VGS = 5 V, ID = 1.25 A,, See Notes 2 and 3 and Figures 6 and 7 TC = 125°C 0.44 0.55 Ilk lkg rDS( DS(on)) Reverse-gate current, drain short circuited to source VGS = 0 VDS = VGS, MIN V(BR)DSX Forward transconductance Ciss Short-circuit input capacitance, common source Coss Short-circuit output capacitance, common source Crss Short-circuit reverse-transfer capacitance, common source VDS = 25 V, f = 1 MHz, 1.5 UNIT V 1.75 2.2 V 18 V 9 V 100 V VGS = 5 V, VDS = 15 V, ID = 0.625 A, See Notes 2 and 3 and Figure 9 gfs 60 0.4 0.47 V 0.9 1.1 V 2 V 0.05 1 0.5 10 20 200 nA 10 100 nA 0.05 1 µA µA Ω 1.25 VGS = 0, See Figure 11 1.63 S 200 250 100 125 60 75 pF F NOTES: 2. Technique should limit TJ – TC to 10°C maximum. 3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. source-to-drain and GND-to-drain diode characteristics, TC = 25°C PARAMETER trr Reverse recovery time Reverse-recovery QRR Total diode charge TEST CONDITIONS IS = 0.625 A, VDS = 48 V, VGS = 0, di/dt = 100 A/µs, 0 A/µs See Figures 1 and 14 POST OFFICE BOX 655303 MIN TYP Z1, Z2, Z3, and Z4 80 D1, D2, D3, and D4 130 Z1, Z2, Z3, and Z4 0.8 D1, D2, D3, and D4 0.66 • DALLAS, TEXAS 75265 MAX UNIT ns µC 2–3 TPIC5423L 4-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS045 – NOVEMBER 1994 resistive-load switching characteristics, TC = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX 34 70 20 40 28 55 15 30 td(on) td(off) Turn-on delay time tr tf Rise time Qg Total gate charge Qgs(th) Threshold gate-to-source charge Qgd Gate-to-drain charge LD Internal drain inductance 5 LS Internal source inductance 5 Rg Internal gate resistance Turn-off delay time RL = 40 Ω, See Figure 2 VDD = 25 V, tdis = 10 ns, ten = 10 ns, Fall time VDS = 48 V, V See Figure 3 ID = 0.625 0 625 A, A VGS = 5 V, V 6.6 8 0.5 0.6 2.6 3.2 UNIT ns nC nH Ω 0.25 thermal resistance PARAMETER TEST CONDITIONS MIN TYP RθJA Junction-to-ambient thermal resistance See Notes 4 and 7 90 RθJB Junction-to-board thermal resistance See Notes 5 and 7 49 RθJP Junction-to-pin thermal resistance See Notes 6 and 7 NOTES: 4. Package mounted on an FR4 printed-circuit board with no heatsink. 5. Package mounted on a 24 in2, 4-layer FR4 printed-circuit board. 6. Package mounted in intimate contact with infinite heatsink. 7. All outputs with equal power. 28 PARAMETER MEASUREMENT INFORMATION 1 Reverse di/dt = 100 A/µs I S – Source-to-Drain Diode Current – A 0.5 0 – 0.5 25% of IRM† –1 Shaded Area = QRR – 1.5 –2 – 2.5 VDS = 48 V VGS = 0 TJ = 25°C Z1 – Z4‡ IRM† trr(SD) –3 0 50 100 150 200 250 300 Time – ns 350 400 450 500 † IRM = maximum recovery current ‡ The above waveform is representative of D1, D2, D3, and D4 in shape only. Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode 2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT °C/W TPIC5423L 4-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS045 – NOVEMBER 1994 VDD = 25 V RL Pulse Generator ten VDS 5V VGS VGS 0V DUT Rgen tdis 50 Ω td(off) td(on) CL = 30 pF (see Note A) 50 Ω tr tf VDD VDS VDS(on) VOLTAGE WAVEFORMS TEST CIRCUIT NOTE A: CL includes probe and jig capacitance. Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms Current Regulator 12 V Battery 0.2 µF Qg Same Type as DUT 50 kΩ 5V 0.3 µF Qgs(th) VDD VDS 0 VGS Gate Voltage DUT IG = 100 µA Qgd Time VOLTAGE WAVEFORM IG CurrentSampling Resistor ID CurrentSampling Resistor TEST CIRCUIT Figure 3. Gate-Charge Test Circuit and Voltage Waveform POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–5 TPIC5423L 4-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS045 – NOVEMBER 1994 PARAMETER MEASUREMENT INFORMATION VDD = 25 V tav tw 7 mH Pulse Generator (see Note A) ID 5V VDS VGS 0V IAS (see Note B) VGS 50 Ω ID DUT 0V Rgen 50 Ω V(BR)DSX = 60 V Min VDS 0V VOLTAGE AND CURRENT WAVEFORMS TEST CIRCUIT NOTES: A. The pulse generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω. B. Input pulse duration (tw) is increased until peak current IAS = 4 A. I V t av AS (BR)DSX Energy test level is defined as E 96 mJ. AS 2 + + Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms TYPICAL CHARACTERISTICS STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 2.5 1 VDS = VGS ID = 1.25 A ID = 1 mA 1.5 ID = 100 µA 1 0.5 0 – 40 – 20 0 20 40 60 80 100 120 140 160 0.8 On-State Resistance – Ω 2 r DS(on) – Static Drain-to-Source VGS(th) – Gate-to-Source Threshold Voltage – V GATE-TO-SOURCE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 0.6 VGS = 5 V 0.2 0 – 40 – 20 0 20 40 60 Figure 5 Figure 6 POST OFFICE BOX 655303 80 100 120 140 160 TJ – Junction Temperature – °C TJ – Junction Temperature – °C 2–6 VGS = 4.5 V 0.4 • DALLAS, TEXAS 75265 TPIC5423L 4-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS045 – NOVEMBER 1994 TYPICAL CHARACTERISTICS STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 4 TJ = 25°C VGS = 4 V 0.6 3 I D – Drain Current – A On-State Resistance – Ω r DS(on) – Static Drain-to-Source 1 0.9 0.8 0.7 DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE 0.5 0.4 VGS = 4.5 V 0.3 VGS = 5 V 0.2 nVGS = 0.2 V TJ = 25°C 2 VGS = 3 V 1 0.1 1 0 10 0 1 2 3 4 5 6 7 8 9 VDS – Drain-to-Source Voltage – V ID – Drain Current – A Figure 7 Figure 8 DRAIN CURRENT vs GATE-TO-SOURCE VOLTAGE DISTRIBUTION OF FORWARD TRANSCONDUCTANCE 60 45 TJ = 75°C 35 30 25 20 15 2 1 TJ = 150°C 10 TJ = 125°C 1.740 1.715 1.690 1.665 1.640 1.615 1.590 1.565 1.540 5 0 TJ = – 40°C TJ = 25°C 3 40 1.515 Percentage of Units – % 50 4 Total Number of Units = 1040 VDS = 15 V ID = 0.625 A TJ = 25°C I D – Drain Current – A 55 10 0 1 2 3 4 5 VGS – Gate-to-Source Voltage – V gfs – Forward Transconductance – S Figure 9 Figure 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–7 TPIC5423L 4-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS045 – NOVEMBER 1994 TYPICAL CHARACTERISTICS SOURCE-TO-DRAIN DIODE CURRENT vs SOURCE-TO-DRAIN VOLTAGE CAPACITANCE vs DRAIN-TO-SOURCE VOLTAGE 400 10 360 Capacitance – pF 320 280 240 I SD – Source-to-Drain Diode Current – A VGS = 0 f = 1 MHz TJ = 25°C CisS(0) = 301 pF Coss(0) = 384 pF Crss(0) = 144 pF Ciss 200 160 120 Coss 80 Crss VGS = 0 6 4 2 1 0.6 TJ = – 40°C TJ = 125°C 0.4 TJ = 150°C TJ = 25°C 0.2 40 TJ = 75°C 0 0.1 0 4 8 12 16 20 24 28 32 36 40 0.1 VDS – Drain-to-Source Voltage – V 1 VSD – Source-to-Drain Voltage – V Figure 11 Figure 12 DRAIN-TO-SOURCE VOLTAGE AND GATE-TO-SOURCE VOLTAGE vs GATE CHARGE REVERSE-RECOVERY TIME vs REVERSE di/dt 50 12 150 10 125 VDD = 20 V VDD = 30 V 40 8 30 6 20 4 VDD = 48 V 10 2 trr – Reverse-Recovery Time – ns ID = 0.625 A TJ = 25°C See Figure 3 VGS – Gate-to-Source Voltage – V VDS – Drain-to-Source Voltage – V 60 10 VDS = 48 V VGS = 0 IS = 0.625 A TJ = 25°C See Figure 1 100 75 D1, D2, D3, and D4 50 Z1, Z2, Z3, and Z4 25 VDD = 20 V 0 0 1 2 3 4 5 6 7 0 0 0 200 300 400 Reverse di/dt – A/µs Qg – Gate Charge – nC Figure 13 2–8 100 Figure 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 500 600 TPIC5423L 4-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS045 – NOVEMBER 1994 THERMAL INFORMATION MAXIMUM DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE 10 I D – Maximum Drain Current – A TC = 25°C 1 µs† 10 ms† 1 ms† 500 µs† 1 ÁÁ ÁÁ θJP§ θJA‡ DC Conditions 0.1 0.1 1 10 VDS – Drain-to-Source Voltage – V 100 † Less than 2% duty cycle ‡ Device mounted on FR4 printed-circuit board with no heatsink. § Device mounted in intimate contact with infinite heatsink. Figure 15 MAXIMUM PEAK AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE I AS – Maximum Peak Avalanche Current – A 10 See Figure 4 TC = 25°C TC = 125°C 1 0.01 0.1 1 10 100 tav – Time Duration of Avalanche – ms Figure 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–9 TPIC5423L 4-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY SLIS045 – NOVEMBER 1994 THERMAL INFORMATION DW PACKAGE† JUNCTION-TO-BOARD THERMAL RESISTANCE vs PULSE DURATION 100 DC Conditions RθJB – Junction-to-Board Thermal Resistance – °C/W d = 0.5 d = 0.2 10 d = 0.1 d = 0.05 d = 0.02 1 d = 0.01 tc Single Pulse tw ID 0 0.1 0.0001 0.001 0.01 0.1 tw – Pulse Duration – s † Device mounted on 24 in2, 4-layer FR4 printed-circuit board with no heatsink. NOTE A: ZθB(t) = r(t) RθJB tw = pulse duration tc = cycle time d = duty cycle = tw / tc Figure 17 2–10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 10 100 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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