TI LMZ12001EXTTZX

LMZ12001EXT
1A SIMPLE SWITCHER® Power Module with 20V Maximum Input
Voltage for Military and Rugged Applications
Easy To Use 7 Pin Package
Performance Benefits
● Low radiated emissions / High radiated immunity
● Passes vibration standard
MIL-STD-883 Method 2007.2 Condition A
JESD22–B103B Condition 1
● Passes drop standard
MIL-STD-883 Method 2002.3 Condition B
JESD22–B110 Condition B
System Performance
30117386
TO-PMOD 7 Pin Package
10.16 x 13.77 x 4.57 mm (0.4 x 0.542 x 0.18 in)
θJA = 20°C/W, θJC = 1.9°C/W
RoHS Compliant
Efficiency VIN = 12V VOUT = 5.0V
Electrical Specifications
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6W maximum total power output
Up to 1A output current
Input voltage range 4.5V to 20V
Output voltage range 0.8V to 6V
Efficiency up to 92%
Key Features
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-55°C to 125°C junction temperature range
Integrated shielded inductor
Simple PCB layout
Flexible startup sequencing using external soft-start
capacitor and precision enable
Protection against inrush currents and faults such as input
UVLO and output short circuit
Single exposed pad and standard pinout for easy
mounting and manufacturing
Fast transient response for FPGAs and ASICs
Low output voltage ripple
Pin-to-pin compatible family:
LMZ14203EXT/2EXT/1EXT (42V max 3A, 2A, 1A)
LMZ14203/2/1 (42V max 3A, 2A, 1A)
LMZ12003/2/1 (20V max 3A, 2A, 1A)
Fully Webench® Power Designer enabled
30117318
Thermal Derating Curve
VIN = 12V VOUT = 5.0V
30117319
Applications
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Point of load conversions from 5V and 12V input rail
Time critical projects
Space constrained high thermal requirement applications
Negative output voltage applications (See AN-2027)
PRODUCTION DATA information is current as of
publication date. Products conform to specifications per
the terms of the Texas Instruments standard warranty.
Production processing does not necessarily include
testing of all parameters.
301173 SNVS661D
Copyright © 1999-2012, Texas Instruments Incorporated
LMZ12001EXT
Radiated Emissions (EN 55022 Class B)
from Evaluation Board
30117350
Simplified Application Schematic
30117301
Connection Diagram
30117309
Top View
7-Lead TO-PMOD
Ordering Information
2
Order Number
Package Type
NSC Package Drawing
Supplied As
LMZ12001EXTTZ
TO-PMOD-7
TZA07A
250 Units in Tape and Reel
LMZ12001EXTTZX
TO-PMOD-7
TZA07A
500 Units in Tape and Reel
LMZ12001EXTTZE
TO-PMOD-7
TZA07A
45 Units in a Rail
Copyright © 1999-2012, Texas Instruments Incorporated
LMZ12001EXT
Pin Descriptions
Pin
Name Description
1
VIN
Supply input — Nominal operating range is 4.5V to 20V . A small amount of internal capacitance is contained within
the package assembly. Additional external input capacitance is required between this pin and exposed pad.
2
RON
On Time Resistor — An external resistor from VIN to this pin sets the on-time of the application. Typical values range
from 25k to 124k ohms.
3
EN
4
GND
5
SS
Soft-Start — An internal 8 µA current source charges an external capacitor to produce the soft-start function. This node
is discharged at 200 µA during disable, over-current, thermal shutdown and internal UVLO conditions.
6
FB
Feedback — Internally connected to the regulation, over-voltage, and short-circuit comparators. The regulation
reference point is 0.8V at this input pin. Connected the feedback resistor divider between the output and ground to set
the output voltage.
7
EP
Enable — Input to the precision enable comparator. Rising threshold is 1.18V nominal; 90 mV hysteresis nominal.
Maximum recommended input level is 6.5V.
Ground — Reference point for all stated voltages. Must be externally connected to EP.
VOUT Output Voltage — Output from the internal inductor. Connect the output capacitor between this pin and exposed pad.
EP
Exposed Pad — Internally connected to pin 4. Used to dissipate heat from the package during operation. Must be
electrically connected to pin 4 external to the package.
Copyright © 1999-2012, Texas Instruments Incorporated
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LMZ12001EXT
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for
availability and specifications.
VIN, RON to GND
-0.3V to 25V
EN, FB, SS to GND
-0.3V to 7V
Junction Temperature
150°C
Storage Temperature Range
-65°C to 150°C
ESD Susceptibility (Note 2)
± 2 kV
Peak Reflow Case Temperature
245°C
(30 sec)
For soldering specifications, refer to the following document:
www.ti.com/lit/snoa549c
Operating Ratings
(Note 1)
VIN
EN
Operation Junction Temperature
4.5V to 20V
0V to 6.5V
−55°C to 125°C
Electrical Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the
junction temperature (TJ) range of -55°C to +125°C. Minimum and Maximum limits are guaranteed through test, design or statistical
correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
Unless otherwise stated the following conditions apply: VIN = 12V, Vout = 1.8V
Symbol
Parameter
Conditions
Min
(Note 3)
Typ
(Note 4)
Max
(Note 3)
1.10
1.18
1.26
Units
SYSTEM PARAMETERS
Enable Control
VEN
VEN-HYS
EN threshold trip point
VEN rising
EN threshold hysteresis
VEN falling
SS source current
VSS = 0V
90
V
mV
Soft-Start
ISS
ISS-DIS
4.9
SS discharge current
8
11
-200
µA
µA
Current Limit
ICL
Current limit threshold
d.c. average
1.4
2.0
3.0
A
ON/OFF Timer
tON-MIN
tOFF
ON timer minimum pulse width
150
ns
OFF timer pulse width
260
ns
Regulation and Over-Voltage Comparator
VFB
VFB-OV
In-regulation feedback voltage
VSS >+ 0.8V
TJ = -55°C to 125°C
IO = 1A
0.777
0.798
0.818
VSS >+ 0.8V
TJ = 25°C
IO = 10 mA
0.786
0.802
0.818
Feedback over-voltage
protection threshold
0.92
V
V
IFB
Feedback input bias current
5
nA
IQ
Non Switching Input Current
VFB= 0.86V
1
mA
ISD
Shut Down Quiescent Current
VEN= 0V
25
μA
Thermal Shutdown
Rising
165
°C
Thermal shutdown hysteresis
Falling
15
°C
Thermal Characteristics
TSD
TSD-HYST
4
Copyright © 1999-2012, Texas Instruments Incorporated
LMZ12001EXT
Symbol
θJA
θJC
Min
(Note 3)
Typ
(Note 4)
Max
(Note 3)
Parameter
Conditions
Junction to Ambient
4 layer JEDEC Printed Circuit Board,
100 vias, No air flow
19.3
°C/W
2 layer JEDEC Printed Circuit Board, No
air flow
21.5
°C/W
No air flow
1.9
°C/W
8
mV PP
Junction to Case
Units
PERFORMANCE PARAMETERS
ΔVO
Output Voltage Ripple
ΔVO/ΔVIN
Line Regulation
VIN = 8V to 20V, IO= 1A
.01
%
ΔVO/ΔVIN
Load Regulation
VIN = 12V
1.5
mV/A
Efficiency
VIN = 12V VO = 1.8V IO = 1A
85
%
η
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: The human body model is a 100pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD-22-114.
Note 3: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical
Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).
Note 4: Typical numbers are at 25°C and represent the most likely parametric norm.
Note 5: EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007. See AN-2024 and layout for information on device under test.
Note 6: Theta JA measured on a 1.705” x 3.0” four layer board, with one ounce copper, thirty five 12 mil thermal vias, no air flow, and 1W power dissipation. Refer
to PCB layout diagrams
Copyright © 1999-2012, Texas Instruments Incorporated
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LMZ12001EXT
Typical Performance Characteristics
Unless otherwise specified, the following conditions apply: VIN = 12V; Cin = 10uF X7R Ceramic; CO = 100uF X7R Ceramic; Tambient
= 25 C for efficiency curves and waveforms.
Efficiency 4.5V Input @ 25°C
Dissipation 4.5V Input @ 25°C
30117351
Efficiency 5V Input @ 25°C
30117352
Dissipation 5V Input @ 25°C
30117353
Efficiency 6V Input @ 25°C
Dissipation 6V Input @ 25°C
30117321
6
30117354
30117322
Copyright © 1999-2012, Texas Instruments Incorporated
LMZ12001EXT
Efficiency 8V Input @ 25°C
Dissipation 8V Input @ 25°C
30117355
Efficiency 12V Input @ 25°C
30117356
Dissipation 12V Input @ 25°C
30117303
Efficiency 20V Input @ 25°C
Dissipation 20V Input @ 25°C
30117357
Copyright © 1999-2012, Texas Instruments Incorporated
30117304
30117358
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LMZ12001EXT
Efficiency 4.5V Input @ 85°C
Dissipation 4.5V Input @ 85°C
30117359
Efficiency 5V Input @ 85°C
30117360
Dissipation 5V Input @ 85°C
30117361
Efficiency 6V Input @ 85°C
Dissipation 6V Input @ 85°C
30117333
8
30117362
30117334
Copyright © 1999-2012, Texas Instruments Incorporated
LMZ12001EXT
Efficiency 8V Input @ 85°C
Dissipation 8V Input @ 85°C
30117340
Efficiency 12V Input @ 85°C
30117341
Dissipation 12V Input @ 85°C
30117342
Efficiency 20V Input @ 85°C
Dissipation 20V Input @ 85°C
30117363
Copyright © 1999-2012, Texas Instruments Incorporated
30117343
30117364
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LMZ12001EXT
Line and Load Regulation @ 25°C
Line and Load Regulation @ 85°C
30117348
Line and Load Regulation @ -55°C
30117369
Output Ripple
12VIN 3.3VO 1A
30117305
30117370
Transient Response
12VIN 3.3VO 0.6A to 1A Step
Current Limit 1.8VOUT @25°C
30117306
30117365
10
Copyright © 1999-2012, Texas Instruments Incorporated
LMZ12001EXT
Current Limit 3.3VOUT @25°C
Current Limit 1.8VOUT @85°C
30117367
Current Limit 1.8VOUT @-55°C
30117372
Thermal Derating VOUT = 1.8V
30117371
30117366
Application Block Diagram
30117308
Copyright © 1999-2012, Texas Instruments Incorporated
11
LMZ12001EXT
General Description
The LMZ12001EXT SIMPLE SWITCHER® power module is an easy-to-use step-down DC-DC solution capable of driving up to
1A load with exceptional power conversion efficiency, line and load regulation, and output accuracy. The LMZ12001EXT is available
in an innovative package that enhances thermal performance and allows for hand or machine soldering.
The LMZ12001EXT can accept an input voltage rail between 4.5V and 20V and deliver an adjustable and highly accurate output
voltage as low as 0.8V. The LMZ12001EXT only requires three external resistors and four external capacitors to complete the
power solution. The LMZ12001EXT is a reliable and robust design with the following protection features: thermal shutdown, input
under-voltage lockout, output over-voltage protection, short-circuit protection, output current limit, and allows startup into a prebiased output. A single resistor adjusts the switching frequency up to 1 MHz.
COT Control Circuit Overview
Constant On Time control is based on a comparator and an on-time one shot, with the output voltage feedback compared with an
internal 0.8V reference. If the feedback voltage is below the reference, the main MOSFET is turned on for a fixed on-time determined
by a programming resistor RON. RON is connected to VIN such that on-time is reduced with increasing input supply voltage. Following
this on-time, the main MOSFET remains off for a minimum of 260 ns. If the voltage on the feedback pin falls below the reference
level again the on-time cycle is repeated. Regulation is achieved in this manner.
Design Steps for the LMZ12001EXT Application
The LMZ12001EXT is fully supported by Webench® and offers the following: Component selection, electrical and thermal simulations as well as the build-it board for a reduction in design time. The following list of steps can be used to manually design the
LMZ12001EXT application.
•Select minimum operating VIN with enable divider resistors
•Program VO with divider resistor selection
•Program turn-on time with soft-start capacitor selection
•Select CO
•Select CIN
•Set operating frequency with RON
•Determine module dissipation
•Layout PCB for required thermal performance
ENABLE DIVIDER, RENT AND RENB SELECTION
The enable input provides a precise 1.18V band-gap rising threshold to allow direct logic drive or connection to a voltage divider
from a higher enable voltage such as Vin. The enable input also incorporates 90 mV (typ) of hysteresis resulting in a falling threshold
of 1.09V. The maximum recommended voltage into the EN pin is 6.5V. For applications where the midpoint of the enable divider
exceeds 6.5V, a small zener can be added to limit this voltage.
The function of this resistive divider is to allow the designer to choose an input voltage below which the circuit will be disabled. This
implements the feature of programmable under voltage lockout. This is often used in battery powered systems to prevent deep
discharge of the system battery. It is also useful in system designs for sequencing of output rails or to prevent early turn-on of the
supply as the main input voltage rail rises at power-up. Applying the enable divider to the main input rail is often done in the case
of higher input voltage systems where a lower boundary of operation should be established. In the case of sequencing supplies,
the divider is connected to a rail that becomes active earlier in the power-up cycle than the LMZ12001EXT output rail. The two
resistors should be chosen based on the following ratio:
RENT / RENB = (VIN UVLO / 1.18V) – 1 (1)
The LMZ12001EXT demonstration and evaluation boards use 11.8kΩ for RENB and 32.4kΩ for RENT resulting in a rising UVLO of
4.5V. This divider presents 5.34V to the EN input when the divider input is raised to 20V.
OUTPUT VOLTAGE SELECTION
Output voltage is determined by a divider of two resistors connected between VO and ground. The midpoint of the divider is connected to the FB input. The voltage at FB is compared to a 0.8V internal reference. In normal operation an on-time cycle is initiated
when the voltage on the FB pin falls below 0.8V. The main MOSFET on-time cycle causes the output voltage to rise and the voltage
at the FB to exceed 0.8V. As long as the voltage at FB is above 0.8V, on-time cycles will not occur.
The regulated output voltage determined by the external divider resistors RFBT and RFBB is:
VO = 0.8V * (1 + RFBT / RFBB) (2)
Rearranging terms; the ratio of the feedback resistors for a desired output voltage is:
RFBT / RFBB = (VO / 0.8V) - 1 (3)
These resistors should be chosen from values in the range of 1.0 kohm to 10.0 kohm.
For VO = 0.8V the FB pin can be connected to the output directly so long as an output preload resistor remains that draws more
than 20uA. Converter operation requires this minimum load to create a small inductor ripple current and maintain proper regulation
when no load is present.
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Copyright © 1999-2012, Texas Instruments Incorporated
LMZ12001EXT
A feed-forward capacitor is placed in parallel with RFBT to improve load step transient response. Its value is usually determined
experimentally by load stepping between DCM and CCM conduction modes and adjusting for best transient response and minimum
output ripple.
A table of values for RFBT , RFBB , CFF and RON is included in the applications schematic.
SOFT-START CAPACITOR SELECTION
Programmable soft-start permits the regulator to slowly ramp to its steady state operating point after being enabled, thereby reducing
current inrush from the input supply and slowing the output voltage rise-time to prevent overshoot.
Upon turn-on, after all UVLO conditions have been passed, an internal 8uA current source begins charging the external soft-start
capacitor. The soft-start time duration to reach steady state operation is given by the formula:
tSS = VREF * CSS / Iss = 0.8V * CSS / 8uA (4)
This equation can be rearranged as follows:
CSS = tSS * 8 μA / 0.8V (5)
Use of a 0.022μF capacitor results in 2.2 msec soft-start interval which is recommended as a minimum value.
As the soft-start input exceeds 0.8V the output of the power stage will be in regulation. The soft-start capacitor continues charging
until it reaches approximately 3.8V on the SS pin. Voltage levels between 0.8V and 3.8V have no effect on other circuit operation.
Note that the following conditions will reset the soft-start capacitor by discharging the SS input to ground with an internal 200 μA
current sink.
• The enable input being “pulled low”
• Thermal shutdown condition
• Over-current fault
• Internal Vcc UVLO (Approx 4V input to VIN)
CO SELECTION
None of the required CO output capacitance is contained within the module. At a minimum, the output capacitor must meet the
worst case minimum ripple current rating of 0.5 * ILR P-P, as calculated in equation (19) below. Beyond that, additional capacitance
will reduce output ripple so long as the ESR is low enough to permit it. A minimum value of 10 μF is generally required. Experimentation will be required if attempting to operate with a minimum value. Ceramic capacitors or other low ESR types are
recommended. See AN-2024 for more detail.
The following equation provides a good first pass approximation of CO for load transient requirements:
CO≥ISTEP*VFB*L*VIN/ (4*VO*(VIN—VO)*VOUT-TRAN)(6)
Solving:
CO≥ 1A*0.8V*10μH*12V / (4*3.3V*( 12V — 3.3V)*33mV)
≥ 25μF (7)
The LMZ12001EXT demonstration and evaluation boards are populated with a 100 uF 6.3V X5R output capacitor. Locations for
other output capacitors are provided.
CIN SELECTION
The LMZ12001EXT module contains an internal 0.47 µF input ceramic capacitor. Additional input capacitance is required external
to the module to handle the input ripple current of the application. This input capacitance should be located in very close proximity
to the module. Input capacitor selection is generally directed to satisfy the input ripple current requirements rather than by capacitance value. Worst case input ripple current rating is dictated by the equation:
I(CIN(RMS)) ≊ 1 /2 * IO * √ (D / 1-D) (8)
where D ≊ VO / VIN
(As a point of reference, the worst case ripple current will occur when the module is presented with full load current and when
VIN = 2 * VO).
Recommended minimum input capacitance is 10uF X7R ceramic with a voltage rating at least 25% higher than the maximum
applied input voltage for the application. It is also recommended that attention be paid to the voltage and temperature deratings of
the capacitor selected. It should be noted that ripple current rating of ceramic capacitors may be missing from the capacitor data
sheet and you may have to contact the capacitor manufacturer for this rating.
If the system design requires a certain minimum value of input ripple voltage ΔVIN be maintained then the following equation may
be used.
CIN ≥ IO * D * (1–D) / fSW-CCM * ΔVIN(9)
If ΔVIN is 1% of VIN for a 20V input to 3.3V output application this equals 200 mV and fSW = 400 kHz.
CIN≥ 1A * 3.3V/20V * (1– 3.3V/20V) / (400000 * 0.200 V)
≥ 1.7μF
Additional bulk capacitance with higher ESR may be required to damp any resonant effects of the input capacitance and parasitic
inductance of the incoming supply lines.
Copyright © 1999-2012, Texas Instruments Incorporated
13
LMZ12001EXT
RON RESISTOR SELECTION
Many designs will begin with a desired switching frequency in mind. For that purpose the following equation can be used.
fSW(CCM) ≊ VO / (1.3 * 10-10 * RON) (10)
This can be rearranged as
RON ≊ VO / (1.3 * 10 -10 * fSW(CCM) )(11)
The selection of RON and fSW(CCM) must be confined by limitations in the on-time and off-time for the COT control section.
The on-time of the LMZ12001EXT timer is determined by the resistor RON and the input voltage VIN. It is calculated as follows:
tON = (1.3 * 10-10 * RON) / VIN (12)
The inverse relationship of tON and VIN gives a nearly constant switching frequency as VIN is varied. RON should be selected such
that the on-time at maximum VIN is greater than 150 ns. The on-timer has a limiter to ensure a minimum of 150 ns for tON. This
limits the maximum operating frequency, which is governed by the following equation:
fSW(MAX) = VO / (VIN(MAX) * 150 nsec) (13)
This equation can be used to select RON if a certain operating frequency is desired so long as the minimum on-time of 150 ns is
observed. The limit for RON can be calculated as follows:
RON ≥ VIN(MAX) * 150 nsec / (1.3 * 10 -10) (14)
If RON calculated in (11) is less than the minimum value determined in (14) a lower frequency should be selected. Alternatively,
VIN(MAX) can also be limited in order to keep the frequency unchanged.
Additionally note, the minimum off-time of 260 ns limits the maximum duty ratio. Larger RON (lower FSW) should be selected in any
application requiring large duty ratio.
Discontinuous Conduction and Continuous Conduction Modes
At light load the regulator will operate in discontinuous conduction mode (DCM). With load currents above the critical conduction
point, it will operate in continuous conduction mode (CCM). When operating in DCM the switching cycle begins at zero amps
inductor current; increases up to a peak value, and then recedes back to zero before the end of the off-time. Note that during the
period of time that inductor current is zero, all load current is supplied by the output capacitor. The next on-time period starts when
the voltage on the at the FB pin falls below the internal reference. The switching frequency is lower in DCM and varies more with
load current as compared to CCM. Conversion efficiency in DCM is maintained since conduction and switching losses are reduced
with the smaller load and lower switching frequency. Operating frequency in DCM can be calculated as follows:
fSW(DCM)≊VO*(VIN-1)*10μH*1.18*1020*IO/(VIN–VO)*RON2 (15)
In CCM, current flows through the inductor through the entire switching cycle and never falls to zero during the off-time. The
switching frequency remains relatively constant with load current and line voltage variations. The CCM operating frequency can
be calculated using equation 7 above.
Following is a comparison pair of waveforms of the showing both CCM (upper) and DCM operating modes.
CCM and DCM Operating Modes
VIN = 12V, VO = 3.3V, IO = 1A/0.25A
30117312
The approximate formula for determining the DCM/CCM boundary is as follows:
IDCB≊VO*(VIN–VO)/(2*10 μH*fSW(CCM)*VIN) (16)
Following is a typical waveform showing the boundary condition.
Transition Mode Operation
14
Copyright © 1999-2012, Texas Instruments Incorporated
LMZ12001EXT
VIN = 12V, VO = 3.3V, IO = 0.29A
30117314
The inductor internal to the module is 10 μH. This value was chosen as a good balance between low and high input voltage
applications. The main parameter affected by the inductor is the amplitude of the inductor ripple current (ILR). ILR can be calculated
with:
ILR P-P=VO*(VIN- VO)/(10µH*fSW*VIN) (17)
Where VIN is the maximum input voltage and fSW is determined from equation 10.
If the output current IO is determined by assuming that IO = IL, the higher and lower peak of ILR can be determined. Be aware that
the lower peak of ILR must be positive if CCM operation is required.
POWER DISSIPATION AND BOARD THERMAL REQUIREMENTS
For the design case of VIN = 12V, VO = 1.8V, IO = 1A, TAMB(MAX) = 85°C , and TJUNCTION = 125°C, the device must see a thermal
resistance from case to ambient of:
θCA< (TJ-MAX — TAMB(MAX)) / PIC-LOSS - θJC (18)
Given the typical thermal resistance from junction to case to be 1.9 °C/W .Use the 85°C power dissipation curves in the Typical
Performance Characteristics section to estimate the PIC-LOSS for the application being designed. In this application it is 0.4W
θCA< (125 — 85) / 0.4W —1.9 = 98.1
To reach θCA = 98.1, the PCB is required to dissipate heat effectively. With no airflow and no external heat, a good estimate of the
required board area covered by 1 oz. copper on both the top and bottom metal layers is:
Board Area_cm2 = 500°C x cm2/W / θJC (19)
As a result, approximately 5 square cm of 1 oz copper on top and bottom layers is required for the PCB design. The PCB copper
heat sink must be connected to the exposed pad. Approximately thirty six, 10 mils (254 μm) thermal vias spaced 59 mils (1.5 mm)
apart must connect the top copper to the bottom copper. For an example of a high thermal performance PCB layout, refer to the
Evaluation Board application note AN–2024. For more information on thermal design see AN–2020 and AN–2026.
PC BOARD LAYOUT GUIDELINES
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC
converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in the traces. These can send
erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following
a few simple design rules.
30117311
Copyright © 1999-2012, Texas Instruments Incorporated
15
LMZ12001EXT
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize the high di/dt current paths during PC board layout. The high current
loops that do not overlap have high di/dt content that will cause observable high frequency noise on the output pin if the input
capacitor CIN1 is placed a distance away for the LMZ12001. Therefore physically place CIN1 asa close as possible to the
LMZ12001EXT VIN and GND exposed pad. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding
for both the input and output capacitor should consist of a localized top side plane that connects to the GND exposed pad (EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and enable components should be routed to the GND pin of the device. This
prevents any switched or load currents from flowing in the analog ground traces. If not properly handled, poor grounding can result
in degraded load regulation or erratic output voltage ripple behavior. Provide the single point ground connection from pin 4 to EP.
3. Minimize trace length to the FB pin.
Both feedback resistors, R FBT and RFBB, and the feed forward capacitor CFF, should be located close to the FB pin. Since the FB
node is high impedance, maintain the copper area as small as possible. The trace are from RFBT, RFBB, and CFF should be routed
away from the body of the LMZ12001EXT to minimize noise.
4. Make input and output bus connections as wide as possible.
This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize voltage accuracy at
the load, ensure that a separate feedback voltage sense trace is made to the load. Doing so will correct for voltage drops and
provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has a
plurality of copper layers, these thermal vias can also be employed to make connection to inner layer heat-spreading ground planes.
For best results use a 6 x 6 via array with minimum via diameter of 10mils (254 μm) thermal vias spaced 59mils (1.5 mm). Ensure
enough copper area is used for heat-sinking to keep the junction temperature below 125°C.
Additional Features
OUTPUT OVER-VOLTAGE COMPARATOR
The voltage at FB is compared to a 0.92V internal reference. If FB rises above 0.92V the on-time is immediately terminated. This
condition is known as over-voltage protection (OVP). It can occur if the input voltage is increased very suddenly or if the output
load is decreased very suddenly. Once OVP is activated, the top MOSFET on-times will be inhibited until the condition clears.
Additionally, the synchronous MOSFET will remain on until inductor current falls to zero.
CURRENT LIMIT
Current limit detection is carried out during the off-time by monitoring the current in the synchronous MOSFET. Referring to the
Functional Block Diagram, when the top MOSFET is turned off, the inductor current flows through the load, the PGND pin and the
internal synchronous MOSFET. If this current exceeds 1.5A (typical) the current limit comparator disables the start of the next ontime period. The next switching cycle will occur only if the FB input is less than 0.8V and the inductor current has decreased below
1.5A. Inductor current is monitored during the period of time the synchronous MOSFET is conducting. So long as inductor current
exceeds 1.5A, further on-time intervals for the top MOSFET will not occur. Switching frequency is lower during current limit due to
the longer off-time. It should also be noted that current limit is dependent on both duty cycle and temperature as illustrated in the
graphs in the typical performance section.
THERMAL PROTECTION
The junction temperature of the LMZ12001EXT should not be allowed to exceed its maximum ratings. Thermal protection is implemented by an internal Thermal Shutdown circuit which activates at 165 °C (typ) causing the device to enter a low power standby
state. In this state the main MOSFET remains off causing VO to fall, and additionally the CSS capacitor is discharged to ground.
Thermal protection helps prevent catastrophic failures for accidental device overheating. When the junction temperature falls back
below 145 °C (typ Hyst = 20 °C) the SS pin is released, VO rises smoothly, and normal operation resumes.
Applications requiring maximum output current especially those at high input voltage may require application derating at elevated
temperatures.
ZERO COIL CURRENT DETECTION
The current of the lower (synchronous) MOSFET is monitored by a zero coil current detection circuit which inhibits the synchronous
MOSFET when its current reaches zero until the next on-time. This circuit enables the DCM operating mode, which improves
efficiency at light loads.
PRE-BIASED STARTUP
The LMZ12001EXT will properly start up into a pre-biased output. This startup situation is common in multiple rail logic applications
where current paths may exist between different power rails during the startup sequence. The following scope capture shows proper
behavior during this event.
16
Copyright © 1999-2012, Texas Instruments Incorporated
LMZ12001EXT
Pre-Biased Startup
30117325
Copyright © 1999-2012, Texas Instruments Incorporated
17
LMZ12001EXT
Evaluation Board Schematic Diagram and BOM
30117307
Ref Des
Description
Case Size
Case Size
Manufacturer P/N
U1
SIMPLE SWITCHER ®
TO-PMOD-7
National Semiconductor
LMZ12001EXTTZ-ADJ
Cin1
1 µF, 50V, X7R
1206
Taiyo Yuden
UMK316B7105KL-T
Cin2
10 µF, 50V, X7R
1210
Taiyo Yuden
UMK325BJ106MM-T
CO1
1 µF, 50V, X7R
1206
Taiyo Yuden
UMK316B7105KL-T
CO2
100 µF, 6.3V, X7R
1210
Taiyo Yuden
JMK325BJ10CR7MM-T
RFBT
1.37 kΩ
0603
Vishay Dale
CRCW06031K37FKEA
RFBB
1.07 kΩ
0603
Vishay Dale
CRCW06031K07FKEA
RON
32.4 kΩ
0603
Vishay Dale
CRCW060332K4FKEA
32.4 kΩ
0603
Vishay Dale
CRCW060332K4FKEA
RENB
11.8 kΩ
0603
Vishay Dale
CRCW060311k8FKEA
CFF
22 nF, ±10%, X7R, 16V
0603
TDK
C1608X7R1H223K
CSS
22 nF, ±10%, X7R, 16V
0603
TDK
C1608X7R1H223K
D1
5.1V
SOD-23
—
Optional
RENT
18
Copyright © 1999-2012, Texas Instruments Incorporated
LMZ12001EXT
30117316
30117317
FIGURE 1. Top And Bottom View Of Evaluation PCB
Copyright © 1999-2012, Texas Instruments Incorporated
19
LMZ12001EXT
Physical Dimensions inches (millimeters) unless otherwise noted
7-Lead TZA Package
NS Package Number TZA07A
20
Copyright © 1999-2012, Texas Instruments Incorporated
LMZ12001EXT
Notes
Copyright © 1999-2012, Texas Instruments Incorporated
21
Notes
Copyright © 1999-2012, Texas Instruments
Incorporated
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