× × × × SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993
D Read and Write Clocks Can Be
D
D
D
D2
D3
D4
D5
D6
D7
D8
4
D1
D0
PAF
PAE
GND
REN1
RCLK
REN2
OE
5
3 2 1 32 31 30
29
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
RS
WEN1
WCLK
WEN2/LD
VCC
Q8
Q7
Q6
Q5
FF
Q0
Q1
Q2
Q3
Q4
D
D
D
D
Asynchronous or Coincident
Organization:
− SN74ACT72211L − 512 × 9
− SN74ACT72221L − 1024 × 9
− SN74ACT72231L − 2048 × 9
− SN74ACT72241L − 4096 × 9
Write and Read Cycle Times of 15 ns
Bit-Width Expandable
Empty and Full Flags
Programmable Almost-Empty and
Almost-Full Flags With Default Offsets
of Empty+7 and Full −7, Respectively
TTL-Compatible Inputs
Fully Compatible With the
IDT72211 / 72221/ 72231/ 72241
Available in 32-Pin Plastic J-Leaded
Chip Carrier (RJ)
EF
D
RJ PACKAGE
(TOP VIEW)
description
The SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, and SN74ACT72241L are constructed with
CMOS dual-port SRAM and are arranged as 512, 1024, 2048, and 4096 9-bit words, respectively. Internal write
and read address counters provide data throughput on a first-in, first-out (FIFO) basis. Full and empty flags
prevent memory overflow and underflow, and two programmable flags (almost full and almost empty) are
provided.
The SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, and SN74ACT72241L are synchronous FIFOs,
which means the data input port and data output port each employ synchronous control. Write-enable (WEN1,
WEN2/LD) signals allow the low-to-high transition of the write clock (WCLK) to store data in memory, and
read-enable (REN1, REN2) signals allow the low-to-high transition of the read clock (RCLK) to read data from
memory. WCLK and RCLK are independent of one another and can operate asynchronously or be tied together
for single-clock operation.
The empty-flag (EF) output is synchronized to RCLK and the full-flag (FF) output is synchronized to WCLK to
indicate absolute boundary conditions. Write operations are prohibited when FF is low, and read operations are
prohibited when EF is low. Two programmable flags, programmable almost empty (PAE) and programmable
almost full (PAF), can both be programmed to indicate any measure of memory fill. After reset, PAE defaults
to empty +7 and PAF defaults to full −7. Flag-offset programming control is similar to a memory write with the
use of the load (WEN2/LD) signal.
These devices are suited for providing a data channel between two buses operating at asynchronous or
synchronous rates. Applications include use as rate buffers for graphics systems and high-speed queues for
communication systems. A 9-bit-wide data path is provided for the transmission of byte data plus a parity bit
or packet-framing information.
The SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, and SN74ACT72241L are characterized for
operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1993, Texas Instruments Incorporated
!"#$%&" ' ()##*& %' "! +),-(%&" .%&*/
#".)(&' ("!"#$ &" '+*(!(%&"' +*# &0* &*#$' "! *1%' '&#)$*&'
'&%.%#. 2%##%&3/ #".)(&" +#"(*''4 ."*' "& *(*''%#-3 (-).*
&*'&4 "! %-- +%#%$*&*#'/
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1
× × × × SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993
functional block diagram
OE
LD
D0 −D8
Input Register
RCLK
REN1
REN2
WCLK
WEN1
WEN2
RS
Synchronous
Read
Control
Synchronous
Write
Control
Offset
Registers
Read
Pointer
Dual-Port
SRAM
512 × 9 or
1024 × 9 or
2048 × 9 or
4096 × 9 †
Write
Pointer
Reset
Logic
Output Register
Q0 −Q8
StatusFlag
Logic
EF
PAE
PAF
FF
† 512 × 9 for the SN74ACT72211L; 1024 × 9 for the SN74ACT72221L; 2048 × 9 for the SN74ACT72231L; 4096 × 9 for the SN74ACT72241L
2
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× × × × SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
D0 −D8
6 −1,
32 −30
I
Data inputs
EF
14
O
Empty-flag. When memory is empty, EF is low and further data reads are ignored by the device. When EF is
high, the memory is not empty and data reads are allowed. EF is synchronized to RCLK by one flip-flop.
FF
15
O
Full-flag. When memory is full, FF is low and data writes are inhibited. FF is synchronized to WCLK by one
flip-flop.
GND
9
OE
13
I
Ground
Output-enable. Q0 −Q8 are in the high-impedance state when OE is high. Q0 −Q8 are active when OE is low.
PAE
8
O
Programmable almost-empty-flag. PAE is low when the FIFO is almost empty based on the value in its offset
register. The default value for the register is empty + 7. PAE is synchronized to RCLK by one flip-flop.
PAF
7
O
Programmable almost-full-flag. PAF is low when the FIFO is almost full based on the value in its offset register.
The default value for the register is full −7. PAF is synchronized to WCLK by one flip-flop.
Q0 −Q8
16 −24
O
Data outputs
RCLK
11
I
Read-clock. A data read is performed by the low-to-high transition of RCLK when REN1 and REN2 are
asserted and EF is high.
REN1,
REN2
10,
11
I
Read-enable. Data is read from the FIFO on a low-to-high transition of RCLK when REN1 and REN2 are low
and EF is high.
RS
29
I
Reset. When RS is set low, the read and write pointers are initialized to the first RAM location and the FIFO
is empty. FF and PAF are set high, and EF and PAE are set low. Each bit in the data output register is set low
by a device reset. The FIFO must be reset after power up before data is written.
VCC
WCLK
WEN1
WEN2/LD
Supply voltage
27
28
26
I
Write-clock. Data is written by the low-to-high transition of WCLK when WEN1 and WEN2/LD are asserted and
FF is high.
I
Write-enable 1. WEN1 is the only write enable terminal if the device is configured to have programmable flags.
Data is written on a low-to-high transition of WCLK when WEN1 is low and FF is high. If the FIFO is not
configured for programmable flags, data is written on a low-to-high transition of WCLK when WEN1 and WEN2
are asserted and FF is high.
I
Write-enable 2 / load. This is a dual-purpose input. The FIFO can have either two write enables or
programmable flags. To use WEN2/LD as a WEN2, WEN2/LD must be held high at reset. When WEN2 and
WEN1 are asserted and FF is high, a low-to-high transition of WCLK writes data. To use WEN2/LD as the LD
terminal, it must be held low at reset. In this case, LD is asserted low to write or read the programmable offset
registers.
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3
× × × × SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993
detailed description
device reset
A reset is performed by taking the reset (RS) input low. This initializes both the write and read pointers to the
first memory location. After a reset, the full flag (FF) and programmable almost-full flag (PAF) are high and the
empty flag (EF) and programmable almost-empty flag (PAE) are low. Each bit in the data output register
(Q0 −Q8) is set low, and the flag offset registers are loaded with the default offset values. A FIFO must be reset
after power up before a write cycle is allowed.
The logic level on the dual-purpose input write enable 2/ load (WEN2/LD) during reset determines its function.
If WEN2/LD is high when RS returns high at the end of the reset cycle, the input is a second write enable (see
FIFO writes and reads) and the programmable flags (PAF, PAE) can only use the default values. If WEN2/LD
is low when RS returns high at the end of the reset cycle, the input is the load (LD) enable for writing and reading
flag offset registers (see flag programming).
FIFO writes and reads
Data is written to memory by a low-to-high transition of write clock (WCLK) when write enable 1 (WEN1) is low,
WEN2/LD is high, and FF is high. This stores D0 −D8 data in the dual-port SRAM and increments the write
pointer.
If no reads are performed after reset (RS = VIL ), FF is set low upon the completion of 512 writes to the
SN74ACT72211, 1024 writes to the SN74ACT72221, 2048 writes to the SN74ACT72231, and 4096 writes to
the SN74ACT72241. Attempted write cycles are ignored when FF is low. FF is set high by the first low-to-high
transition of WCLK after data is read from a full FIFO. FF and PAF are each synchronized to the low-to-high
transition of WCLK by one flip-flop.
If a device is configured to have two write enables (see device reset), data is read by the low-to-high transition
of read clock (RCLK) when both read enables (REN1, REN2) are low and EF is high. WEN2/LD must also be
high if the device is configured to have programmable flags. A read from the FIFO puts RAM data on Q0−Q8
and increments the read pointer in the same sequence as the write pointer. New data is not shifted to the output
register while either one or both of the read enables are high.
EF and PAE are each synchronized to the low-to-high transition of RCLK by one flip-flop. When the device is
empty, the write and read pointers are equal and EF is set low. Attempted read cycles are ignored while EF is
set low. EF is set high by the first low-to-high transition of RCLK after data is written to an empty FIFO.
WCLK and RCLK can be asynchronous or coincident to one another. Writing data to FIFO memory is
independent of reading data from FIFO memory and vice versa.
flag programming
When WEN2/LD is held low during a device reset (RS = VIL ), the input is the load (LD) enable for flag offset
programming. In this configuration, WEN2/LD can be used to access the four 8-bit offset registers contained
in the SN74ACT72211L / -72221L / -72231L / -72241L for writing or reading data.
When the device is configured for programmable flags and both WEN2/LD and WEN1 are low, the first
low-to-high transition of WCLK writes data from the data inputs to the empty offset least significant bit (LSB)
register. The second, third, and fourth low-to-high transitions of WCLK store data in the empty offset most
significant bit (MSB) register, full offset LSB register, and full offset MSB register, respectively, when WEN2/LD
and WEN1 are low. The fifth low-to-high transition of WCLK while WEN2/LD and WEN1 are low writes data to
the empty LSB register again. Figure 1 shows the register sizes and default values for the various device types.
It is not necessary to write to all the offset registers at one time. A subset of the offset registers can be written;
then, by bringing the WEN2/LD input high, the FIFO is returned to normal read and write operation. The next
time WEN2/LD is brought low, a write operation stores data in the next offset register in sequence.
4
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× × × × SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993
flag programming (continued)
The contents of the offset registers can be read to the data outputs when WEN2/LD is low and both REN1 and
REN2 are low. Low-to-high transitions of RCLK read the register contents to the data outputs. Writes and reads
should not be performed simultaneously on the offset registers (see Figure 1 and Table 1).
SN74ACT72211L − 512 × 9-Bit
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
8
7
SN74ACT72221L − 1024 × 9-Bit
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
0
8
Empty Offset (LSB) Register
Default Value = 007h
1
0
8
(MSB)
8
0
7
0
8
Full Offset (LSB) Register
0
0
SN74ACT72231L − 2048 × 9-Bit
7
8
2
00
7
8
(MSB)
000
0
8
0
3
0
(MSB)
0000
7
0
Full Offset (LSB) Register
Default Value = 007h
2
(MSB)
Default Value = 007h
0
7
0
Empty Offset (LSB) Register
Full Offset (LSB) Register
8
0
1
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
0
Default Value = 007h
8
00
SN74ACT72241L − 4096 × 9-Bit
Empty Offset (LSB) Register
8
(MSB)
7
8
(MSB)
8
0
Default Value = 007h
1
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
1
Full Offset (LSB) Register
Default Value = 007h
8
0
Empty Offset (LSB) Register
Default Value = 007h
8
7
Default Value = 007h
0
8
(MSB)
000
3
0
(MSB)
0000
Figure 1. Offset Register Location and Default Values
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5
× × × × SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993
flag programming (continued)
Table 1. Writing the Offset Registers
LD
WEN1
WCLK†
SELECTION
Empty offset (LSB)
Empty offset (MSB)
Full offset (LSB)
Full offset (MSB)
0
0
↑
0
1
↑
No operation
1
0
↑
Write into FIFO
1
1
↑
No operation
† The same selection sequence applies to reading from
the registers. REN1 and REN2 are enabled and a read
is performed on the low-to-high transition of RCLK.
programmable flag (PAE, PAF) operation
Whether the flag offset registers are programmed as described in Table 1 or the default values are used, the
programmable almost-empty flag (PAE) and programmable almost-full flag (PAF) states are determined by their
corresponding offset registers and the difference between the read and write pointers.
The number formed by the empty offset least significant bit register and empty offset most significant bit register
is referred to as n and determines the operation of PAE. PAE is synchronized to the low-to-high transition of
RCLK by one flip-flop and is low when the FIFO contains n or fewer unread words. PAE is set high by the
low-to-high transition of RCLK when the FIFO contains (n + 1) or greater unread words.
The number formed by the full offset least significant bit register and full offset most significant bit register is
referred to as m and determines the operation of PAF. PAF is synchronized to the low-to-high transition of WCLK
by one flip-flop and is set low when the number of unread words in the FIFO is greater then or equal to (512 − m)
for the SN74ACT72211L, (1024 − m) for the SN74ACT72221L, (2048 − m) for the SN74ACT72231L, and
(4096 − m) for the SN74ACT72241L. PAF is set high by the low-to-high transition of WCLK when the number
of available memory locations is greater than m (see Table 2).
Table 2. Status Flags
NUMBER OF WORDS IN FIFO
SN74ACT72211L
SN74ACT72221L
SN74ACT72231L
SN74ACT72241L
FF
PAF
PAE
0
1 to n†
0
1 to n†
0
1 to n†
0
1 to n†
H
H
L
L
H
H
L
H
(n + 1) to
[512 − (m + 1)]
(512 − m)‡ to 511
(n + 1) to
[1024 − (m + 1)]
(1024 − m)‡ to 1023
(n + 1) to
[2048 − (m + 1)]
(2048 − m)‡ to 2047
(n + 1) to
[4096 − (m + 1)]
(4096 − m)‡ to 4095
H
H
H
H
H
L
H
H
2048
4096
L
L
H
H
512
1024
† n = empty offset (default value = 7)
‡ m = full offset (default value = 7)
6
OUTPUTS
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•
EF
× × × × SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993
tw(RS)
RS
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
ÌÌÌÌÌÌÌÌÌÌÌÌÌ
tsu(RS)
th(RS)
REN1,
REN2
tsu(RS)
th(RS)
tsu(RS)
th(RS)
WEN1
WEN2/LD
(see Note A)
tpd(RS-O)
EF, PAE
tpd(RS-O)
FF, PAF
tpd(RS-O)
See Note B
Q0 −Q8
NOTES: A. Holding WEN2/LD high during reset makes it act as a second write enable. Holding WEN2/LD low during reset makes it act as a
load enable for the programmable flag offset registers.
B. After reset, the outputs are low if OE is low and at the high-impedance level if OE is high.
C. The clocks (RCLK, WCLK) can be free running during reset.
Figure 2. Reset Timing
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•
7
× × × × SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993
tc
tw(CLKH)
WCLK
tw(CLKL)
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÏÏÏ
ÏÏÏ
ÏÏÏ
D0 −D8
Data
Valid
tsu(EN)
WEN1
WEN2
(if applicable)
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÏÏÏÏ
ÌÌ
ÏÏÏÏ
ÌÌ
ÏÏÏÏ
ÌÌ
ÌÌÌÌ
ÏÏ
ÌÌÌÌ
ÏÏ
ÌÌÌÌ
ÏÏ
th(D)
tsu(D)
th(EN)
No Operation
No Operation
tpd(W-FF)
tpd(W-FF)
FF
tsk1 (see Note A)
RCLK
REN1,
REN2
NOTE A: tsk1 is the minimum time between a rising RCLK edge and a subsequent rising WCLK edge for FF to change logic levels during the
current clock cycle. If the time between the rising edge of RCLK and the subsequent rising edge of WCLK is less than tsk1, then FF may
not change its logic level until the next WCLK rising edge.
Figure 3. Write-Cycle Timing
8
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× × × × SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993
tc
tw(CLKH)
tw(CLKL)
RCLK
ÌÌÌ ÏÏÏ
ÌÌÌ ÏÏÏ
ÌÌÌ ÏÏÏ
ÌÌÌ
ÌÌÌ
ÌÌÌ
th(EN)
tsu(EN)
REN1, REN2
No Operation
tpd(R-EF)
tpd(R-EF)
EF
ta
Q0 −Q8
ten
OE
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
Valid Data
tdis
tpd(OE-Q)
tsk1 (see Note A)
WCLK
WEN1
WEN2
NOTE A: tsk1 is the minimum time between a rising WCLK edge and a subsequent rising RCLK edge for EF to change logic levels during the
current clock cycle. If the time between the rising edge of WCLK and the subsequent rising edge of RCLK is less than tsk1, then EF may
not change its logic level until the next RCLK rising edge.
Figure 4. Read-Cycle Timing
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9
× × × × SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993
WCLK
D0 −D8
WEN1
WEN2
(if applicable)
ÎÎÎÎÎÉÉ
ÎÎÎÎÎÉÉ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
tsu(D)
W0 (1st valid write)
W1
W2
W3
tsu(EN)
tsk1 (see Note A)
RCLK
tpd(R-EF)
EF
REN1,
REN2
Low
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ta
Q0 −Q8
ten
ta
W0
W1
tpd(OE-Q)
OE
NOTE A: tsk1 is the minimum time between a rising WCLK edge and a subsequent rising RCLK edge for EF to change during the current clock
cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tsk1, then EF may not change state until
the next RCLK edge.
Figure 5. First-Data-Word-Latency Timing
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× × × × SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993
No Write
No Write
WCLK
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
tsk1
(see Note A)
tsu(D)
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
tsk1
tsu(D)
Data
Write
D0 −D8
tpd(W-FF)
tpd(W-FF)
tpd(W-FF)
FF
WEN1
WEN2
(if applicable)
RCLK
tsu(EN)
th(EN)
tsu(EN)
th(EN)
REN1,
REN2
ta
OE
Low
ta
Q0 −Q8
Data in Output Register
Data Read
Next Data Read
NOTE A: tsk1 is the minimum time between a rising RCLK edge and a subsequent rising WCLK edge for FF to change logic levels during the
current clock cycle. If the time between the rising edge of RCLK and the subsequent rising edge of WCLK is less than tsk1, then FF may
not change its logic level until the next WCLK rising edge.
Figure 6. Full-Flag Timing
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11
× × × × SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993
WCLK
ÎÎÉ
ÎÎÉ
ÌÌÌ
ÌÌÌ
ÏÏÏ
ÏÏÏ
tsu(D)
D0 −D8
Data Write 1
tsu(EN)
th(EN)
WEN1
WEN2
(if applicable)
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÌÌÌ
ÌÌÌ
ÏÏÏ
ÏÏÏ
tsu(EN)
tsu(D)
Data Write 2
th(EN)
tsk1 (see Note A)
ÉÎÎÎÎÎÎÎ
É
ÎÎÎÎÎÎÎ
tsk1 (see Note A)
RCLK
tpd(R-EF)
tpd(R-EF)
tpd(R-EF)
EF
REN1,
REN2
OE
Low
ta
Q0 −Q8
Data in Output Register
Data Read
NOTE A: tsk1 is the minimum time between a rising WCLK edge and a subsequent rising RCLK edge for EF to change logic levels during the
current clock cycle. If the time between the rising edge of WCLK and the subsequent rising edge of RCLK is less than tsk1, then EF may
not change its logic level until the next RCLK rising edge.
Figure 7. Empty-Flag Timing
12
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× × × × SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993
tw(CLKH)
tw(CLKL)
See Note D
WCLK
ÌÌÌÌÏÏÏÏ
ÌÌÌÌÏÏÏÏ
ÏÏÏÏÌÌÌÌ
ÏÏÏÏÌÌÌÌ
ÏÏÏÏÌÌÌÌ
tsu(EN)
WEN1
WEN2
(if applicable)
th(EN)
tpd(W-AF)
PAF
(Full − m) Words in FIFO
(see Note B)
[Full − (m + 1)] Words in FIFO
(see Note A)
tpd(W-AF)
tsk2
RCLK
ÌÌÌ ÏÏÏ
ÌÌÌ ÏÏÏ
tsu(EN)
REN1,
REN2
th(EN)
NOTES: A. PAF offset = m
B. (512 − m) words for SN74ACT72211L, (1024 − m) words for SN74ACT72221L, (2048 − m) words for SN74ACT72231L, (4096 − m)
words for SN74ACT72241L
C. tsk2 is the minimum time between a rising RCLK edge and the subsequent rising WCLK edge for PAF to change its logic level during
that clock cycle. If the time between the rising edge of RCLK and the subsequent rising edge of WCLK is less than tsk2, then PAF
may not change its logic level until the next WCLK rising edge.
D. If a write is performed on this rising edge of the write clock, there will be [Full − (m − 1)] words in the FIFO when PAF goes low.
Figure 8. Programmable Almost-Full Flag Timing
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•
13
× × × × SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993
tw(CLKH)
tw(CLKL)
WCLK
ÌÌÌ
ÌÌÌ
ÌÌÌ
ÏÏÏ
ÏÏÏ
ÏÏÏ
tsu(EN)
WEN1
WEN2
(if applicable)
PAE
ÏÏÏ
ÏÏÏ
ÏÏÏ
ÌÌÌ
ÌÌÌ
ÌÌÌ
th(EN)
See Note A
n Words in FIFO
tsk2 (see Note B)
(n + 1) Words in FIFO
tpd(R-AE)
(see Note C)
tpd(R-AE)
RCLK
ÌÌÌÌÏÏÏÏ
ÌÌÌÌÏÏÏÏ
tsu(EN)
REN1,
REN2
th(EN)
NOTES: A. PAE offset = n
B. tsk2 is the minimum time between a rising WCLK edge and the subsequent rising RCLK edge for PAE to change its logic level during
that clock cycle. If the time between the rising edge of WCLK and the subsequent rising edge of RCLK is less than tsk2, then PAE
may not change its logic level until the next RCLK rising edge.
C. If a write is performed on this rising edge of the write clock, there will be [Empty + (n − 1)] words in the FIFO when PAE goes low.
Figure 9. Programmable Almost-Empty Flag Timing
14
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× × × × SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993
tc
tw(CLKH)
tw(CLKL)
WCLK
ÌÌÌÌÎÎÎÎÎÎ
ÌÌÌÌÎÎÎÎÎÎ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ
ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ
tsu(EN)
LD
th(EN)
tsu(EN)
WEN1
tsu(D)
D0 −D7
th(D)
PAE
Offset
(LSB)
PAE
Offset
(MSB)
PAF
Offset
(LSB)
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
PAF
Offset
(MSB)
ÎÎÎ
ÎÎÎ
ÎÎÎ
Figure 10. Write-Offset-Registers Timing
tc
tw(CLKH)
tw(CLKL)
RCLK
ÌÌÌÌÎÎÎÎÎ
ÎÎÎÎ
ÌÌÌÌÎÎÎÎÎ
ÎÎÎÎ
ÌÌÌÌÎÎÎÎÎ
ÎÎÎÎ
ÌÌÌÌ
ÌÌÌÌ
ÌÌÌÌ
tsu(EN)
LD
th(EN)
tsu(EN)
REN1,
REN2
ta
Q0 −Q7
Data In Output Register
PAE Offset (LSB)
PAE Offset (MSB)
PAF Offset (LSB)
PAF Offset (MSB)
Figure 11. Read-Offset-Registers Timing
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•
15
× × × × SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, any input, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
0.8
V
High-level output current
−2
mA
IOL
TA
Low-level output current
8
mA
70
°C
High-level input voltage
2
Operating free-air temperature
V
V
0
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
High-level output voltage
II
IOZ
Ci‡
Input current
Co‡
ICC¶
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
IOH = − 2 mA
IOL = 8 mA
VCC = 5.5 V,
VCC = 5.5 V,
VI = VCC or 0 V
VO = VCC or 0 V
f = 1 MHz
Output capacitance
VI = 0,
VO = 0,
Active supply current
fclock = 20 MHz
Low-level output voltage
High-impedance output current
Input capacitance
MIN
MAX
2.4
UNIT
V
0.4
V
±1
µA
± 10
µA
10
pF
OE ≥ VIH
10
140§
pF
SN74ACT72221L, SN74ACT72231L,
SN74ACT72241L
160#
f = 1 MHz,
SN74ACT72211L
mA
‡ Specified by design but not tested
§ ICC measurements are made with outputs open (only capacitive loading). Typical ICC = 65 + (fclock × 1.1/MHz) + (fclock × CL × 0.03/MHz-pF) mA
(CL = external capacitive load).
¶ The ICC limits are valid for tc = 15, 20, 25, and 50 ns.
# ICC measurements are made with outputs open (only capacitive loading). Typical ICC = 80 + (fclock × 2.1/MHz) + (fclock × CL × 0.03/MHz-pF) mA
(CL = external capacitive load).
16
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•
× × × × SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figures 2 through 13)
′ACT72211L-15
′ACT72221L-15
′ACT72231L-15
′ACT72241L-15
MIN
fclock
tc
Clock frequency, RCLK or WCLK
′ACT72211L-20
′ACT72221L-20
′ACT72231L-20
′ACT72241L-20
MAX
MIN
66.7
′ACT72211L-25
′ACT72221L-25
′ACT72231L-25
′ACT72241L-25
MAX
MIN
50
MAX
′ACT72211L-50
′ACT72221L-50
′ACT72231L-50
′ACT72241L-50
MIN
40
UNIT
MAX
20
MHz
15†
20
25
50
ns
Pulse duration, RCLK or WCLK
high
6
8
10
20
ns
tw(CLKL)
tw(RS)
Pulse duration, RCLK or WCLK low
6
8
10
20
ns
15
20
25
50
ns
tsu(D)
Setup time, D0 −D8 before RCLK↑
Setup time, WEN1, WEN2‡, and
LD§ before WCLK↑; REN1, REN2,
and LD§ before RCLK↑
4
5
6
10
ns
4
5
6
10
ns
15
20
25
50
ns
1
1
1
2
ns
1
1
1
2
ns
tw(CLKH)
tsu(EN)
tsu(RS)
th(D)
th(EN)
Clock cycle time, RCLK or WCLK
Pulse duration, RS low
Setup time, REN1, REN2, WEN1,
and WEN2/LD before RS high
Hold time, D0 −D8 after RCLK↑
Hold time, WEN1, WEN2‡, and
LD§ after WCLK↑; REN1, REN2,
and LD§ after RCLK↑
th(RS)
Hold time, REN1, REN2, WEN1,
and WEN2/LD after RS high
15
20
25
50
tsk1
Skew time between RCLK↑ and
WCLK↑ to allow EF or FF to
change logic levels during the
current clock cycle
6
8
10
15
ns
tsk2
Skew time between RCLK↑ and
WCLK↑ to allow PAF or PAE to
change logic levels during the
current clock cycle
28
35
40
45
ns
† Valid for PAE or PAF program values as follows:
≤ 63 bytes from the respective boundary for the SN74ACT72211L;
≤ 511 bytes from the respective boundary for the SN74ACT72221L/-72231L/-72241L;
minimum tc is 20 ns for program values greater than those indicated above.
‡ Applicable when the device is configured with two write-enable inputs (WEN2/LD = WEN2).
§ Applicable when the device is configured to have programmable flags (WEN2/LD = LD).
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× × × × SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figures 2 through 13)
′ACT72211L-15
′ACT72221L-15
′ACT72231L-15
′ACT72241L-15
PARAMETER
′ACT72211L-20
′ACT72221L-20
′ACT72231L-20
′ACT72241L-20
′ACT72211L-25
′ACT72221L-25
′ACT72231L-25
′ACT72241L-25
′ACT72211L-50
′ACT72221L-50
′ACT72231L-50
′ACT72241L-50
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
ta
Access time, RCLK↑ to Q0 −Q8
valid
2
10
2
12
3
15
3
25
ns
tpd(OE-Q)
Propagation delay time, OE low to
Q0 −Q8 valid
3
8
3
10
3
13
3
28
ns
tpd(R-EF)
Propagation delay time, RCLK↑ to
EF low or high
10
12
15
30
ns
tpd(W-FF)
Propagation delay time, WCLK↑ to
FF low or high
10
12
15
30
ns
tpd(R-AE)
Propagation delay time, RCLK↑ to
PAE low or high
10
12
15
30
ns
tpd(W-AF)
Propagation delay time, WCLK↑ to
PAF low or high
10
12
15
30
ns
tpd(RS-O)
Propagation delay time, RS low to
FF and PAF high and EF, PAE, and
Q0 −Q8 low
15
20
25
50
ns
ten
Enable time, OE low to Q0 −Q8 at
the low-impedance level†
0
tdis
Disable time, OE high to Q0 −Q8 at
the high-impedance level†
3
0
8
3
0
10
† These values are characterized but not tested.
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•
3
0
13
3
ns
28
ns
× × × × SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993
APPLICATION INFORMATION
width-expansion configuration
Word width is increased by connecting the corresponding input control signals of multiple devices. Composite
empty and full flags should be created by monitoring all devices in width expansion. Almost-full and
almost-empty status can be obtained from any one device. Figure 12 shows an 18-bit-wide data path formed
by using two SN74ACT72211L / 72221L/ 72231L/ 72241L devices.
In Figure 12, read enable 2 (REN2) is grounded and read enable 1 (REN1) acts as the only read control. The
write enable 2/load (WEN2/LD) input of only one device is set low at reset to configure the device for
programmable flags and to have it act as a load control for reading and writing the programmable flag offset
registers.
SN74ACT72211L / 72221L / 72231L / 72241L
RS
RS
RCLK
RCLK
WCLK
WCLK
REN1
REN1
WEN1
WEN1
REN2
LD
WEN2/LD
PAE
PAF
PAF
PAE
EF
FF
9
9
D0 −D8
Q0 −Q8
D0 −D8
Q0 −Q8
FF
EF
SN74ACT72211L / 72221L / 72231L / 72241L
18
D0 −D17
5V
RS
RCLK
WCLK
REN1
WEN1
REN2
18
Q0 −Q17
WEN2/LD
FF
EF
9
9
Q0 −Q8
D0 −D8
D9 −D17
Q9 −Q17
Figure 12. Word-Width Expansion for 512 / 1024 / 2048 / 4096 × 18 FIFO
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× × × × SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993
PARAMETER MEASUREMENT INFORMATION
5V
1100 Ω
From Output
Under Test
3V
1.5 V
Input
GND
30 pF
(see Note A)
680 Ω
1.5 V
tpd
tpd
VOH
In-Phase
Output
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
LOAD CIRCUIT
3V
High-Level
Input
3V
Timing
Input
1.5 V
1.5 V
GND
GND
Data
Input
tw
th
tsu
3V
3V
1.5 V
Low-Level
Input
1.5 V
GND
1.5 V
1.5 V
GND
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTE A: Includes probe and jig capacitance
Figure 13. Load Circuit and Voltage Waveforms
20
1.5 V
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