SN54ABT841, SN74ABT841A 10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS196D – FEBRUARY 1991 – REVISED MAY 1997 D D D D D D State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C High-Impedance State During Power Up and Power Down SN54ABT841 . . . JT OR W PACKAGE SN74ABT841A . . . DB, DW, NT, OR PW PACKAGE (TOP VIEW) OE 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D GND High-Drive Outputs (–32-mA IOH, 64-mA IOL) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q LE SN54ABT841 . . . FK PACKAGE (TOP VIEW) 2D 1D OE NC VCC 1Q 2Q D description The ten transparent D-type latches provide true data at their outputs. A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. 3D 4D 5D NC 6D 7D 8D 4 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 3Q 4Q 5Q NC 6Q 7Q 8Q 9D 10D GND NC LE 10Q 9Q The SN54ABT841 and SN74ABT841A 10-bit latches are designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. NC – No internal connection OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT841 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT841A is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙB is a trademark of Texas Instruments Incorporated. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABT841, SN74ABT841A 10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS196D – FEBRUARY 1991 – REVISED MAY 1997 FUNCTION TABLE INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic symbol† OE LE 1D 2D 3D 4D 5D 6D 7D 8D 9D 10D 1 EN 13 2 C1 23 1D 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages. logic diagram (positive logic) OE LE 1 13 C1 1D 2 23 1D To Seven Other Channels Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1Q SN54ABT841, SN74ABT841A 10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS196D – FEBRUARY 1991 – REVISED MAY 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT841 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT841A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero. recommended operating conditions (see Note 3) SN54ABT841 MAX MIN MAX 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC –24 Low-level output current 48 ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 High-level input voltage SN74ABT841A MIN 2 2 0.8 Input voltage 0 0 5 V V VCC –32 V mA 64 mA 5 –40 V 0.8 ns/V µs/V 200 125 UNIT 85 °C NOTE 3: Unused inputs must be held high or low to prevent them from floating. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABT841, SN74ABT841A 10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS196D – FEBRUARY 1991 – REVISED MAY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, VCC = 4 4.5 5V VOL VCC = 4 4.5 5V Vhys II IOZH IOZL Ioff ICEX IO§ SN54ABT841 MIN –1.2 MAX SN74ABT841A MIN –1.2 MAX –1.2 2.5 2.5 2.5 IOH = –3 mA IOH = –24 mA 3 3 3 2 2 IOH = –32 mA IOL = 48 mA 2* V V IOL = 64 mA 0.55 0.55* 0.55 V mV ±1 ±1 ±1 µA ±50 ±50 ±50 µA VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE ≥ 2 V ±50 ±50 ±50 µA 10 10 10 µA VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE ≥ 2 V VCC = 0, VI or VO ≤ 4.5 V –10 –10 –10 µA ±100 µA VCC = 5.5 5 5 V, V IO = 0, 0 VI = VCC or GND ∆ICC# UNIT 2 0.55 VCC = 0 to 5.5 V, VI = VCC or GND VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X VCC = 5.5 V, VO = 5.5 V VCC = 5.5 V, ICC Co TA = 25°C TYP† MAX 100 IOZPU‡ IOZPD‡ Ci MIN VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND ±100 Outputs high 50 VO = 2.5 V Outputs high –50 –140 –180 1** 50 –50 –180 –50 50 µA –180 mA µA Outputs low 24** 250** 38¶** 280 45¶ 250 38¶ mA Outputs disabled 0.5** 250** 280 250 µA mA Outputs enabled 1.5 1.5 1.5 Outputs disabled 250** 280 250 µA 1.5 1.5 1.5 mA Control inputs VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V 4 pF 7 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. ** These limits apply only to the SN74ABT841A. † All typical values are at VCC = 5 V. ‡ This parameter is characterized, but not production tested. § Not more than one output should be tested at a time, and the duration of the test should not exceed one second. ¶ This limit may vary among suppliers. # This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25°C MIN tw 4 Pulse duration, LE high or low tsu Setup time, time data before LE↓ th Hold time, time data after LE↓ POST OFFICE BOX 655303 MAX SN54ABT841 MIN MAX SN74ABT841A MIN 3.3 3.3 3.3 High 2.5 2.5 2.5 Low 1.5 1.5 1.5 High 1.5 1.5 1.5 Low 1.5 2 1.5 • DALLAS, TEXAS 75265 UNIT MAX ns ns ns SN54ABT841, SN74ABT841A 10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS196D – FEBRUARY 1991 – REVISED MAY 1997 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54ABT841 PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPZH tPZL OE Q tPHZ tPLZ OE Q VCC = 5 V, TA = 25°C MIN 1† TYP MAX 4.1 5.5 1.5† 1.6† 4 5.5 6.6† 2† 4.1 4.6 MIN MAX 1† 1.5† 6.8 1.6† 7.4 2† 6.8 1 5.8 6.5 6.6 1 3 6.2 4.9† 2.2 2† 4.1 5.7† 4.7 6.2 2.2 2† 1.5† 4.6 6.1 1.5† 6.8 7.2 UNIT ns ns ns ns † This data sheet limit may vary among suppliers. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74ABT841A PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL D Q tPLH tPHL LE Q tPZH tPZL OE Q tPHZ tPLZ OE Q VCC = 5 V, TA = 25°C MIN 1.4† 1.5† TYP MAX 4.1 5.5 4 2.1† 2.4† 4.1 5.5 5.9† 1 3 6.2 4.7† 2.2 2.6† 4.1 5.7† 4.7 1.9† 4.6 4.6 MIN MAX 1.4† 1.5† 6.2† 2.1† 2.4† 1 6.2 6.5† 6.7 5.3† 6.3† 6.2 2.2 2.6† 6.1 1.9† 6.5 7.1 UNIT ns ns ns ns † This data sheet limit may vary among suppliers. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ABT841, SN74ABT841A 10-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS196D – FEBRUARY 1991 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 7V Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 3V th 3V 1.5 V Input 1.5 V 0V Data Input 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION 3V 1.5 V Input 1.5 V 0V VOH 1.5 V Output 1.5 V VOL VOH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 1.5 V 0V tPZL tPLZ Output Waveform 1 S1 at 7 V (see Note B) tPLH tPHL Output 3V Output Control tPHL tPLH 1.5 V Output Waveform 2 S1 at Open (see Note B) 1.5 V 3.5 V VOL + 0.3 V VOL tPHZ tPZH 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) 5962-9676901Q3A ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629676901Q3A SNJ54ABT 841FK 5962-9676901QKA ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9676901QK A SNJ54ABT841W 5962-9676901QLA ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9676901QL A SNJ54ABT841JT SN74ABT841ADBLE OBSOLETE SSOP DB 24 TBD Call TI Call TI -40 to 85 SN74ABT841ADBR ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB841A SN74ABT841ADBRE4 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB841A SN74ABT841ADBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB841A SN74ABT841ADW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT841A SN74ABT841ADWG4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT841A SN74ABT841ADWR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT841A SN74ABT841ADWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT841A SN74ABT841ADWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ABT841A SN74ABT841ANT ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74ABT841ANT SN74ABT841ANTE4 ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74ABT841ANT SN74ABT841APW ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB841A SN74ABT841APWE4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB841A Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 25-Sep-2013 Status (1) Package Type Package Pins Package Drawing Qty SN74ABT841APWG4 ACTIVE TSSOP PW 24 SN74ABT841APWLE OBSOLETE TSSOP PW 24 SN74ABT841APWR ACTIVE TSSOP PW SN74ABT841APWRE4 ACTIVE TSSOP SN74ABT841APWRG4 ACTIVE SNJ54ABT841FK Eco Plan Lead/Ball Finish (2) 60 Green (RoHS & no Sb/Br) TBD 24 2000 Green (RoHS & no Sb/Br) PW 24 2000 Green (RoHS & no Sb/Br) TSSOP PW 24 2000 ACTIVE LCCC FK 28 SNJ54ABT841JT ACTIVE CDIP JT SNJ54ABT841W ACTIVE CFP W MSL Peak Temp Op Temp (°C) Device Marking (3) CU NIPDAU (4/5) Level-1-260C-UNLIM -40 to 85 AB841A Call TI Call TI -40 to 85 CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB841A CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB841A Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 AB841A 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629676901Q3A SNJ54ABT 841FK 24 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9676901QL A SNJ54ABT841JT 24 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9676901QK A SNJ54ABT841W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 25-Sep-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ABT841 : • Catalog: SN74ABT841 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74ABT841ADBR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1 SN74ABT841ADWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 SN74ABT841APWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ABT841ADBR SSOP DB 24 2000 367.0 367.0 38.0 SN74ABT841ADWR SOIC DW 24 2000 367.0 367.0 45.0 SN74ABT841APWR TSSOP PW 24 2000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MCER004A – JANUARY 1995 – REVISED JANUARY 1997 JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE 24 LEADS SHOWN PINS ** A 13 24 B 1 24 28 A MAX 1.280 (32,51) 1.460 (37,08) A MIN 1.240 (31,50) 1.440 (36,58) B MAX 0.300 (7,62) 0.291 (7,39) B MIN 0.245 (6,22) 0.285 (7,24) DIM 12 0.070 (1,78) 0.030 (0,76) 0.100 (2,54) MAX 0.320 (8,13) 0.290 (7,37) 0.015 (0,38) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.014 (0,36) 0.008 (0,20) 0.100 (2,54) 4040110/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MCFP007 – OCTOBER 1994 W (R-GDFP-F24) CERAMIC DUAL FLATPACK 0.375 (9,53) 0.340 (8,64) Base and Seating Plane 0.006 (0,15) 0.004 (0,10) 0.090 (2,29) 0.045 (1,14) 0.045 (1,14) 0.026 (0,66) 0.395 (10,03) 0.360 (9,14) 0.360 (9,14) 0.240 (6,10) 1 0.360 (9,14) 0.240 (6,10) 24 0.019 (0,48) 0.015 (0,38) 0.050 (1,27) 0.640 (16,26) 0.490 (12,45) 0.030 (0,76) 0.015 (0,38) 12 13 30° TYP 1.115 (28,32) 0.840 (21,34) 4040180-5 / B 03/95 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD Index point is provided on cap for terminal identification only. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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