SN74ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996 D D D D D D Member of the Texas Instruments Widebus Family Independent Asynchronous Inputs and Outputs 1024 Words × 18 Bits Read and Write Operations Can Be Synchronized to Independent System Clocks Programmable Almost-Full/Almost-Empty Flag Pin-to-Pin Compatible With SN74ACT7881, SN74ACT7882, and SN74ACT7884 D D D D D Input-Ready, Output-Ready, and Half-Full Flags Cascadable in Word Width and/or Word Depth Fast Access Times of 15 ns With a 50-pF Load High-Output Drive for Direct Bus Interface Available in 68-Pin PLCC (FN) and Space-Saving 80-Pin Thin Quad Flat (PN) Packages D15 D16 D17 GND RDCLK RDEN1 RDEN2 OE RESET V CC GND OR VCC Q17 Q16 GND Q15 FN PACKAGE (TOP VIEW) 9 10 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 11 59 12 58 13 57 14 56 15 55 16 54 17 53 18 52 19 51 20 50 21 49 22 48 23 47 24 46 25 45 44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 VCC Q14 Q13 GND Q12 Q11 VCC Q10 Q9 GND Q8 Q7 VCC Q6 Q5 GND Q4 DAF GND WRTCLK WRTEN1 WRTEN2 VCC AF/AE GND IR HF VCC Q0 Q1 GND Q2 Q3 VCC D14 D13 D12 D11 D10 D9 VCC D8 GND D7 D6 D5 D4 D3 D2 D1 D0 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996 Q15 VCC Q14 Q13 GND GND Q12 Q11 VCC Q10 Q9 GND Q8 Q7 VCC Q6 Q5 GND GND Q4 PN PACKAGE (TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 NC GND GND Q16 Q17 1 60 2 59 3 58 4 57 5 56 VCC OR GND VCC RESET OE RDEN2 RDEN1 RDCLK GND D17 D16 D15 NC NC 6 55 7 54 8 53 9 52 10 51 11 50 12 49 13 48 14 47 15 46 16 45 17 44 18 43 19 42 20 41 VCC VCC NC Q3 Q2 GND Q1 Q0 VCC HF IR GND GND AF/AE VCC WRTEN2 WRTEN1 WRTCLK GND NC D4 D3 D2 D1 D0 DAF NC NC D14 D13 D12 D11 D10 D9 VCC D8 GND D7 D6 D5 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NC – No internal connection description A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ACT7811 is a 1024 × 18-bit FIFO for high speed and fast access times. It processes data at rates up to 40 MHz and access times of 15 ns in a bit-parallel format. Data outputs are noninverting with respect to the data inputs. Expansion is easily accomplished in both word width and word depth. The SN74ACT7811 has normal input-bus-to-output-bus asynchronous operation. The special enable circuitry adds the ability to synchronize independent read and write (interrupts or requests) to their respective system clock. The SN74ACT7811 is characterized for operation from 0°C to 70°C. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996 logic symbol† Φ FIFO 1024 × 18 SN74ACT7811 RESET WRTCLK WRTEN1 WRTEN2 RDCLK RDEN1 OE RDEN2 DAF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 1 RESET 29 WRTCLK 30 & 31 5 IN RDY WRTEN RDCLK HALF FULL ALMOST FULL/EMPTY 4 OUT RDY & 2 EN1 35 36 33 66 IR HF AF/AE OR RDEN 3 27 26 DEF ALMOST FULL 0 0 38 25 39 24 41 23 42 22 44 21 46 20 47 19 49 17 50 Data Data 1 15 52 14 53 13 55 12 56 11 58 10 59 9 61 8 63 7 64 17 17 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the FN package. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996 functional block diagram OE D0 – D17 RDCLK RDEN1 RDEN2 Synchronous Read Control Location 1 Location 2 Read Pointer 1024 × 18 RAM WRTCLK WRTEN1 WRTEN2 Synchronous Write Control Write Pointer Location 1023 Location 1024 Register Reset Logic Q0 – Q17 RESET StatusFlag Logic DAF OR IR HF AF/AE 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996 Terminal Functions TERMINAL† NAME NO. I/O DESCRIPTION Almost-full/almost-empty flag. The AF/AE boundary is defined by the almost-full/almost-empty offset value (X). This value can be programmed during reset or the default value of 256 can be used. AF/AE is high when the FIFO contains (X + 1) or less words or (1025 – X) or more words. AF/AE is low when the FIFO contains between (X + 2) and (1024 - X) words. Programming procedure for AF/AE – The almost-full/almost-empty flag is programmed during each reset cycle. The almost-full/almost-empty offset value (X) is either a user-defined value or the default of X = 256. Instructions to program AF/AE using both methods are as follows: AF/AE 33 O User-defined X Step 1: Take DAF from high to low. Step 2: If RESET is not already low, take RESET low. Step 3: With DAF held low, take RESET high. This defines the AF/AE using X. Step 4: To retain the current offset for the next reset, keep DAF low. Default X To redefine AF/AE using the default value of X = 256, hold DAF high during the reset cycle. DAF 27 I Define almost full. The high-to-low transition of DAF stores the binary value of data inputs as the almost-full/almost-empty offset value (X). With DAF held low, a low pulse on RESET defines the AF/AE flag using X. D0 – D17 26 – 19, 17, 15 – 7 I Data inputs for 18-bit-wide data to be stored in the memory. Data lines D0 – D8 also carry the almost-full/almost-empty offset value (X) on a high-to-low transition of the DAF. HF 36 O Half-full flag. HF is high when the FIFO contains 513 or more words and is low when it contains 512 or less words. IR 35 O Input-ready flag. IR is high when the FIFO is not full and low when the device is full. During reset, IR is driven low on the rising edge of the second WRTCLK pulse. IR is then driven high on the rising edge of the second WRTCLK pulse after RESET goes high. After the FIFO is filled and IR is driven low, IR is driven high on the second WRTCLK pulse after the first valid read. OE 2 I Output enable. The data-out (Q0 – Q17) outputs are in the high-impedance state when OE is low. OE must be high before the rising edge of RDCLK to read a word from memory. O Output-ready flag. OR is high when the FIFO is not empty and low when it is empty. During reset, OR is set low on the rising edge of the third RDCLK pulse. OR is set high on the rising edge of the third RDCLK pulse to occur after the first word is written into the FIFO. OR is set low on the rising edge of the first RDCLK pulse after the last word is read. O Data outputs. The first data word to be loaded into the FIFO is moved to Q0 – Q17 on the rising edge of the third RDCLK pulse to occur after the first valid write. The RDEN1 and RDEN2 inputs do not affect this operation. Following data is unloaded on the rising edge of RDCLK when RDEN1, RDEN2, OE, and the OR are high. OR 66 Q0 – Q17 38 – 39, 41 – 42, 44, 46 – 47, 49 – 50, 52 – 53, 55 – 56, 58 – 59, 61, 63 – 64 RDCLK 5 I Read clock. Data is read out of memory on a low-to-high transition RDCLK if OR, OE, and RDEN1 and RDEN2 control inputs are high. RDCLK is a free-running clock and functions as the synchronizing clock for all data transfers out of the FIFO. OR is also driven synchronously with respect to RDCLK. RDEN1, RDEN2 4 3 I Read enable. RDEN1 and RDEN2 must be high before a rising edge on RDCLK to read a word out of memory. RDEN1 and RDEN2 are not used to read the first word stored in memory. I A reset is accomplished by taking RESET low and generating a minimum of four RDCLK and WRTCLK cycles. This ensures that the internal read and write pointers are reset and OR, HF, and IR are low and AF/AE is high. The FIFO must be reset upon power up. With DAF at a low level, a low pulse on RESET defines the AF/AE status flag using the almost-full/almost-empty offset value (X), where X is the value previously stored. With DAF at a high level, a low-level pulse on RESET defines the AF/AE flag using the default value of X = 256. RESET 1 † Terminals listed are for the FN package. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996 Terminal Functions (Continued) TERMINAL† I/O DESCRIPTION 29 I Write clock. Data is written into memory on a low-to-high transition of WRTCLK if IR, WRTEN1, and WRTEN2 are high. WRTCLK is a free-running clock and functions as the synchronizing clock for all data transfers into the FIFO. IR is also driven synchronously with respect to WRTCLK. 30 31 I Write enables. WRTEN1 and WRTEN2 must be high before a rising edge on WRTCLK for a word to be written into memory. WRTEN1 and WRTEN2 do not affect the storage of the almost-full/almost-empty offset value (X). NAME NO. WRTCLK WRTEN1, WRTEN2 † Terminals listed are for the FN package. RESET DAF WRTCLK WRTEN1 WRTEN2 D0 – D17 RDCLK RDEN1 RDEN2 OE Q0 – Q17 OR AF/AE HF IR ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Don’t Care 1 2 3 4 1 2 Don’t Care Don’t Care X† Don’t Care 1 2 3 4 Don’t Care Don’t Care 1 0 ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Invalid Don’t Care Don’t Care Don’t Care Don’t Care Store the Value of D0 – D8 as X Define the AF/AE Flag Using the Value of X † X is the binary value of D0 – D8 only. Figure 1. Reset Cycle: Define AF/AE Using the Value of X 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ RESET DAF Don’t Care WRTCLK 1 WRTEN1 Don’t Care WRTEN2 Don’t Care 2 3 4 1 2 Don’t Care D0 – D17 RDCLK 1 2 RDEN1 Don’t Care RDEN2 Don’t Care 3 4 1 0 OE Q0 – Q17 ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ Don’t Care OR AF/AE Don’t Care HF Don’t Care IR Invalid Don’t Care Define the AF/AE Flag Using the Value of X = 256 Figure 2. Reset Cycle: Define AF/AE Using the Default Value POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996 1 0 RESET ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Don’t Care DAF WRTCLK 1 0 WRTEN1 WRTEN2 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ D0 – D17 RDCLK W1 W2 W3 W4 1 2 3 W(X+2) W513 W(1025–X) W1025 1 0 RDEN1 RDEN2 1 0 OE ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Q0 – Q17 Invalid W1 OR AF/AE HF IR Figure 3. Write Cycle 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996 RESET ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 1 0 Don’t Care DAF WRTCLK 1 2 WRTEN1 WRTEN2 D0 – D17 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ W1025 RDCLK RDEN1 RDEN2 OE Q0 – Q17 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ W1 W1 W2 W3 W(X+1) W(X+2) W513 W514 W(1024–X) W(1025–X) W1024 W1025 OR AF/AE HF IR Figure 4. Read Cycle POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN74ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions MIN MAX 4.5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 V High-level output current –8 mA IOL TA Low-level output current 16 mA 70 °C High-level input voltage 2 Operating free-air temperature 0 V V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VOH VOL VCC = 4.5 V, VCC = 4.5 V, IOH = – 8 mA IOL = 16 mA II IOZ VCC = 5.5 V, VCC = 5.5 V, VI =VCC or 0 V VO =VCC or 0 V ICC§ VI =VCC – 0.2 V or 0 V One input at 3.4 V, Ci Co TYP‡ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX 2.4 UNIT V Other inputs at VCC or GND VI = 0 V, f = 1 MHz VO = 0 V, f = 1 MHz ‡ All typical values are at VCC = 5 V, TA = 25°C. § ICC tested with outputs open 10 MIN 0.5 V ±5 µA ±5 µA 400 µA 1 mA 4 pF 8 pF SN74ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996 timing requirements (see Figures 1 through 8) ′ACT7811-15 MIN fclock Clock frequency tsu th Pulse duration Setup time Hold time ′ACT7811-18 MIN MAX ′ACT7811-20 MIN MAX ′ACT7811-25 MIN 40 35 28.5 16.7 10 12 14 20 WRTCLK high 7 8.5 10 17 WRTCLK low 10 11 14 23 RDCLK high 7 8.5 10 17 RDCLK low 10 11 14 23 DAF high 10 10 10 10 WRTEN1, WRTEN2 high or low 10 10 10 10 OE, RDEN1, RDEN2 high or low 10 10 10 10 D0 – D17 before WRTCLK↑ 5 5 5 5 WRTEN1, WRTEN2 high before WRTCLK↑ 5 5 5 5 OE, RDEN1, RDEN2 high before RDCLK↑ 5 5 5 5 Reset: RESET low before first WRTCLK and RDCLK↑ 7 7 7 7 Define AF/AE: D0 – D8 before DAF↓ 5 5 5 5 Define AF/AE: DAF↓ before RESET↑ 7 7 7 7 Define AF/AE (default): DAF high before RESET↑ 5 5 5 5 D0 – D17 after WRTCLK↑ 1 1 1 1 WRTEN1, WRTEN2 high after WRTCLK↑ 1 1 1 1 OE, RDEN1, RDEN2 high after RDCLK↑ 1 1 1 1 Reset: RESET low after fourth WRTCLK and RDCLK↑ 0 0 0 0 Define AF/AE: D0 – D8 after DAF↓ 1 1 1 1 Define AF/AE: DAF low after RESET↑ 0 0 0 0 Define AF/AE (default): DAF high after RESET↑ 1 1 1 1 D0 – D17 high or low tw MAX MAX UNIT MHz ns ns ns † To permit the clock pulse to be utilized for reset purposes POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN74ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996 switching characteristics over recommended operating free-air temperature range (see Figures 9 and 10) PARAMETER FROM (INPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = 0°C to 70°C TO (OUTPUT) ′ACT7811-15 MIN fmax WRTCLK or RDCLK tpd tpd† RDCLK↑ tpd tpd tpd d tPLH tPHL tPLH tPHL ten tdis TYP ′ACT7811-18 MAX 40 Any Q 4 MIN MAX 35 12 UNIT ′ACT7811-20 MIN ′ACT7811-25 MAX 28.5 MIN MAX 16.7 MHz 15 4 18 4 20 4 25 10.5 ns WRTCLK↑ IR 2 10 2 12 2 14 2 16 ns RDCLK↑ OR 2 10 2 12 2 14 2 16 ns 6 20 6 22 6 24 6 26 6 20 6 22 6 24 6 26 6 19 6 21 6 23 6 25 6 19 6 21 6 23 6 25 AF/AE 3 19 3 21 3 23 3 25 HF 4 21 4 23 4 25 4 27 2 11 2 11 2 11 2 11 2 14 2 14 2 14 2 14 WRTCLK↑ RDCLK↑ WRTCLK↑ RDCLK↑ RESET↓ OE AF/AE HF Any Q ns ns ns ns † This parameter is measured with CL = 30 pF (see Figure 5). operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd 12 Power dissipation capacitance per 1K bits POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TEST CONDITIONS TYP UNIT CL = 50 pF, f = 5 MHz 65 pF SN74ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996 TYPICAL CHARACTERISTICS Figure 2Figure 3Figure 4 TYPICAL PROPAGATION DELAY TIME vs LOAD CAPACITANCE 18 VCC = 5 V TA = 25°C RL = 500 Ω t pd – Propagation Delay Time – ns 17 16 15 14 13 12 11 10 0 50 100 150 200 250 300 C L – Load Capacitance – pF Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SN74ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996 TYPICAL CHARACTERISTICS TYPICAL POWER DISSIPATION CAPACITANCE vs SUPPLY VOLTAGE pd – Power Dissipation Capacitance – pF 68 67 fi = 5 MHz TA = 25°C CL = 50 pF 66 65 64 63 62 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5 VCC – Supply Voltage – V Figure 6 calculating power dissipation The maximum power dissipation (PT) of the SN74ACT7811 can be calculated by: PT = VCC × [ICC + (N × ∆ICC × dc)] + Σ (Cpd × VCC2 × fi) + Σ (CL × VCC2 × fo) where: ICC N ∆ ICC dc Cpd CL fi fo 14 = = = = = = = = power-down ICC maximum number of inputs driven by a TTL device increase in supply current duty cycle of inputs at a TTL high level of 3.4 V power dissipation capacitance output capacitive load data input frequency data output frequency POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996 APPLICATION INFORMATION expanding the SN74ACT7811 The SN74ACT7811 is expandable in width and depth. Expanding in word depth offers special timing considerations: After the first data word is loaded into the FIFO, the word is unloaded and the output-ready flag (OR) output goes high after (N × 3) read-clock (RDCLK) cycles, where N is the number of devices used in depth expansion. After the FIFO is filled, the input-ready flag (IR) output goes low, the first word is unloaded, and the IR flag output is driven high after (N × 2) write-clock cycles, where N is the number of devices used in depth expansion. CLOCK WRTCLK SN74ACT7811 WRTCLK RDCLK SN74ACT7811 WRTCLK RDCLK RDCLK WRTEN1 WRTEN1 OR WRTEN1 RDEN1 RDEN1 WRTEN2 WRTEN2 RDEN1 WRTEN2 RDEN2 RDEN2 IR RDEN2 IR OE D0 – D17 D0 – D17 IR 5V Q0 – Q17 D0 – D17 OR OR OE OE Q0 – Q17 Q0 – Q17 Figure 7. Word-Depth Expansion: 2048 Words × 18 Bits, N = 2 WRTCLK WRTEN SN74ACT7811 RDCLK WRTCLK WRTEN1 RDEN1 WRTEN2 RDEN2 IR D0 – D17 RDEN OR OE D18 – D35 RDCLK Q0 – Q17 IR OE Q18 – Q35 OR SN74ACT7811 RDCLK WRTCLK WRTEN1 RDEN1 WRTEN2 RDEN2 IR OR OE D0 – D17 D0 – D17 Q0 – Q17 Q0 – Q17 Figure 8. Word-Width Expansion: 1024 Words × 36 Bits POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SN74ACT7811 1024 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS151C – JANUARY 1991 – REVISED FEBRUARY 1996 PARAMETER MEASUREMENT INFORMATION 3V Input From Output Under Test 1.5 V 0V RL = 500 Ω tpd CL = 50 pF tpd 3V 1.5 V Output 0V TOTEM-POLE OUTPUTS LOAD CIRCUIT Figure 9. Standard CMOS Outputs 3V 7V 1.5 V Input 1.5 V 0V RL = R1 = R2 tPZL S1 tPLZ R1 From Output Under Test ≈ 3.5 V Test Point CL 1.5 V Output R2 VOL 0.3 V tPHZ tPZH VOH Output 1.5 V 0.3 V ≈0V LOAD CIRCUIT VOLTAGE WAVEFORMS PARAMETER R1, R2 CL† ten tPZH tPZL 500 Ω 50 pF tdi dis tPHZ tPLZ 500 Ω 50 pF S1 Open Closed Open Closed tpd 500 Ω 50 pF Open † Includes probe and test fixture capacitanceFigure 9 Figure 10. 3-State Outputs (Any Q) 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated