TI 74ACT16544

54ACT16544, 74ACT16544
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS161A – AUGUST 1990 – REVISED APRIL 1996
D
D
D
D
D
D
D
D
Members of the Texas Instruments
Widebus Family
Inputs Are TTL-Voltage Compatible
3-State Inverted Outputs
Flow-Through Architecture Optimizes
PCB Layout
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
EPIC  (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The ’ACT16544 are 16-bit registered transceivers
that contain two sets of D-type latches for
temporary storage of data flowing in either
direction. They can be used as two 8-bit
transceivers or one 16-bit transceiver. Separate
latch-enable (LEAB or LEBA) and output-enable
(OEAB or OEBA) inputs are provided for each
register to permit independent control in either
direction of data flow.
The A-to-B enable (CEAB) input must be low to
enter data from A or to output data to B. Having
CEAB low and LEAB low makes the A-to-B
latches transparent; a subsequent low-to-high
transition at LEAB puts the A latches in the
storage mode. Data flow from B to A is similar, but
requires using the CEBA, LEBA, and OEBA
inputs.
54ACT16544 . . . WD PACKAGE
74ACT16544 . . . DL PACKAGE
(TOP VIEW)
1OEAB
1LEAB
1CEAB
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2CEAB
2LEAB
2OEAB
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEBA
1LEBA
1CEBA
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2CEBA
2LEBA
2OEBA
The 74ACT16544 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16544 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74ACT16544 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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1
54ACT16544, 74ACT16544
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS161A – AUGUST 1990 – REVISED APRIL 1996
FUNCTION TABLE†
INPUTS
OEAB
A
OUTPUT
B
CEAB
LEAB
H
X
X
X
Z
L
X
H
X
Z
L
H
L
X
L
L
L
L
B0‡
H
L
L
L
H
L
† A-to-B data flow is shown: B-to-A flow control is the
same except that it uses CEBA, LEBA, and OEBA.
‡ Output level before the indicated steady-state
input conditions were established
2
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54ACT16544, 74ACT16544
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS161A – AUGUST 1990 – REVISED APRIL 1996
logic symbol†
1OEBA
56
54
1CEBA
1LEBA
55
1
1OEAB
1CEAB
2LEBA
2OEAB
2CEAB
2 C6
31
30
28
26
27
2LEAB
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
1 C5
G2
2
29
2CEBA
G1
2 EN4
3
1LEAB
2OEBA
1 EN3
5
6
7 EN9
G7
7 C11
8 EN10
G8
8 C12
3
1
5D
6D
1
4
52
51
8
49
9
48
10
47
12
45
13
44
14
43
15
16
9
1
11D
12D
1
10
42
41
17
40
19
38
20
37
21
36
23
34
24
33
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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54ACT16544, 74ACT16544
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS161A – AUGUST 1990 – REVISED APRIL 1996
logic diagram (positive logic)
1OEBA
1CEBA
1LEBA
1OEAB
56
54
55
1
3
1CEAB
1LEAB
1A1
2
5
C1
1D
52
1B1
C1
1D
To Seven Other Channels
2OEBA
2CEBA
2LEBA
2OEAB
29
31
30
28
26
2CEAB
2LEAB
2A1
27
15
C1
1D
C1
1D
To Seven Other Channels
4
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42
2B1
54ACT16544, 74ACT16544
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS161A – AUGUST 1990 – REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCC + 0.5 V
Input voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA
Maximum power package dissipation at TA = 55°C (see Note 2): DL package . . . . . . . . . . . . . . . . . . . . . 1.4 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54ACT16544
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level output current
IOL
∆t/∆v
Low-level output current
High-level input voltage
74ACT16544
MIN
2
2
0.8
Input transition rise or fall rate
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
UNIT
V
V
0.8
V
VCC
VCC
V
–24
–24
mA
24
24
mA
VCC
VCC
0
0
V
0
10
0
10
ns/V
–55
125
–40
85
°C
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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54ACT16544, 74ACT16544
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS161A – AUGUST 1990 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
24 mA
IOH = –24
IOH = –75 mA†
TA = 25°C
TYP
MAX
MIN
MAX
74ACT16544
MIN
4.4
4.4
5.5 V
5.4
5.4
5.4
4.5 V
3.94
3.8
3.8
5.5 V
4.94
4.5 V
IOL = 24 mA
54ACT16544
4.4
5.5 V
IOL = 50 µA
VOL
MIN
4.5 V
IOH = –50
50 µA
VOH
VCC
4.8
4.8
3.85
3.85
0.1
0.1
MAX
UNIT
V
0.1
5.5 V
0.1
0.1
0.1
4.5 V
0.36
0.44
0.44
5.5 V
0.36
0.44
0.44
1.65
1.65
±1
±1
µA
V
II
Control inputs
IOL = 75 mA†
VI = VCC or GND
IOZ‡
ICC
A or B ports
VO = VCC or GND
5.5 V
±0.5
±5
±5
µA
VI = VCC or GND,
IO = 0
One input at 3.4 V,
Other inputs at VCC or GND
5.5 V
8
80
80
µA
5.5 V
0.9
1
1
mA
∆ICC§
Ci
Control inputs
Cio
A or B ports
5.5 V
5.5 V
±0.1
VI = VCC or GND
VO = VCC or GND
5V
4.5
pF
5V
12
pF
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
§ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
Pulse duration
tsu
Setup time
th
Hold time
MIN
MAX
74ACT16544
MIN
LEAB or LEBA low
5.5
5.5
5.5
Data before LEAB or LEBA↑
1.5
1.5
1.5
Data before CEAB or CEBA↑
1.5
1.5
1.5
Data after LEAB or LEBA↑
3
3
3
Data after CEAB or CEBA↑
3
3
3
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
54ACT16544
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MAX
UNIT
ns
ns
ns
54ACT16544, 74ACT16544
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS161A – AUGUST 1990 – REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPLH
tPHL
LEBA or LEAB
A or B
tPZH
tPZL
CEBA or CEAB
A or B
tPHZ
tPLZ
CEBA or CEAB
A or B
tPZH
tPZL
OEBA or OEAB
A or B
tPHZ
tPLZ
OEBA or OEAB
A or B
MIN
TA = 25°C
TYP
MAX
54ACT16544
74ACT16544
MIN
MAX
MIN
MAX
2.8
6.7
10
2.8
11.2
2.8
11.2
4
7.5
10
4
11.2
4
11.2
2.7
9
13.3
2.7
14
2.7
14
2.8
8.5
12.1
2.8
13.5
2.8
13.5
3.2
7.2
10.5
3.2
11.7
3.2
11.7
3.8
8.2
12
3.8
13.6
3.8
13.6
5.8
8.2
10.3
5.8
11.1
5.8
11.1
5
7.4
9.4
5
10.2
5
10.2
2.8
6.9
10.2
2.8
11.4
2.8
11.4
3.6
7.9
11.7
3.6
13.3
3.6
13.3
5.2
7.7
9.8
5.2
10.5
5.2
10.5
3.4
6.8
8.8
3.4
9.6
3.4
9.6
UNIT
ns
ns
ns
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
d
Power dissipation capacitance per transceiver
TEST CONDITIONS
Outputs enabled
Outputs disabled
pF
CL = 50 pF,
f = 1 MHz
TYP
60
13
UNIT
pF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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54ACT16544, 74ACT16544
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS161A – AUGUST 1990 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
500 Ω
LOAD CIRCUIT
3V
Timing Input
1.5 V
0V
tw
tsu
3V
Input
1.5 V
1.5 V
th
3V
1.5 V
1.5 V
Data Input
0V
0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3V
Input
1.5 V
1.5 V
0V
tPHL
Output
tPLH
VOH
50% VCC
VOL
50% VCC
3V
0V
tPZL
[ VCC
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
1.5 V
50% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
20% VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
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Copyright  1998, Texas Instruments Incorporated