DS90LV019 DS90LV019 3.3V or 5V LVDS Driver/Receiver Literature Number: SNLS008B DS90LV019 3.3V or 5V LVDS Driver/Receiver General Description Features The DS90LV019 is a Driver/Receiver designed specifically for the high speed low power point-to-point interconnect applications. The device operates from a single 3.3V or 5.0V power supply and includes one differential line driver and one receiver. The DS90LV019 features an independent driver and receiver with TTL/CMOS compatibility (DIN and ROUT). The logic interface provides maximum flexibility as 4 separate lines are provided (DIN, DE, RE, and ROUT). The device also features a flow-through pin out which allows easy PCB routing for short stubs between its pins and the connector. The driver has 3.5 mA output loop current. The driver translates between TTL levels (single-ended) to Low Voltage Differential Signaling levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides common-mode noise rejection. The receiver threshold is ± 100 mV over a ± 1V commonmode range and translates the low swing differential levels to standard (TTL/CMOS) levels. n n n n n n n n n n n n LVDS Signaling 3.3V or 5.0V operation Low power CMOS design Balanced Output Impedance Glitch free power up/down (Driver disabled) High Signaling Rate Capacity (above 100 Mbps) Ultra Low Power Dissipation ± 1V Common-Mode Range ± 100 mV Receiver Sensitivity Product offered in SOIC and TSSOP packages Flow-Through Pin Out Industrial Temperature Range Operation Connection Diagram DS100053-1 Order Number DS90LV019TM or DS90LV019TMTC See NS Package Number M14A or MTC14 Block Diagram DS100053-2 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2000 National Semiconductor Corporation DS100053 www.national.com DS90LV019 3.3V or 5V LVDS Driver/Receiver August 2000 DS90LV019 Absolute Maximum Ratings (Note 1) Derate SOIC Package If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. TSSOP Supply Voltage VCC −0.3V to (VCC + 0.3V) Receiver Output Voltage (ROUT) −0.3V to (VCC + 0.3V) Driver Output Voltage (DO ± ) −0.3V to +3.9V Receiver Input Voltage (RI ± ) −0.3V to (VCC + 0.3V) Driver Short Circuit Current 260˚C Recommended Operating Conditions ESD (Note 4) > 2.0 kV > 200 V (EIAJ, 0 Ω, 200 pF) −65˚C to +150˚C Lead Temperature (Soldering, 4 sec.) Continuous (HBM, 1.5 kΩ, 100 pF) 6.3mW/˚C Storage Temperature Range −0.3V to (VCC +0.3V) Driver Input Voltage (DIN) 790 mW Derate TSSOP Package 6.0V Enable Input Voltage (DE, RE) 7.7mW/˚C Min Max Units Supply Voltage (VCC) or 3.0 3.6 V Supply Voltage (VCC) 4.5 5.5 V Receiver Input Voltage 0.0 2.4 V Operating Free Air Temperature TA −40 +85 ˚C Units Maximum Package Power Dissipation at 25˚C SOIC 960 mW DC Electrical Characteristics TA = −40˚C to +85˚C unless otherwise noted, VCC = 3.3 ± 0.3V. (Notes 2, 3) Symbol Parameter Conditions Pin Min Typ Max DO+, DO− 250 350 450 mV 6 60 mV 1 1.25 1.7 V 5 60 mV +10 µA +10 µA −4 mA DIFFERENTIAL DRIVER CHARACTERISTICS RL = 100Ω (Figure 1) VOD Output Differential Voltage ∆VOD VOD Magnitude Change VOS Offset Voltage ∆VOS Offset Magnitude Change IOZD TRI-STATE ® Leakage VOUT = VCC or GND, DE = 0V −10 IOXD Power-Off Leakage VOUT = 3.6V or GND, VCC = 0V −10 ±1 ±1 IOSD Output Short Circuit Current VOUT = 0V, DE = VCC −10 −6 2.9 3.3 V 2.9 3.3 V 0.1 0.4 V −75 −34 −20 mA +100 mV DIFFERENTIAL RECEIVER CHARACTERISTICS VOH Voltage Output High VID = +100 mV IOH = −400 µA ROUT Inputs Open VOL Voltage Output Low IOL = 2.0 mA, VID = −100 mV IOS Output Short Circuit Current VOUT = 0V VTH Input Threshold High VTH Input Threshold Low IIN Input Current RI+, RI− VIN = +2.4V or 0V, VCC = 3.6V or 0V −100 −10 mV ±1 +10 µA VCC V DEVICE CHARACTERISTICS VIH Minimum Input High Voltage DIN, DE, RE VIL Maximum Input Low Voltage IIH Input High Current VIN = VCC or 2.4V IIL Input Low Current VIN = GND or 0.4V VCL Input Diode Clamp Voltage ICLAMP = −18 mA ICCD Power Supply Current 2.0 GND ±1 ±1 −1.5 VCC V µA −0.7 µA V 9 12.5 mA ICCR DE = RE = 0V 4.5 7.0 mA ICCZ DE = 0V, RE = VCC 3.7 7.0 mA 15 20 mA ICC DE = RE = VCC 0.8 ± 10 ± 10 DE = VCC, RE = 0V CD output Capacitance DO+, DO− 5 pF CR input Capacitance RI+, RI− 5 pF www.national.com 2 Symbol Parameter Conditions Pin Min Typ Max Units DO+, DO− 250 360 450 mV 6 60 mV 1 1.25 1.8 V 5 60 mV +10 µA +10 µA −4 mA DIFFERENTIAL DRIVER CHARACTERISTICS VOD Output Differential Voltage ∆VOD VOD Magnitude Change VOS Offset Voltage ∆VOS Offset Magnitude Change IOZD TRI-STATE Leakage IOXD IOSD R L = 100Ω (Figure 1) VOUT = VCC or GND, DE = 0V −10 Power-Off Leakage VOUT = 5.5V or GND, VCC = 0V −10 ±1 ±1 Output Short Circuit Current VOUT = 0V, DE = VCC −10 −6 4.3 5.0 4.3 5.0 DIFFERENTIAL RECEIVER CHARACTERISTICS VOH Voltage High VID = +100 mV IOH = −400 µA ROUT Inputs Open VOL Voltage Output Low IOL = 2.0 mA, VID = −100 mV IOS Output Short Circuit Current VOUT = 0V VTH Input Threshold High VTH Input Threshold Low IIN Input Current −150 RI+, RI− V V 0.1 0.4 V −75 −40 mA +100 mV −100 VIN = +2.4V or 0V, VCC = 5.5V or 0V mV ±1 −15 +15 µA DEVICE CHARACTERISTICS VIH Minimum Input High Voltage VIL Maximum Input Low Voltage IIH Input High Current VIN = VCC or 2.4 V IIL Input Low Current VIN = GND or 0.4V VCL Input Diode Clamp Voltage ICLAMP = −18 mA ICCD Power Supply Current DE = RE = VCC DIN, DE ,RE 2.0 VCC V GND 0.8 V ± 10 ± 10 µA 12 19 mA ±1 ±1 −1.5 −0.8 VCC µA V ICCR DE = RE = 0V 5.8 8 mA ICCZ DE = 0V, RE = VCC 4.5 8.5 mA ICC DE = VCC, RE = 0V 18 48 mA CD output Capacitance DO+, DO− 5 pF CR input Capacitance RI+, RI− 5 pF Note 1: “Absolute Maximum Ratings” are these beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. Note 3: All typicals are given for VCC = +3.3V or +5.0V and TA = +25˚C, unless otherwise stated. Note 4: ESD Rating: > 2.0 kV > 200V. HBM (1.5 kΩ, 100 pF) EIAJ (0Ω, 200 pF) Note 5: CL includes probe and fixture capacitance. Note 6: Generator waveforms for all tests unless otherwise specified; f = 1 MHz, ZO = 50Ω, tr = tf ≤ 6.0 ns (0%–100%). AC Electrical Characteristics TA = −40˚C to +85˚C, VCC = 3.3V ± 0.3V. (Note 6) Symbol Parameter Conditions Min Typ Max Units RL = 100Ω, CL = 10 pF (Figure 2 and Figure 3) 2.0 4.0 6.5 ns 1.0 5.6 7.0 ns 0.4 1.0 ns DRIVER TIMING REQUIREMENTS tPHLD Differential Propagation Delay High to Low tPLHD Differential Propagation Delay Low to High tSKD Differential Skew |tPHLD − tPLHD| tTLH Transition Time Low to High 0.2 0.7 3.0 ns tTHL Transition Time High to Low 0.2 0.8 3.0 ns 3 www.national.com DS90LV019 DC Electrical Characteristics TA = −40˚C to +85˚C unless otherwise noted, VCC = 5.0 ± 0.5V. (Notes 2, 3) DS90LV019 AC Electrical Characteristics (Continued) TA = −40˚C to +85˚C, VCC = 3.3V ± 0.3V. (Note 6) Symbol Parameter Conditions Min Typ Max Units RL = 100Ω, CL = 10 pF (Figure 4 and Figure 5) 1.5 4.0 8.0 ns DRIVER TIMING REQUIREMENTS tPHZ Disable Time High to Z tPLZ Disable Time Low to Z tPZH Enable Time Z to High tPZL Enable Time Z to Low 2.5 5.3 9.0 ns 4.0 6.0 8.0 ns 3.5 6.0 8.0 ns 3.0 5.8 7.0 ns 3.0 5.6 9.0 ns 0.55 1.5 ns RECEIVER TIMING REQUIREMENTS tPHLD Differential Propagation Delay High to Low tPLHD Differential Propagation Delay Low to High tSKD Differential Skew |tPHLD − tPLHD| CL = 10 pF, VID = 200 mV (Figure 6 and Figure 7) tr Rise Time 0.15 2.0 3.0 ns tf Fall Time 0.15 0.9 3.0 ns tPHZ Disable Time High to Z 3.0 4.0 6.0 ns tPLZ Disable Time Low to Z tPZH Enable Time Z to High tPZL Enable Time Z to Low RL = 500Ω, CL = 10 pF (Figure 8 and Figure 9) 3.0 4.5 6.0 ns 3.0 6.0 8.0 ns 3.0 6.0 8.0 ns Conditions Min Typ Max Units RL = 100Ω, CL = 10 pF (Figure 2 and Figure 3) 2.0 3.3 6.0 ns AC Electrical Characteristics TA = −40˚C to +85˚C, VCC = 5.0V ± 0.5V. (Note 6) Symbol Parameter DRIVER TIMING REQUIREMENTS tPHLD Differential Propagation Delay High to Low tPLHD Differential Propagation Delay Low to High tSKD Differential Skew |tPHLD − tPLHD| tTLH Transition Time Low to High tTHL Transition Time High to Low tPHZ Disable Time High to Z tPLZ Disable Time Low to Z tPZH Enable Time Z to High tPZL Enable Time Z to Low 1.0 0.15 RL = 100Ω, CL = 10 pF (Figure 4 and Figure 5) 3.3 5.0 ns 0.6 1.0 ns 0.9 3.0 ns 0.15 1.2 3.0 ns 1.5 3.5 7.0 ns 3.0 5.2 9.0 ns 2.0 4.5 7.0 ns 2.0 4.5 7.0 ns 3.0 6.0 8.0 ns RECEIVER TIMING REQUIREMENTS tPHLD Differential Propagation Delay High to Low tPLHD Differential Propagation Delay Low to High tSKD Differential Skew |tPHLD − tPLHD| tr Rise Time tf Fall Time tPHZ Disable Time High to Z tPLZ Disable Time Low to Z tPZH Enable Time Z to High tPZL Enable Time Z to Low www.national.com CL = 10 pF, VID = 200 mV (Figure 6 and Figure 7) RL = 500Ω, CL = 10 pF (Figure 8 and Figure 9) 4 3.0 5.6 8.0 ns 0.7 1.6 ns 0.15 0.8 3.0 ns 0.15 0.8 3.0 ns 3.0 3.5 4.5 ns 3.5 3.6 7.0 ns 3.0 5.0 7.0 ns 3.0 5.0 7.0 ns DS90LV019 Test Circuits and Timing Waveforms DS100053-3 FIGURE 1. Differential Driver DC Test Circuit DS100053-4 FIGURE 2. Differential Driver Propagation Delay and Transition Test Circuit DS100053-5 FIGURE 3. Differential Driver Propagation and Transition Time Waveforms DS100053-6 FIGURE 4. Driver TRI-STATE Delay Test Circuit 5 www.national.com DS90LV019 Test Circuits and Timing Waveforms (Continued) DS100053-7 FIGURE 5. Driver TRI-STATE Delay Waveforms DS100053-8 FIGURE 6. Receiver Propagation Delay and Transition Time Test Circuit DS100053-9 FIGURE 7. Receiver Propagation Delay and Transition Time Waveforms DS100053-10 FIGURE 8. Receiver TRI-STATE Delay Test Circuit www.national.com 6 DS90LV019 Test Circuits and Timing Waveforms (Continued) DS100053-11 FIGURE 9. Receiver TRI-STATE Delay Waveforms TRI-STATE Delay Waveforms DS100053-13 FIGURE 10. Terminated Input Fail-Safe Circuit Typical Application Diagram DS100053-12 and 0.01 µF in parallel should be used between each VCC and ground. The capacitors should be as close as possible to the VCC pin. Applications Information The DS90LV019 has two control pins, which allows the device to operate as a driver, a receiver or both driver and a receiver at the same time. There are a few common practices which should be implied when designing PCB for LVDS signaling. Recommended practices are: • Use at least 4 PCB board layer (LVDS signals, ground, power and TTL signals). • Keep drivers and receivers as close to the (LVDS port side) connector as possible. • Bypass each LVDS device and also use distributed bulk capacitance. Surface mount capacitors placed close to power and ground pins work best. Two or three multilayer ceramic (MLC) surface mount capacitors 0.1 µF, • Use controlled impedance traces which match the differential impedance of your transmission medium (i.e., Cable) and termination resistor. • Use the termination resistor which best matches the differential impedance of your transmission line. • Isolate TTL signals from LVDS signals. MEDIA (CABLE AND CONNECTOR) SELECTION: • 7 Use controlled impedance media. The cables and connectors should have a matched differential impedance of about 100Ω. www.national.com DS90LV019 Applications Information • (Continued) • Balanced cables (e.g., twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax) for noise reduction and signal quality. • For cable distances < 0.5m, most cables can be made to work effectively. For distances 0.5m ≤ d ≤ 10m, CAT 3 (category 3) twisted pair cable works well and is readily available and relatively inexpensive. For distances > 10m, and high data rates CAT 5 twisted pair is recommended. There are three Fail-Safe scenarios, open input pins, shorted inputs pins and terminated input pins. The first case is guaranteed for DS90LV019. A HIGH state on ROUT pin can be achieved by using two external resistors (one to VCC and one to GND) per Figure 10 (Terminated Input Fail-Safe Circuit). R1 and R2 should be RT to limit the loading to the LVDS driver . RT is selected to match the impedance of the cable. TABLE 1. Functional Table MODE SELECTED DE RE DRIVER MODE H H RECEIVER MODE L L TRI-STATE MODE L H FULL DUPLEX MODE H L TABLE 2. Transmitter Mode INPUTS TABLE 3. Receiver Mode OUTPUTS INPUTS OUTPUT DE DI DO+ DO− RE (RI+) − (RI−) H L L H L L ( < −100 mV) L H H H L L H ( > +100 mV) H H 2 > & > 0.8 X X L 100 mV > & > −100 mV X L X Z Z H X Z X = High or Low logic state Z = High impedance state L = Low state H = High state X = High or Low logic state Z = High impedance state L = Low state H = High state TABLE 4. Device Pin Description Pin Name Pin # Input/Output DIN 2 I TTL Driver Input DO ± 11, 12 O LVDS Driver Outputs RI ± 9, 10 I LVDS Receiver Inputs ROUT 4 O TTL Receiver Output RE 8 I Receiver Enable TTL Input (Active Low) DE 1 I GND 7 NA Ground VCC 14 NA Power Supply (3.3V ± 0.3V or 5.0V ± 0.5V) www.national.com Description Driver Enable TTL Input (Active High) 8 DS90LV019 Physical Dimensions inches (millimeters) unless otherwise noted Order Number DS90LV019TM NS Package Number M14A 9 www.national.com DS90LV019 3.3V or 5V LVDS Driver/Receiver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Order Number DS90LV019TMTC NS Package Number MTC14 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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