SMV512K32-SP www.ti.com SLVSA21H – JUNE 2011 – REVISED JULY 2013 16-Mb RADIATION-HARDENED SRAM Check for Samples: SMV512K32-SP FEATURES 1 • • • • • 20-ns Read, 13.8-ns Write Through Maximum Access Time Functionally Compatible With Commercial 512K x 32 SRAM Devices Built-In EDAC (Error Detection and Correction) to Mitigate Soft Errors Built-In Scrub Engine for Autonomous Correction CMOS Compatible Input and Output Level, Three State Bidirectional Data Bus – 3.3 ±0.3-V I/O, 1.8 ±0.15-V CORE xxx xxx xxx • • (1) (2) (3) Radiation Performance (1) – Uses Both Substrate Engineering and Radiation Hardened by Design (HBD) (2) – TID Immunity > 3e5 rad (Si) – SER < 5e-17 Upsets/Bit-Day (Core Using EDAC and Scrub) (3) – Latch up immunity > LET = 110 MeV (T = 398K) Available in a 76-Lead Ceramic Quad Flatpack Radiation tolerance is a typical value based upon initial device qualification. Radiation Data and Lot Acceptance Testing is available – contact factory for details. HardSILTM technology and memory design under a license agreement with Silicon Space Technology (SST). SER calculated using CREME96 for geosynchronous orbit, solar minimum. DESCRIPTION The SMV512K32 is a high performance asynchronous CMOS SRAM organized as 524,288 words by 32 bits. It is pin selectable between two modes: master or slave. The master device selection provides user defined autonomous EDAC scrubbing options. The slave device selection employs a scrub on demand feature that can be initiated by a master device. Three read cycles and four write cycles (described below) are available depending on the user needs. Table 1. ORDERING INFORMATION (1) TC –55°C to 125°C PACKAGE (2) ORDERABLE PART NUMBER SMV512K32HFG SMV512K32HFG 76-pin HFG 5962-1123701VXC 5962-1123701VXC SMV512K32HFGMPR SMV512K32HFG/EM (3) 25°C (1) (2) (3) TOP-SIDE MARKING For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. These units are intended for engineering evaluation only. They are processed to a non compliant flow (e.g., no burn-in) and only tested at +25°C. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted as to performance over temperature or operating life. xxx HardSILTM is a trademark of Silicon Space Technology (SST). 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2013, Texas Instruments Incorporated SMV512K32-SP SLVSA21H – JUNE 2011 – REVISED JULY 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Figure 1. SMV512K32 Block Diagram E1Z E2 o o • GZ o o o o • • • • o o Read/Write Circuit DQ(31:0) • • Row Decoder A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 WZ Memory Array 512 K x 32 ° ° ° I/O Circuit Column Decoder EDAC ° 39 57 __ VDD1 __ DQ16 __ DQ17 __ DQ18 __ DQ19 __ DQ20 __ DQ21 __ DQ22 __ DQ23 __ VSS1 __ DQ24 __ DQ25 __ DQ26 __ DQ27 __ DQ28 __ DQ29 __ DQ30 __ DQ31 __ VSS2 A0 A1 A2 A3 A4 A5 A6 A17 A18 MBE SCRUBZ BUSYZ VDD1 __ 58 VDD1 __ A10 __ A9 __ A8 __ A7 __ A6 __ WZ __ A18 __ VSS1 __ A17 __ A5 __ A4 __ A3 __ A2 __ A1 __ A0 __ VSS2 __ VSS2 __ 76 38 VSS2 __ 1 DQ0 __ DQ1 __ DQ2 __ DQ3 __ DQ4 __ DQ5 __ DQ6 __ DQ7 __ VSS1 __ DQ8 __ DQ9 __ DQ10 __ DQ11 __ DQ12 __ DQ13 __ DQ14 __ DQ15 __ VDD1 __ 19 20 __VSS2 __ MSS __ VDD2 __ MBE __ BUSYZ __ SCRUBZ __ VSS1 __ VDD2 __ E2 __ GZ __ E1Z __ A16 __ A15 __ A14 __ A13 __ A12 __ A11 __ VDD1 __ VDD1 Figure 2. SMV512K32 Pin Out 2 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SMV512K32-SP SMV512K32-SP www.ti.com SLVSA21H – JUNE 2011 – REVISED JULY 2013 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. TERMINAL FUNCTIONS PIN NAME TYPE ACTIVE DESCRIPTION A[18:0] Input N/A Address DQ[31:0] Bidirectional N/A Data input/output E1Z Input Low Chip enable - 1 E2 Input High Chip enable - 2 WZ Input Low Write enable GZ Input Low Output enable for bidirectional input/output VDD1 Power N/A Power supply (1.8 V) VDD2 Power N/A Power supply (3.3 V) VSS1 Power N/A Ground (core) VSS2 Power N/A Ground (I/O) MSS Input N/A Used for setting master/slave selection. Connect to VSS2 for master operation and VDD2 for slave operation. MBE Bidirectional High Multiple bit or single bit error indicator (output - user programmable) EDAC function select (input) SCRUBZ Bidirectional Low Master SCRUBZ (output) Slave SCRUBZ (input) BUSYZ Output Low Master BUSYZ (output) Slave (do not use) ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range (unless otherwise noted). (1) VALUE UNIT VDD1 DC supply voltage(core) –0.3 to 2.0 V VDD2 DC supply voltage (I/O) –0.3 to 3.8 V VI/O Voltage on any pin –0.3 to 3.8 V TSTG Storage temperature –65 to 150 °C PD Maximum power dissipation 1.2 W TJ Maximum junction temperature 150 °C θJC Thermal resistance, junction-to-case 5 °C/W II DC input current ±5 mA (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SMV512K32-SP 3 SMV512K32-SP SLVSA21H – JUNE 2011 – REVISED JULY 2013 www.ti.com 100.00 ← Continuous T Estimated Life (Years) J of 95°C results in operating life of 15.03 years. 10.00 1.00 70 80 90 100 110 120 130 140 150 160 0.10 Continuous TJ (°C) Notes: (1) See datasheet for absolute maximum and minimum recommended operating conditions. (2) Mil-Prf 38535, appendix B, section B.3.4 targets a 15 year operating life at 65°C ≤ TJ ≤ 95°C. (3) Above derating is based upon a worse-case power supply current condition for continuous IDD1(OP2) write operation at 50 MHz and may not reflect actual usage. Figure 3. SMV512K32 Operating Life Derating Chart (Electromigration Fail Mode) RECOMMENDED OPERATING CONDITIONS Over operating free-air temperature range (unless otherwise noted). MIN TYP MAX UNIT VDD1 DC supply voltage (core) 1.7 1.8 1.9 VDD2 DC supply voltage (I/O) 3.0 3.3 3.6 V TC Case temperature range –55 125 °C VIN DC input voltage 0 VDD2 V 4 Submit Documentation Feedback V Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SMV512K32-SP SMV512K32-SP www.ti.com SLVSA21H – JUNE 2011 – REVISED JULY 2013 ELECTRICAL CHARACTERISTICS TC = -55°C to 125°C, VDD1 = 1.7 V to 1.9 V, VDD2 = 3 V to 3.6 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX 0.7 x VDD2 VIH HIgh-level input voltage VIL Low-level input voltage VOL Low-level output voltage IOL = 4 mA, VDD2 = VDD2(min) VOH High-level output voltage IOH = -4 mA, VDD2 = VDD2(min) UNIT V 0.3 x VDD2 V 0.2 x VDD2 V 0.8 x VDD2 V CIN (1) Input capacitance f = 1 MHz at 0 V 4.5 CIO (1) Bidirectional I/O capacitance f = 1 MHz at 0 V 4.5 pF IIN Input leakage current VIN=VDD2 and VSS –500 500 nA IOZ Tri-state output leakage current VO= VDD2 and VSS VDD2 = VDD2(max), GZ=VDD2(max) –500 500 nA Short-circuit output current VDD2 = VDD2(max), VO = VDD2 VDD = VDD2(max), VO = VSS –46 46 mA VDD1 supply operating current at 1 MHz Input: VIL = VSS + 0.2 V, VIH = VDD2 - 0.2 V, IOUT = 0 A, VDD1 = VDD1(max), VDD2 = VDD2(max) IOS (2) (3) IDD1(OP1) IDD1(OP2) IDD2(OP1) IDD2(OP2) VDD1 supply operating current at 50 MHz VDD2 supply operating current at 1 MHz VDD2 supply operating current at 50 MHz Input: VIL = VSS + 0.2 V, VIH = VDD2 - 0.2 V, IOUT = 0 A, VDD1 = VDD1(max), VDD2 = VDD2(max) Input: VIL = VSS + 0.2 V, VIH = VDD2 - 0.2 V, IOUT = 0 A, VDD1 = VDD1(max), VDD2 = VDD2(max) Input: VIL = VSS + 0.2 V, VIH = VDD2 - 0.2 V, IOUT = 0 A, VDD1 = VDD1(max), VDD2 = VDD2(max) Write Read Write Read Write Read Write Read –55°C to 25°C 18 125°C 31 –55°C to 25°C 13 125°C 27 –55°C to 25°C 635 125°C 460 –55°C to 25°C 365 125°C 315 –55°C to 25°C 255 125°C 255 –55°C to 25°C 5.2 125°C 5.1 –55°C to 25°C 5.9 125°C 1.2 –55°C to 25°C 275 125°C 120 Supply stand-by current at 0 MHz CMOS inputs, IOUT = 0 A E1Z = VDD2 - 0.2 V, E2 = GND, VDD1 = VDD1(max), VDD2 = VDD2(max) –55°C to 25°C IDD1(SB) (4) 125°C 17 330 Supply stand-by current at 0 MHz CMOS inputs, IOUT = 0 A E1Z = VDD2 - 0.2 V, E2 = GND, VDD1 = VDD1(max), VDD2 = VDD2(max) –55°C to 25°C IDD2(SB) (4) 125°C 330 4.4 Supply stand-by current A[16:0] at 50 MHz CMOS inputs, IOUT = 0 A E1Z = VDD2 - 0.2 V, E2 = GND, VDD1 = VDD1(max), VDD2 = VDD2(max) –55°C to 25°C IDD1(SB) (4) 125°C 21 1.6 Supply stand-by current A[16:0] at 50 MHz CMOS inputs, IOUT = 0 A E1Z = VDD2 - 0.2 V, E2 = GND, VDD1 = VDD1(max), VDD2 = VDD2(max) –55°C to 25°C IDD2(SB) (4) 125°C 0.8 (1) (2) (3) (4) pF mA mA µA mA mA 0.375 mA µA mA mA Measured for initial qualification and after process or design changes that could affect input/output capacitance. Provided as a design limit but not guaranteed or tested. No more than one output may be shorted at a time for maximum duration of one second. VIH = VDD2(max), VIL = 0 V Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SMV512K32-SP 5 SMV512K32-SP SLVSA21H – JUNE 2011 – REVISED JULY 2013 www.ti.com OPERATIONS SMV512K32 has four control inputs called chip enable-1 (E1Z), chip enable-2 (E2), write enable (WZ) and output enable (GZ); 19 address inputs A[18:0] and a 32-bit bidirectional data bus DQ[31:0]. E1Z and E2 enable control device selection, active and stand-by modes (with and without scrub). WZ controls read and write operations. During read operation, GZ must be asserted to enable the outputs. Table 2. SRAM Device Control Operation Truth Table E1Z (1) (2) E2 GZ WZ MBE I/O MODE MODE H X X X X DQ[31:0] 3-State Standby without EDAC scrub enable L L X X X DQ[31:0] 3-state Standby with EDAC scrub enable (1) L H L H X DQ[31:0] Data out Word read L H X L X DQ[31:0] Data in Word write L H H H L DQ[31:0] 3-state 3-state L H H H H DQ[31:0] Data in/out EDAC function select (see Table 7) (2) During SCRUB mode, MBE is 3-state if GZ is high and indicates multiple or single bit error if GZ is low. Special precautions must be observed to prevent accidental over-writing of the Control Register in the memory after a bit error is detected and the memory drives MBE high (please refer to the next section). Procedures for Controlling the MBE Pin A 1-kΩ resistor must be attached from the MBE pin to ground to insure that MBE cannot float high during time intervals when it is not actively driven HIGH by the memory or actively driven by the external memory control. During normal EDAC operation, the control registers are set as shown by Sequence 1 in Table 3. Whenever the EDAC circuit encounters either a multiple-bit error or single-bit error (depending on user configuration), the MBE pin is driven high by the memory as shown by Sequence 2 in Table 3 . Following this the MBE will need to be reset (low) to restore the detection circuit for the next bit error event. The MBE pin will be pulled low by the 1-kΩ resistor when GZ is switched to high state. However, to accomplish the MBE reset properly and avoid an accidental write to the control register, the memory must first be disabled by switching either E1Z to high or E2 to low (Sequence 3) before switching GZ from low to high (Sequence 4). Note however, that if E1Z is switched to high this will disable scrub during the interval that GZ is being set high after the memory is disabled. The memory must remain disabled long enough to insure that MBE is pulled low before the memory is enabled again. During the time the memory is disabled the address at which the MBU was detected must also be changed to access the last known error free address. After the address is changed the memory can be enabled with GZ high. Then an Output Enable-controlled read operation can be performed using the last known error free address. This turns off the MBE error flag in the memory and causes the memory to drive MBE low after the GZcontrolled output data valid time, tGLMV. This procedure resets the memory back into its normal EDAC read state in which the memory will drive MBE low sequentially for each read operation until the next bit error is encountered. This avoids accidental over-writing of the Control Register in the memory. After this procedure is completed the system protocol for responding to bit errors can be executed. 6 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SMV512K32-SP SMV512K32-SP www.ti.com SLVSA21H – JUNE 2011 – REVISED JULY 2013 Table 3. Example Control Settings for Resetting MBE SEQUENCE E1Z E2 GZ WZ MBE 1 L H L H L DQ[31:0] Data out Normal read mode with EDAC enabled 2 L H L H H DQ[31:0] Data out MBE driven high when single bit or multiple bit error (depending on user configuration) is detected during read 3 H L L H H DQ[31:0] Data out Memory disabled 4 H L H H H→L DQ[31:0] Tri-state Outputs tri-stated and MBE pulled low by load R 5 L H H H L DQ[31:0] Tri-state Read at a last known error free address (1) 6 L H L H L DQ[31:0] Data out Output enable-controlled read (2) (1) (2) I/O MODE MODE During this operation MBE drive circuitry in the memory is tri-stated but MBE is held low by the 1-kΩ resistor to ground. During this operation MBE is actively driven low by the MBE drive circuitry in the memory after a time, tGLMV, and the memory is back to the original state corresponding to normal read mode with EDAC enabled. Read Operations A combination of E1Z low, E2 high and WZ high defines a read cycle. GZ low enables the outputs to drive read data to the DQ pins. Read access time is measured from the latter of device enable, output enable or valid address to valid data output. • SRAM read cycle 1 (Figure 4): Address controlled access is initiated by a change in address inputs while device is selected with WZ high and GZ low. Valid data appears on DQ[31:0] after a specified tAVQV is satisfied. Outputs remain active throughout the entire cycle. As long as the device enable and output enable are active, the minimum time between valid address changes is specified by the read cycle time tAVAV. • SRAM read cycle 2 (Figure 5): Chip-enable controlled access is initiated by the latter of either E1Z or E2 going active while GZ is low, WZ is high, and address remains stable for the entire cycle. After the specified time tETQV, the 32-bit word addressed by A[18:0] is accessed and appears at DQ[31:0]. • SRAM read cycle 3 (Figure 6): Output-enable controlled access is initiated by GZ going active while E1Z and E2 are asserted, WZ is de-asserted, and address is stable. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied. If EDAC is turned on during read operation: • If MBE is low, data is valid. • If MBE is high, data is corrupted (dependent on EDAC programming configuration on A[12], MBE can indicate a single bit or double bit error). Single bit error is correctable by EDAC. Table 4. AC Characteristics Read Cycle SYMBOL PARAMETER (1) MIN UNIT FIGURE ns Figure 4 ns Figure 4 7.5 ns Figure 4 3.5 ns Figure 6 8.6 ns Figure 6 5 ns Figure 6 tAVAV1 Read cycle time tAVQV1 Address to data valid from address change (2) tAXQX Output hold time tGLQX1 GZ-controlled output enable time tGLQV GZ-controlled output data valid tGHQZ1 GZ-controlled output enable tri-state time 3.5 tETQX E-controlled output enable time 3.5 tETQV E-controlled access time tEFQZ E-controlled tri-state time tAVMV Address to error flag valid tAXMX Address to error flag hold time from address change (1) (2) MAX 20 20 3.5 7.5 ns Figure 5 20 ns Figure 5 5 ns Figure 5 20 ns Figure 4 ns Figure 4 TC = -55°C to 125°C, VDD1 = 1.7 V to 1.9 V, VDD2 = 3 V to 3.6 V (unless otherwise noted). 20 ns at 5-pF load. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SMV512K32-SP 7 SMV512K32-SP SLVSA21H – JUNE 2011 – REVISED JULY 2013 www.ti.com Table 4. AC Characteristics Read Cycle SYMBOL (1) (continued) PARAMETER tGLMV GZ-controlled error flag valid tGLMX GZ-controlled error flag enable time tETMX E-controlled error flag enable time tETMV E-controlled error flag time MIN MAX UNIT FIGURE ns Figure 6 3.5 ns Figure 6 3.5 ns Figure 5 20 ns Figure 5 8.6 (3) GZ-controlled error flag tri-state time 3.5 5 ns Figure 6 tEFMZ (3) Chip enable change to MBE tri-state 3.5 5 ns Figure 5 tGHMZ (3) Parameters ensured by design and/or characterization if not production tested. tAVAV1 A(18:0) DQ(31:0) Previous valid data Valid data MBE Valid data tAXQX, tAXMX tAVQV1, tAVMV Assumptions: E1Z low, E2 high, WZ high, GZ low and SCRUBZ high. Reading uninitialized addresses will cause MBE to be asserted. Figure 4. SRAM Read Cycle 1, Address-Controlled Access A(18:0) Latter of E1Z low of E2 high tETQV, tETMV tEFQZ DQ(31:0) tETQX, tETMX Data valid tEFMZ MBE Data valid Assumptions: GZ low, WZ high and SCRUBZ high. Reading uninitialized addresses will cause MBE to be asserted. Figure 5. Read Cycle 2, Chip Enable-Controlled Access 8 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SMV512K32-SP SMV512K32-SP www.ti.com SLVSA21H – JUNE 2011 – REVISED JULY 2013 A[18:0] tAVQV1, tAVMV GZ tGHQZ1 tGLQV DQ(31:0) Data valid tGLQX1 tGHMZ tGLMX tGHMZ MBE tGLMV Data valid Assumptions: E1Z low, E2 high, WZ high and SCRUBZ high. Reading uninitialized addresses will cause MBE to be asserted. Figure 6. Read Cycle 3, Output Enable-Controlled Access Write Operation With Write-Through Support A combination of WZ and E1Z low with E2 high defines a write cycle. The state of GZ is “don’t care” for a write cycle although it may be necessary to set GZ high for convenient setup of new data for some system operation modes in order to avoid data bus contention. During a write operation, data just written will be sent to the outputs. When the write operation has been completed, the output data bus will be updated by controlling either GZ going low or WZ goes high while GZ low. The outputs are placed in a high impedance state when GZ is high or WZ is low during standard read and write cycles. • Write cycle 1 (Figure 7): Access and data write through controlled by WZ is initiated when WZ goes low and is terminated by WZ going high while E1Z and E2 remain active. The write pulse width is determined by tWLWH and tETWH. To avoid bus contention, tWLQZ must be satisfied before write data is applied to the DQ[31:0] pins. In addition, at the end of the write operation write data must be removed from the DQ[31:0] pins after tWHDX is met, but before tWHQX. The output access time is determined by tWHQV as long as GZ remains low. • Write cycle 1a (Figure 8): WZ controlled write cycle with GZ high is similar to write cycle 1 but with GZ fixed high so data outputs remain in high impedance state. • Write cycle 2 (Figure 9): WZ controlled write access with data write through controlled by GZ is similar to write cycle 1 with the difference being that the output data comes out when GZ goes low with WZ high. The output access time is determined by tGLQV. The GZ high pulse is used to keep the DQ[31:0] outputs in a high impedance state during the write operation to avoid bus contention. • Write cycle 3 (Figure 10): Chip enable controlled write access with data write through controlled by WZ is initiated when E1Z or E2 goes active, and the data write operation is terminated by WZ going high. The write pulse width is defined by tETWHZ from the latter of E1Z or E2 going active to WZ high. The output access time is determined by tWHQV as long as GZ remains low. As with write cycle 1, the write data must be removed from the DQ[31:0] pins after the input data hold time, tWHDX, but before tWHQX. • Write cycle 3a (Figure 11): chip enabled controlled write cycle with GZ high is similar to write cycle3, but with GZ fixed high so the data outputs remain in a high impedance state. • Write cycle 4 (Figure 12): Chip enable controlled write access with data write through controlled by GZ is similar to Write cycle 3 with the difference that the data output is controlled by GZ going low. The output access time is determined by tGLQV. The GZ high pulse is used to keep the DQ[31:0] pins in a high impedance state during the write operation to avoid bus contention. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SMV512K32-SP 9 SMV512K32-SP SLVSA21H – JUNE 2011 – REVISED JULY 2013 www.ti.com Table 5. AC Characteristics Write Cycle SYMBOL PARAMETER (1) MIN MAX UNIT FIGURE 20 ns Figure 7 Figure 9 Figure 10 Figure 12 13.8 ns Figure 8 Figure 11 tAVAV Write-through cycle time tAVAV2 (2) Write cycle time with GZ always high tETWH Device enable to end of write (WZ-controlled) 12 ns Figure 7 Figure 8 Figure 9 tETWH2 (3) Device enable to end of write (E-controlled) 11 ns Figure 10 Figure 12 tAVET Address setup time for write (E-controlled) 1.4 ns Figure 10 Figure 11 Figure 12 tEFQZ E-controlled tri-state time 3.5 ns Figure 7 Figure 9 Figure 10 Figure 12 tAVWL Address setup time for write (WZ-controlled) 3.6 ns Figure 7 Figure 8 Figure 9 tWLWH Write pulse width 7.9 ns Figure 7 Figure 8 Figure 9 Address hold time for write-through (WZ-controlled) 8.5 ns Figure 7 Figure 9 Address hold time for write (WZ-controlled) with GZ always high 2.3 ns Figure 8 0.1 ns Figure 10 Figure 11 Figure 12 Device enable pulse width (E-controlled) 19.5 ns Figure 10 Figure 12 Device enable pulse width (E-controlled) with GZ always high 12.3 ns Figure 11 ns Figure 7 Figure 8 Figure 9 Figure 10 Figure 12 (3) tWHAX tWHAX1 (2) tEFAX tETEF Address hold time for device enable (E-controlled) (3) tETEF1 (2) tDVWH Data setup time 5 8.2 tWHDX Data hold time 0.2 ns Figure 7 Figure 8 Figure 9 Figure 10 Figure 12 tWHEF Write disable time to device disable for write-through 8.5 ns Figure 7 Figure 9 Figure 10 Figure 12 tWHEF1 (2) Write disable time to device disable with GZ always high 2.3 ns Figure 8 tWHWL Write disable time. Write pulse width high for write-through. 12.1 ns Figure 7 Figure 9 tWHWL1 (2) Write disable time. Write pulse width high with GZ always high. 2.6 ns Figure 8 tWHQX WZ-controlled tri-state end time 3 ns Figure 7 Figure 10 tWHQV WZ-controlled output data valid 10 ns Figure 7 Figure 10 tWLQZ WZ-controlled tri-state time 3.3 ns Figure 7 (1) (2) (3) 10 2 TC = -55°C to 125°C, VDD1 = 1.7 V to 1.9 V, VDD2 = 3 V to 3.6 V (unless otherwise noted). Write-only operations with GZ fixed high (no write-through). Parameters ensured by design and/or characterization if not production tested. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SMV512K32-SP SMV512K32-SP www.ti.com SLVSA21H – JUNE 2011 – REVISED JULY 2013 Table 5. AC Characteristics Write Cycle SYMBOL (continued) PARAMETER tGLQX GZ-controlled output enable time tGLQV GZ-controlled output data valid tGLMX GZ-controlled error flag enable time tGLMV GZ-controlled error flag valid tWHMX (4) WZ-controlled error flag enable time tWHMV (4) WZ-controlled error flag valid tEFMZ (4) Chip enable change to MBE tri-state tWLMZ (4) WZ-controlled output MBE tri-state time (4) (1) MIN MAX UNIT FIGURE ns Figure 9 Figure 12 ns Figure 9 Figure 12 ns Figure 9 Figure 12 ns Figure 9 Figure 12 ns Figure 7 Figure 10 8.5 ns Figure 7 Figure 10 3.5 5 ns Figure 7 Figure 9 Figure 10 Figure 12 2 3.3 ns Figure 7 1.3 8.6 3.5 8.6 4 Parameters ensured by design and/or characterization if not production tested. tAVAV A[18:0] E1Z E2 tETWH tAVWL tWHEF tWLWH tWHAX WZ tWHWL tWHDX DQ[31:0] tWHQV Valid Applied Din tWLQZ tDVWH tWLMZ tEFQZ tWHQX tWHMV tEFMZ tWHMX MBE Valid Assumption: SCRUBZ high, GZ low Figure 7. SRAM Write Cycle 1, WZ Controlled Access Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SMV512K32-SP 11 SMV512K32-SP SLVSA21H – JUNE 2011 – REVISED JULY 2013 www.ti.com A[18:0] tAVAV2 E1Z E2 tETWH tAVWL tWHEF1 tWHAX1 tWLWH WZ tWHWL1 tDVWH tWHDX Applied Din DQ[31:0] Assumptions: SCRUBZ high, GZ high Figure 8. SRAM Write Cycle 1a, WZ-Controlled Write Only With GZ Fixed High tAVAV A[18:0] E1Z E2 tWHEF tETWH tAVWL tWHAX tWLWH WZ tWHWL GZ tGLQV tEFQZ tWHDX DQ[31:0] Applied Din Valid tGLQX tDVWH tGLMV MBE tGLMX tEFMZ Valid Assumptions: SCRUBZ high Figure 9. SRAM Write Cycle 2, WZ Controlled Write With Data Write Through Controlled by GZ 12 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SMV512K32-SP SMV512K32-SP www.ti.com SLVSA21H – JUNE 2011 – REVISED JULY 2013 tAVAV A[18:0] tAVET tETEF tEFAX E1Z E2 or E1Z E2 tWHEF tETWH2 WZ tWHQV tEFQZ tWHDX Valid Applied Din DQ[31:0] tWHQX tDVWH tEFMZ tWHMV tWHMX Valid MBE Assumptions: Either E1Z,/E2 scenario can occur, SCRUBZ high, GZ low Figure 10. SRAM Write Cycle 3, Enable Controlled Write With Data Write Through Controlled by WZ tAVAV2 A[18:0] tAVET tETEF1 E1Z E2 or E1Z E2 tETWH2 tWHEF1 tWHAX1 WZ tWHDX DQ[31:0] Applied Din tDVWH Assumptions: Either E1Z,/E2 scenario can occur, SCRUBZ high, GZ High Figure 11. SRAM Write Cycle 3a, Enable Controlled Write Only With GZ Fixed High Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SMV512K32-SP 13 SMV512K32-SP SLVSA21H – JUNE 2011 – REVISED JULY 2013 www.ti.com tAVAV A[18:0] tAVET tETEF tEFAX E1Z E2 or E1Z E2 tETWH2 tWHEF WZ GZ tWHDX tGLQV tDVWH DQ[31:0] Applied Din tEFQZ Valid tEFMZ tGLQX tGLMV Valid MBE tGLMX Assumptions: Either E1Z,/E2 scenario can occur, SCRUBZ high Figure 12. SRAM Write Cycle 4, Enable Controlled Write With Data Write Through Controlled by GZ Scrub Operation The SMV512K32 uses embedded error detection and correction (EDAC) to correct single bit upset of each 32-bit word. The device pins BUSYZ and SCRUBZ are used differently depending on whether the device is operated as a slave device (MSS pin connected to VDD2) or as a master device (MSS pin connected to VSS2). The BUSYZ pin is an output for the master device and is driven low to indicate that a scrub cycle is about to be initiated. The BUSYZ signal can be used to generate wait states by the memory controller. The BUSYZ pin should should be left unconnected for slave devices. The SCRUBZ pin is an output on the master device and an input on slave devices. The master SCRUBZ pin is driven low when a scrub cycle initiates and can be used to trigger scrub cycles for slave units by connecting their respective SCRUBZ pins to the SCRUBZ master output. The EDAC operation truth table is shown in Table 6. 14 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SMV512K32-SP SMV512K32-SP www.ti.com SLVSA21H – JUNE 2011 – REVISED JULY 2013 Table 6. EDAC Control Operation Mode Truth Table (1) MBE (OUTPUT) SCRUBZ BUSYZ H H H Read I/O MODE Data error detected (1) MODE L H H Read Valid data out (1) X H H X Device ready X H L X Device ready/early scrub request coming X L X Not accessible Device busy (scrub in progress) MBE is only valid in EDAC operation modes (Read with EDAC enable or scrub). MBE indicates Multiple Bit Error if A[12] bit in the control register is ‘0’. MBE indicates Single Bit Error if A[12] bit in the control register is ‘1’. To allow system design flexibility, the time delay between falling edges of BUSYZ and SCRUBZ as well as the scrub rate are user programmable (see the control register programming description below). Depending on environment and usage, some users may want a high scrub rate to minimize error rate at the sacrifice of reduced data throughput, while others may want a lower scrub rate to increase the throughput and accept a higher error rate. Data errors are detected and corrected not only during scrub cycles, but also during normal read cycles. EDAC Configuration and Scrub Address Polling (Master Device Only) The user can program the scrub rate and the edge relationship between BUSYZ and SCRUBZ by writing configuration data to the control register. The value recorded in the control register determines scrub rate, SCRUBZ to BUSYZ delay, EDAC bypass selection, scrub enable/disable and single bit or multiple bit error detection. See Table 8 for more detail. Table 9 and Table 10 give typical timing characteristics for various configuration options. Table 11 gives the AC characteristics for EDAC functions. The following EDAC control operations are defined by Table 7. • Control register write (Figure 15): This mode is used to write configuration values to the EDAC control register. • Control register read (Figure 16): This mode is used to read the contents of the EDAC control register. • Scrub address counter read (Figure 17): This mode is to read out the address counter which is used as a pointer for scrub operations. The address counter is reset to all ‘1’ when the configuration register is written. It is then automatically incremented for each scrub cycle. In the event of a single or multiple bit error detected during a scrub cycle, the address can be polled to determine the location of the data error. During the address counter read, the 19 bits of the counter are output on data bits DQ[18:0]. The value of the other data bits DQ[31:19] are ignored. Table 7. EDAC Function Select Truth Table (1) (1) E1Z E2 GZ WZ MBE A7 A8 A9 A10 L H H H H X L H H H H X L H H H H H MODE X L L Write control register X H L Read control register X X H Address counter read All other combinations of A7-A10 are reserved and should be avoided. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SMV512K32-SP 15 SMV512K32-SP SLVSA21H – JUNE 2011 – REVISED JULY 2013 www.ti.com Table 8. EDAC Control Register Programming (1) (2) ADDRESS BIT PARAMETER VALUE FUNCTION 0–15 As scrub rate changes from 0 to 15, then the interval between scrub cycles, tBLBL, will change as follows: 0 = N/A /xxxxxxxxxxx. 6 = 222 kHz xxx 11 = 7 kHz 1 = N/A /xxxxxxxxxxx. 7 = 111 kHz xxx 12 = 3.5 kHz 2 = N/A /xxxxxxxxxxx. 8 = 55 kHz xxxx. 13 = 1.75 kHz 3 = N/A .xxxxxxxxxx.x 9 = 28 kHz xxxx. 14 = 0.875 kHz 4 = 888 kHz xxxx xxx 10 = 14 kHz xxxx 15 = 0.433 kHz 5 = 444 kHz See Table 9. A[7:4] BUSYZ to SCRUBZ – Delays are approximate and will vary with temperature and voltage conditions as well as process parameters 0–15 If A[7:4] changes from 0 to 15, the interval tBLSL between falling edges of BUSYZ and SCRUBZ will change as follows: 0 = 80 ns xxxxx 6 = 480 ns xxxxxx 11 = 820 ns 1 = 160 ns xxxx 7 = 560 ns xxxxxx 12 = 880 ns 2 = 220 ns xxxx 8 = 620 ns xxxxxx 13 = 960 ns 3 = 280 ns xxxx 9 = 680 ns xxxxxx 14 = 1020 ns 4 = 360 ns xxxx 10 = 760 ns xxxxx 15 = 1080 ns 5 = 420 ns See Table 10. A[8] EDAC bypass bit 0/1 0: Enable EDAC 1: Disable EDAC including scrub A[11] Scrub enable bit 0/1 0: Enable scrub 1: Disable scrub A[12] SE/DE indication bit 0/1 0: MBE indicates multiple-bit error 1: MBE indicates single-bit error A[3:0] (1) (2) Scrub rate – Rates are approximate and will vary with temperature and voltage conditions as well as process parameters A(10:9) must be '00' during control register programming according to Table 7. A(18:13) are don't care. xxx NOTE During power up, states of all registers are random so it is imperative that the user execute Write Control Register and preferably Read Control Register to affirm desired operations. The following values are recommended to set for initial use: 1. Scrub rate is 111 kHz. 2. tBLSL is 760 ns. 3. EDAC bit is 0 (enabled). 4. Scrub enable bit is 0 (enabled). 5. SE/DE indication bit is 0 (multiple bit). 16 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SMV512K32-SP SMV512K32-SP www.ti.com SLVSA21H – JUNE 2011 – REVISED JULY 2013 Table 9. Scrub Rate Variation (Voltage = 1.8 V, Temperature = –55°C to 125°C) VALUE MAX (ns) 0000 N/A 0001 N/A 0010 N/A 0011 N/A 0100 1,500 0101 3,100 0110 6,100 0111 12,200 1000 24,200 1001 48,300 1010 96,400 1011 192,500 1100 384,500 1101 770,000 1110 1,500,00 1111 3,200,00 Table 10. BUSYZ Low to SCRUBZ Low Delay Variation (Voltage = 1.8 V, Temperature = –55°C to 125°C) VALUE MAX (ns) 0000 80 0001 180 0010 270 0011 370 0100 460 0101 600 0110 650 0111 800 1000 900 1001 1000 1010 1200 1011 1300 1100 1400 1101 1500 1110 1600 1111 1600 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SMV512K32-SP 17 SMV512K32-SP SLVSA21H – JUNE 2011 – REVISED JULY 2013 www.ti.com Table 11. AC Characteristics for EDAC Function SYMBOL PARAMETER MIN (1) MAX UNIT FIGURE See Table 10 ns Figure 13 Figure 14 See Table 9 ns Figure 14 tBLSL User programmable, BUSYZ low to SCRUBZ low tBLBL User programmable, BUSYZ low to BUSYZ low tSLSH SCRUBZ low to SCRUBZ high 200 504 ns Figure 13 Figure 14 tSHBH SCRUBZ high to BUSYZ high 50 120 ns Figure 13 Figure 14 tETMH Device enable to MBE high 5.5 ns Figure 15 Figure 16 Figure 17 tGHMH GZ high to MBE high 6.5 ns Figure 15 Figure 16 Figure 17 tAVMH Address valid to MBE high 0.9 ns Figure 15 Figure 16 Figure 17 tMHML MBE high to MBE low 12.8 ns Figure 15 Figure 16 Figure 17 tMLEF MBE low to device disable 0.4 ns Figure 15 Figure 16 Figure 17 tMLGL MBE low to GZ low 1.8 ns Figure 15 Figure 16 Figure 17 tMLAX MBE low to address change 0.1 ns Figure 15 Figure 16 Figure 17 tMHQX MBE high to data change 4.5 ns Figure 16 Figure 17 tMHQV MBE high to data valid 8.2 ns Figure 16 Figure 17 tEFQZ Memory enable change to output data tri-state 3.5 5 ns Figure 16 Figure 17 tEFMZ (2) Memory enable change to MBE tri-state 3.5 5 ns Figure 14 tGLMX GZ-controlled error flag enable time 3.5 ns Figure 13 tETMX E-controlled error flag enable time 3.5 ns Figure 14 tINIT_E E1Z low to BUSYZ low 160 ns Figure 14 tINIT_MBE MBE low to BUSYZ low 160 ns Figure 13 tSLMV SCRUBZ low to MBE valid 146 ns Figure 13 Figure 14 tE1ZHSH E1Z high to SCRUBZ high 20 ns Figure 14 tE1ZHBH E1Z high to BUSYZ high 20 ns Figure 14 tMHBH MBE high to BUSYZ high 20 ns Figure 15 (1) (2) 18 TC = -55°C to 125°C, VDD1 = 1.7 V to 1.9 V, VDD2 = 3 V to 3.6 V (unless otherwise noted). Parameters ensured by design and/or characterization if not production tested. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SMV512K32-SP SMV512K32-SP www.ti.com SLVSA21H – JUNE 2011 – REVISED JULY 2013 E1Z low/ E2 high GZ tGLMX MBE Data valid BUSYZ tSLMV SCRUBZ tINIT_MBE tBLSL tSLSH Write Control Register tSHBH Assumption: WZ is high Figure 13. Scrub Cycle Controlled by MBE E1Z tETMX MBE low Data valid tSLMV tE1ZHBH BUSYZ tBLBL tE1ZHSH SCRUBZ tINIT_E tBLSL tSLSH tSHBH Assumptions: E2 and GZ are low, WZ is high Figure 14. Scrub Cycle Controlled by E1Z Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SMV512K32-SP 19 SMV512K32-SP SLVSA21H – JUNE 2011 – REVISED JULY 2013 www.ti.com tMLEF tETMH E1Z low E2 high tGHMH tMLGL GZ tMHML MBE tMLAX tAVMH A[10:9] 00 A[12:11], A[8:0] Configuration Data tMHBH BUSYZ Assumptions: SCRUBZ and WZ are high Figure 15. Control Register Write Cycle tETMH tMLEF E1Z low, E2 high tGHMH tMLGL GZ tMHML MBE tETMH tMLAX A[10:9] tMHQV DQ[10:0] tMHQX tEFQZ Control Reg Read Assumptions: SCRUBZ and WZ are high Figure 16. Control Register Read Cycle 20 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SMV512K32-SP SMV512K32-SP www.ti.com SLVSA21H – JUNE 2011 – REVISED JULY 2013 tETMH tMLEF tGHMH tMLGL E1Z low, E2 high GZ tMHML MBE tAVMH A[10:7] tMLAX 1xx1 tMHQV DQ[18:0] tMHQX tEFQZ Current Counter Assumptions: SCRUBZ and WZ are high Figure 17. Address Counter Read Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: SMV512K32-SP 21 PACKAGE OPTION ADDENDUM www.ti.com 6-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 5962-1123701VXC ACTIVE CFP HFG 76 1 TBD Call TI Call TI -55 to 125 SMV512K32HFG 5962-1123701VXC SMV512K32HFG ACTIVE CFP HFG 76 1 TBD Call TI Call TI -55 to 125 SMV512K32HFG 5962-1123701VXC SMV512K32HFG/EM PREVIEW CFP HFG 76 TBD Call TI Call TI 25 Only SMV512K32HFG/EM EVAL ONLY (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. 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