SCAS188A − MAY 1991 − REVISED APRIL 1996
D Members of the Texas Instruments
D
D
D
D
D
D
D
D
D
54ACT16648 . . . WD PACKAGE
74ACT16648 . . . DL PACKAGE
(TOP VIEW)
Widebus Family
Inputs Are TTL-Voltage Compatible
Independent Registers for A and B Buses
Inverting Data Path
Multiplexed Real-Time and Stored Data
Flow-Through Architecture Optimizes
PCB Layout
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
1DIR
1CLKAB
1SAB
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2SAB
2CLKAB
2DIR
description
The ’ACT16648 are 16-bit bus transceivers that
consist of D-type flip-flops and control circuitry
arranged for multiplexed transmission of data
directly from the data bus or from the internal
storage registers. The devices can be used as two
8-bit transceivers or one 16-bit transceiver. Data
on the A or B bus is clocked into the registers on
the low-to-high transition of the appropriate clock
(CLKAB or CLKBA) input. Figure 1 illustrates the
four fundamental bus-management functions that
can be performed with the 74ACT16648.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OE
1CLKBA
1SBA
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2SBA
2CLKBA
2OE
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port can be stored in either register or in both. The
select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry
used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition
between stored and real-time data. DIR determines which bus receives data when OE is low. In the isolation
mode (OE high), A data can be stored in one register and/or B data can be stored in the other register.
When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
The 74ACT16648 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
!"#$%&' #"'(' ')"*%("' #$**&' ( ") +$,-#("' !(&. *"!$# #"')"*% "
+&#)#("' +&* & &*% ") &/( '*$%&' ('!(*! 0(**('1.
*"!$#"' +*"#&'2 !"& '" '&#&(*-1 '#-$!& &'2 ") (-+(*(%&&*.
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•
1
SCAS188A − MAY 1991 − REVISED APRIL 1996
description (continued)
The 54ACT16648 is characterized for operation over the full military temperature range of −55°C to 125°C. The
74ACT16648 is characterized for operation from −40°C to 85°C.
FUNCTION TABLE
(each 8-bit section)
INPUTS
DATA I/O
OE
DIR
CLKAB
CLKBA
SAB
SBA
A1−A8
B1−B8
X
X
↑
X
X
X
Input
Unspecified†
OPERATION OR FUNCTION
X
X
X
↑
X
X
Unspecified†
Input
Store A, B unspecified†
Store B, A unspecified†
H
X
↑
↑
X
X
Input
Input
Store A and B data
H
X
L
L
X
X
Input disabled
Input disabled
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
L
X
H
Output
Input
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B bus
L
H
L
X
H
X
Input
Output
Stored A data to B bus
† The data-output functions may be enabled or disabled by a variety of level combinations at OE and DIR. Data-input functions are always enabled;
i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
2
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•
56
OE
L
1
DIR
L
2
55
3
CLKAB CLKBA SAB
X
X
X
BUS B
BUS A
BUS A
BUS B
SCAS188A − MAY 1991 − REVISED APRIL 1996
56
OE
L
54
SBA
L
1
DIR
H
1
DIR
X
X
X
2
55
3
CLKAB CLKBA SAB
↑
X
↑
X
↑
↑
X
X
X
3
SAB
L
54
SBA
X
BUS B
BUS A
BUS A
56
OE
X
X
H
55
CLKBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
2
CLKAB
X
54
SBA
56
OE
L
L
X
X
X
STORAGE FROM
A, B, OR A AND B
1
DIR
L
H
2
CLKAB
55
CLKBA
3
SAB
54
SBA
X
L
L
X
X
H
H
X
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
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3
SCAS188A − MAY 1991 − REVISED APRIL 1996
logic symbol†
1OE
1DIR
1CLKBA
1SBA
1CLKAB
1SAB
2OE
2DIR
2CLKBA
2SBA
2CLKAB
2SAB
1A1
56
1
55
54
2
3
29
28
30
31
27
26
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
C6
G7
G10
10 EN8 [BA]
10 EN9 [AB]
C11
G12
C13
G14
5
1
≥1
5
6D
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
6
4D
5
2
1 7
51
8
49
9
48
10
47
12
45
13
44
14
43
≥1
15
12 11D
8
1B1
1
≥1
7
52
42
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
12 1
≥1
13D 14
9
2A2
2A3
2A4
2A5
2A6
2A7
2A8
16
1 14
41
17
40
19
38
20
37
21
36
23
34
24
33
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
4
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•
2B2
2B3
2B4
2B5
2B6
2B7
2B8
SCAS188A − MAY 1991 − REVISED APRIL 1996
logic diagram (positive logic)
1OE
56
1
1DIR
55
1CLKBA
1SBA 54
2
1CLKAB
1SAB 3
One of Eight
Channels
1A1
1D
C1
5
52
1B1
1D
C1
To Seven Other Channels
2OE
29
28
2DIR
30
2CLKBA
2SBA 31
27
2CLKAB
2SAB 26
One of Eight
Channels
2A1
1D
C1
15
42
2B1
1D
C1
To Seven Other Channels
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•
5
SCAS188A − MAY 1991 − REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA
Maximum package power dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.4 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54ACT16684
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level output current
IOL
∆t/∆v
Low-level output current
High-level input voltage
2
2
0.8
Input transition rise or fall rate
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
•
V
V
0.8
V
VCC
VCC
V
−24
−24
mA
24
24
mA
VCC
VCC
0
0
V
0
10
0
10
ns/V
125
−40
85
°C
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•
UNIT
−55
')"*%("' #"'#&*' +*"!$# ' & )"*%(3& "*
!&2' +(& ") !&3&-"+%&'. (*(#&*# !(( ('! "&*
+&#)#("' (*& !&2' 2"(-. &/( '*$%&' *&&*3& & *2 "
#('2& "* !#"''$& && +*"!$# 0"$ '"#&.
6
74ACT16684
SCAS188A − MAY 1991 − REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
II
IOZ‡
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
4.5 V
3.94
3.8
3.8
IOH = −24 mA
5.5 V
4.94
4.8
4.8
IOH = −75 mA†
5.5 V
A or B ports
ICC
Control inputs
0.1
VO = VCC or GND
VI = VCC or GND,
IO = 0
VI = VCC or GND
VO = VCC or GND
MAX
MIN
MAX
UNIT
V
3.85
0.1
0.1
5.5 V
0.1
0.1
0.1
4.5 V
0.36
0.44
0.44
5.5 V
0.36
0.44
0.44
1.65
1.65
±1
±1
µA
5.5 V
One input at 3.4 V,
Other inputs at VCC or GND
∆ICC§
Ci
IOL = 75 mA†
VI = VCC or GND
MIN
3.85
4.5 V
IOL = 24 mA
Control inputs
74ACT16648
4.5 V
IOL = 50 µA
A
VOL
54ACT16648
MIN
IOH = −50 µA
A
VOH
TA = 25°C
TYP
MAX
VCC
V
5.5 V
±0.1
5.5 V
±0.5
±5
±5
µA
5.5 V
8
80
80
µA
5.5 V
0.9
1
1
mA
5V
4
pF
Cio
A or B ports
5V
12
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
§ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
pF
timing requirements over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
TA = 25°C
MIN
MAX
0
MIN
MAX
0
75
74ACT16648
MIN
MAX
0
75
UNIT
fclock
tw
Clock frequency
Pulse duration, CLKAB or CLKBA high or low
6.5
6.5
6.5
ns
tsu
th
Setup time, A before CLKAB↑ or B before CLKBA↑
4.5
4.5
4.5
ns
1
1
1
ns
Hold time, A after CLKAB↑ or B after CLKBA↑
75
54ACT16648
MHz
')"*%("' #"'#&*' +*"!$# ' & )"*%(3& "*
!&2' +(& ") !&3&-"+%&'. (*(#&*# !(( ('! "&*
+&#)#("' (*& !&2' 2"(-. &/( '*$%&' *&&*3& & *2 "
#('2& "* !#"''$& && +*"!$# 0"$ '"#&.
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7
SCAS188A − MAY 1991 − REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
MIN
TA = 25°C
TYP
MAX
75
A or B
B or A
OE
A or B
OE
A or B
CLKBA or CLKAB
A or B
SBA or SAB†
(with A or B high)
A or B
SBA or SAB†
(with A or B low)
A or B
DIR
A or B
DIR
A or B
54ACT16648
MIN
74ACT16648
MAX
MIN
75
MAX
75
UNIT
MHz
2.4
7.2
9.8
2.4
11
2.4
11
3.8
7.7
10.1
3.8
11.2
3.8
11.2
2.9
7.9
10.7
2.9
12
2.9
12
3.6
9.1
12.1
3.6
13.7
3.6
13.7
5.2
8.1
9.7
5.2
10.4
5.2
10.4
4.7
7.3
9.1
4.7
9.9
4.7
9.9
4.4
8.5
11.3
4.4
12.7
4.4
12.7
4.6
8.8
11.4
4.6
12.7
4.6
12.7
3.8
7.5
10
3.8
11.3
3.8
11.3
5.1
11.4
12.7
5.1
16.6
5.1
16.6
4.5
10.6
13.9
4.5
15.8
4.5
15.8
4.3
8.3
10.8
4.3
11.9
4.3
11.9
2.8
7.8
10.7
2.8
11.9
2.8
11.9
3.7
9.3
12.2
3.7
13.7
3.7
13.7
4.6
8.6
10.9
4.6
11.5
4.6
11.5
4
7.4
9.7
4
10.4
4
10.4
ns
ns
ns
ns
ns
ns
ns
ns
† These parameters are measured with the internal output state of the storage registers opposite that of the bus input.
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
Outputs enabled
Cpd
Power dissipation capacitance per transceiver
Outputs disabled
')"*%("' #"'#&*' +*"!$# ' & )"*%(3& "*
!&2' +(& ") !&3&-"+%&'. (*(#&*# !(( ('! "&*
+&#)#("' (*& !&2' 2"(-. &/( '*$%&' *&&*3& & *2 "
#('2& "* !#"''$& && +*"!$# 0"$ '"#&.
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•
TYP
UNIT
63
CL = 50 pF,
f = 1 MHz
14
pF
SCAS188A − MAY 1991 − REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
500 Ω
LOAD CIRCUIT
3V
Timing Input
(see Note B)
1.5 V
0V
tw
tsu
3V
Input
1.5 V
th
1.5 V
3V
1.5 V
1.5 V
Data Input
0V
0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3V
Input
1.5 V
1.5 V
0V
tPHL
tPLH
In-Phase
Output
tPLH
tPHL
Out-of-Phase
Output
Output
Waveform 2
S1 at GND
(see Note B)
VOH
50% VCC
VOL
50% VCC
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
50% VCC
VOL
50% VCC
3V
1.5 V
1.5 V
50% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
[ VCC
20% VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
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•
9
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