WINBOND W25X64V

W25X64
64M-BIT
SERIAL FLASH MEMORY WITH
4KB SECTORS AND DUAL OUTPUT SPI
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Publication Release Date: December 19, 2008
Revision A
W25X64
Table of Contents
1
GENERAL DESCRIPTION................................................................................................... 4
2
FEATURES........................................................................................................................ 4
3
PIN CONFIGURATION WSON 8X6-MM ................................................................................ 5
4
PIN CONFIGURATION PDIP 300-MIL ................................................................................... 5
5
PIN DESCRIPTION PDIP 300-MIL, WSON 8X6...................................................................... 6
6
PIN CONFIGURATION SOIC 300-MIL ................................................................................... 6
7
PIN DESCRIPTION SOIC 300-MIL........................................................................................ 7
7.1
Package Types ....................................................................................................... 8
7.2
Chip Select (/CS) .................................................................................................... 8
7.3
Serial Data Output (DO)........................................................................................... 8
7.4
Write Protect (/WP)................................................................................................. 8
7.5
HOLD (/HOLD)........................................................................................................ 8
7.6
Serial Clock (CLK)................................................................................................... 8
7.7
Serial Data Input / Output (DIO) ................................................................................ 8
8
BLOCK DIAGRAM.............................................................................................................. 9
9
FUNCTIONAL DESCRIPTION .............................................................................................10
9.1
9.2
SPI OPERATIONS .................................................................................................10
9.1.1
SPI Modes ....................................................................................................................................10
9.1.2
Dual Output SPI...........................................................................................................................10
9.1.3
Hold Function ..............................................................................................................................10
WRITE PROTECTION.............................................................................................11
9.2.1
10
Write Protect Features ...............................................................................................................11
CONTROL AND STATUS REGISTERS ................................................................................12
10.1
10.2
STATUS REGISTER...............................................................................................12
10.1.1
BUSY...........................................................................................................................................12
10.1.2
Write Enable Latch (WEL).......................................................................................................12
10.1.3
Block Protect Bits (BP2, BP1, BP0) .......................................................................................12
10.1.4
Top/Bottom Block Protect (TB) ...............................................................................................12
10.1.5
Reserved Bits ............................................................................................................................12
10.1.6
Status Register Protect (SRP)................................................................................................13
10.1.7
Status Register Memory Protection.......................................................................................13
INSTRUCTIONS .....................................................................................................14
10.2.1
Manufacturer and Device Identification.................................................................................14
10.2.2
Instruction Set............................................................................................................................15
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W25X64
11
12
10.2.3
Write Enable (06h)....................................................................................................................16
10.2.4
Write Disable (04h) ..................................................................................................................16
10.2.5
Read Status Register (05h)....................................................................................................17
10.2.6
Write Status Register (01h) ....................................................................................................18
10.2.7
Read Data (03h) .......................................................................................................................19
10.2.8
Fast Read (0Bh)........................................................................................................................20
10.2.9
Fast Read Dual Output (3Bh).................................................................................................21
10.2.10
Page Program (02h)..............................................................................................................22
10.2.11
Sector Erase (20h).................................................................................................................23
10.2.12
Block Erase (D8h)..................................................................................................................24
10.2.13
Chip Erase (C7h) ...................................................................................................................25
10.2.14
Power-down (B9h) .................................................................................................................26
10.2.15
Release Power-down / Device ID (ABh) ............................................................................27
10.2.16
Read Manufacturer / Device ID (90h)..................................................................................29
10.2.17
JEDEC ID (9Fh) ......................................................................................................................30
ELECTRICAL CHARACTERISTICS......................................................................................31
11.1
Absolute Maximum Ratings ....................................................................................31
11.2
Operating Ranges ..................................................................................................31
11.3
Power-up Timing and Write Inhibit Threshold.............................................................32
11.4
DC Electrical Characteristics...................................................................................33
11.5
AC Measurement Conditions ...................................................................................35
11.6
AC Electrical Characteristics...................................................................................36
11.7
AC Electrical Characteristics (cont’d).......................................................................37
11.8
Serial Output Timing...............................................................................................38
11.9
Input Timing...........................................................................................................38
11.10
Hold Timing ..........................................................................................................38
PACKAGE SPECIFICATION...............................................................................................39
12.1
8-Pin PDIP 300-mil (Package Code DA) ...................................................................39
12.2
8-Contact 8x6mm WSON (Package Code ZE) ..........................................................40
12.3
16-Pin SOIC 300-mil (Winbond Package Code SF)....................................................41
13
ORDERING INFORMATION (1) ............................................................................................42
14
REVISION HISTORY..........................................................................................................44
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Publication Release Date: December 19, 2008
Revision A
W25X64
1
GENERAL DESCRIPTION
The W25X64 (64M-bit) Serial Flash memory provide a storage solution for systems with limited space,
pins and power. The 25X series offers flexibility and performance well beyond ordinary Serial Flash
devices. They are ideal for code download applications as well as storing voice, text and data. The
devices operate on a single 2.7V to 3.6V power supply with current consumption as low as 5mA active
and 1µA for power-down. All devices are offered in space-saving packages.
The W25X64 array is organized into 32,768 programmable pages of 256-bytes each. Up to 256 bytes can
be programmed at a time using the Page Program instruction. Pages can be erased in groups of 16
(sector erase), groups of 256 (block erase) or the entire chip (chip erase). The W25X64 has 2048
erasable sectors and 128 erasable blocks. The small 4KB sectors allow for greater flexibility in
applications that require data and parameter storage. (See figure 2.)
The W25X64 supports the standard Serial Peripheral Interface (SPI), and a high performance dual output
SPI using four pins: Serial Clock, Chip Select, Serial Data I/O and Serial Data Out. SPI clock
frequencies of up to 75MHz are supported allowing equivalent clock rates of 150MHz when using the
Fast Read Dual Output instruction. These transfer rates are comparable to those of 8 and 16-bit Parallel
Flash memories.
A Hold pin, Write Protect pin and programmable write protect, with top or bottom array control features,
provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and
device identification.
2 FEATURES
– More than 100,000 erase/write cycles
– More than 20-year retention
• Family of Serial Flash Memories
– W25X64: 64M-bit / 8M-byte (8,388,608)
– 256-bytes per programmable page
– Uniform 4K-byte Sectors / 64K-byte Blocks
• Low Power Consumption, Wide
Temperature Range
– Single 2.7 to 3.6V supply
– 5mA active current, 1µA Power-down (typ)
– -40° to +85°C operating range
• SPI with Single or Dual Outputs
– Clock, Chip Select, Data I/O, Data Out
– Optional Hold function for SPI flexibility
• Software and Hardware Write Protection
– Write-Protect all or portion of memory
– Enable/Disable protection with /WP pin
– Top or bottom array protection
• Data Transfer up to 150-bits / second
– Clock operation to 75MHz
– Fast Read Dual Output instruction
– Auto-increment Read capability
• Space Efficient Packaging
– 8-pin PDIP 300-mil
– 16-pin SOIC 300-mil
– 8-pad WSON 8x6-mm
• Flexible Architecture with 4KB sectors
– Sector Erase (4K-bytes)
– Block Erase (64K-byte)
– Page program up to 256 bytes <2ms
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W25X64
3
PIN CONFIGURATION WSON 8X6-MM
Figure 1b. W25X64 Pad Assignments, 8-pad WSON 8x6-mm (Package Code ZE)
4
PIN CONFIGURATION PDIP 300-MIL
Figure 1c. W25X64 Pin Assignments, 8-pin PDIP (Package Code DA)
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Publication Release Date: December 19, 2008
Revision A
W25X64
5
6
PIN DESCRIPTION PDIP 300-MIL, WSON 8X6
PIN NO.
PIN NAME
I/O
FUNCTION
1
/CS
I
Chip Select Input
2
DO
O
Data Output
3
/WP
I
Write Protect Input
4
GND
5
DIO
I/O
6
CLK
I
Serial Clock Input
7
/HOLD
I
Hold Input
8
VCC
Ground
Data Input / Output
Power Supply
PIN CONFIGURATION SOIC 300-MIL
Figure 1d. W25X64 Pin Assignments, 16-pin SOIC 300-mil
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W25X64
7
PIN DESCRIPTION SOIC 300-MIL
PIN NO.
PIN NAME
I/O
FUNCTION
1
/HOLD
I
2
VCC
Power Supply
3
N/C
No Connect
4
N/C
No Connect
5
N/C
No Connect
6
N/C
No Connect
7
/CS
I
Chip Select Input
8
DO
O
Data Output
9
/WP
I
Write Protect Input
10
GND
Ground
11
N/C
No Connect
12
N/C
No Connect
13
N/C
No Connect
14
N/C
No Connect
15
DIO
I/O
16
CLK
I
Hold Input
Data Input / Output
Serial Clock Input
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Publication Release Date: December 19, 2008
Revision A
W25X64
7.1
Package Types
At the time this datasheet was published not all package types had been finalized. Contact Winbond to
confirm availability of these packages before designing to this specification. W25X64 is offered in an
8x6-mm WSON (package code ZE), 16-pin plastic 300-mil width SOIC (package code SF) and 300-mil
DIP (package code DA). See figures 1a-d. Package diagrams and dimensions are illustrated at the end
of this datasheet.
7.2
Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the devices
power consumption will be at standby levels unless an internal erase, program or status register cycle is
in progress. When /CS is brought low the device will be selected, power consumption will increase to
active levels and instructions can be written to and data read from the device. After power-up, /CS must
transition from high to low before a new instruction will be accepted. The /CS input must track the VCC
supply level at power-up (see “Write Protection” and figure 20). If needed a pull-up resister on /CS can be
used to accomplish this.
7.3
Serial Data Output (DO)
The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from
(shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.
7.4
Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP2, BP1, and BP0) bits and Status Register
Protect (SRP) bits, a portion or the entire memory array can be hardware protected. The /WP pin is
active low.
7.5
HOLD (/HOLD)
The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low,
while /CS is low, the DO pin will be at high impedance and signals on the DIO and CLK pins will be
ignored (don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can
be useful when multiple devices are sharing the same SPI signals. (“See Hold function”)
7.6
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI
Operations")
7.7
Serial Data Input / Output (DIO)
The SPI Serial Data Input/Output (DIO) pin provides a means for instructions, addresses and data to be
serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK)
input pin. The DIO pin is also used as an output when the Fast Read Dual Output instruction is
executed.
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W25X64
8 BLOCK DIAGRAM
Figure 2. W25X64 Block Diagram
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Publication Release Date: December 19, 2008
Revision A
W25X64
9
FUNCTIONAL DESCRIPTION
9.1
9.1.1
SPI OPERATIONS
SPI Modes
The W25X64 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),
Chip Select (/CS), Serial Data Input/Output (DIO) and Serial Data Output (DO). Both SPI bus operation
Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3 concerns
the normal state of the CLK signal when the SPI bus master is in standby and data is not being
transferred to the Serial Flash. For Mode 0 the CLK signal is normally low. For Mode 3 the CLK signal is
normally high. In either case data input on the DIO pin is sampled on the rising edge of the CLK. Data on
the DO and DIO pins are clocked out on the falling edge of CLK.
9.1.2
Dual Output SPI
The W25X64 supports Dual output operation when using the "Fast Read with Dual Output" (3B hex)
instruction. This feature allows data to be transferred from the Serial Flash memory at twice the rate
possible with the standard SPI. This instruction is ideal for quickly downloading code from Flash to RAM
upon power-up (code-shadowing) or for applications that cache code-segments to RAM for execution.
The Dual output feature simply allows the SPI input pin to also serve as an output during this instruction.
All other operations use the standard SPI interface with single output signal.
9.1.3
Hold Function
The /HOLD signal allows the W25X64 operation to be paused while it is actively selected (when /CS is
low). The /HOLD function may be useful in cases where the SPI data and clock signals are shared with
other devices. For example, consider if the page buffer was only partially written when a priority interrupt
requires use of the SPI bus. In this case the /HOLD function can save the state of the instruction and the
data in the buffer so programming can resume where it left off once the bus is available again.
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate
on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the
/HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the
rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD
condition will terminate after the next falling edge of CLK.
During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data Input/Output
(DIO) and Serial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept active (low) for the
full duration of the /HOLD operation to avoid resetting the internal logic state of the device.
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W25X64
9.2
WRITE PROTECTION
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the W25X64
provides several means to protect data from inadvertent writes.
9.2.1
Write Protect Features
•
Device resets when VCC is below threshold.
•
Time delay write disable after Power-up.
•
Write enable/disable instructions.
•
Automatic write disable after program and erase.
•
Software write protection using Status Register.
•
Hardware write protection using Status Register and /WP pin.
•
Write Protection using Power-down instruction.
Upon power-up or at power-down the W25X64 will maintain a reset condition while VCC is below the
threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 20). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC voltage
exceeds VWI, all program and erase related instructions are further disabled for a time delay of t PUW. This
includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status
Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up
until the VCC-min level and t VSL time delay is reached. If needed a pull-up resister on /CS can be used
to accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program,
Sector Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a
program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a writedisabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting
the Status Register Protect (SRP) and Block Protect (TB, BP2, BP1, and BP0) bits. These Status
Register bits allow a portion or all of the memory to be configured as read only. Used in conjunction with
the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware
control. See Status Register for further information.
Additionally, the Power-down instruction offers an extra level of write protection as all instructions are
ignored except for the Release Power-down instruction.
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Publication Release Date: December 19, 2008
Revision A
W25X64
10
CONTROL AND STATUS REGISTERS
The Read Status Register instruction can be used to provide status on the availability of the Flash
memory array, if the device is write enabled or disabled, and the state of write protection. The Write
Status Register instruction can be used to configure the devices write protection features. See Figure 3.
10.1 STATUS REGISTER
10.1.1 BUSY
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a
Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction. During this
time the device will ignore further instructions except for the Read Status Register instruction (see t W,
t PP, tSE, t BE, and t CE in AC Characteristics). When the program, erase or write status register instruction
has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further
instructions.
10.1.2 Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after executing a
Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is write disabled. A write
disable state occurs upon power-up or after any of the following instructions: Write Disable, Page
Program, Sector Erase, Block Erase, Chip Erase and Write Status Register.
10.1.3 Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, and BP0) are non-volatile read/write bits in the status register (S4,
S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using the
Write Status Register Instruction (see t W in AC characteristics). All, none or a portion of the memory
array can be protected from Program and Erase instructions (see Status Register Memory Protection
table). The factory default setting for the Block Protection Bits is 0, none of the array protected. The
Block Protect bits can not be written to if the Status Register Protect (SRP) bit is set to 1 and the Write
Protect (/WP) pin is low.
10.1.4 Top/Bottom Block Protect (TB)
The Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top (TB=0)
or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The TB bit
is non-volatile and the factory default setting is TB=0. The TB bit can be set with the Write Status
Register Instruction provided that the Write Enable instruction has been issued. The TB bit can not be
written to if the Status Register Protect (SRP) bit is set to 1 and the Write Protect (/WP) pin is low.
10.1.5 Reserved Bits
Status register bit location S6 is reserved for future use. Current devices will read 0 for this bit location. It
is recommended to mask out the reserved bit when testing the Status Register. Doing this will ensure
compatibility with future devices.
- 12 -
W25X64
10.1.6 Status Register Protect (SRP)
The Status Register Protect (SRP) bit is a non-volatile read/write bit in status register (S7) that can be
used in conjunction with the Write Protect (/WP) pin to disable writes to status register. When the SRP
bit is set to a 0 state (factory default) the /WP pin has no control over status register. When the SRP pin
is set to a 1, the Write Status Register instruction is locked out while the /WP pin is low. When the /WP
pin is high the Write Status Register instruction is allowed.
Figure 3. Status Register Bit Locations
10.1.7 Status Register Memory Protection
STATUS REGISTER(1)
TB
x
0
0
0
0
0
0
1
1
1
1
1
1
x
BP2
0
0
0
0
1
1
1
0
0
0
1
1
1
1
BP1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
BP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
W25X64 (64M-BIT) MEMORY PROTECTION
BLOCK(S)
NONE
126 and 127
124 and 127
120 thru 127
112 thru 127
96 thru 127
64 thru 127
0 and 1
0 thru 3
0 thru 7
0 thru 15
0 thru 31
0 thru 63
0 thru 127
ADDRESSES
NONE
7E0000h - 7FFFFFh
7C0000h - 7FFFFFh
780000h - 7FFFFFh
700000h - 7FFFFFh
600000h - 7FFFFFh
400000h - 7FFFFFh
000000h - 01FFFFh
000000h - 03FFFFh
000000h - 07FFFFh
000000h – 0FFFFFh
000000h – 1FFFFFh
000000h – 3FFFFFh
000000h - 7FFFFFh
DENSITY
NONE
128KB
256KB
512KB
1MB
2MB
4MB
128KB
256KB
512KB
1MB
2MB
4MB
8MB
PORTION
NONE
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
Lower 1/64
Lower 1/32
Lower 1/16
Lower 1/8
Lower 1/4
Lower 1/2
ALL
Note:
1. x = don’t care
- 13 -
Publication Release Date: December 19, 2008
Revision A
W25X64
10.2 INSTRUCTIONS
The instruction set of the W25X64 consists of fifteen basic instructions that are fully controlled through
the SPI bus (see Instruction Set table). Instructions are initiated with the falling edge of Chip Select
(/CS). The first byte of data clocked into the DIO input provides the instruction code. Data on the DIO
input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes,
data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed
with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in
figures 4 through 19. All read instructions can be completed after any clocked bit. However, all
instructions that Write, Program or Erase must complete on a byte boundary (CS driven high after a full
8-bits have been clocked) otherwise the instruction will be terminated. This feature further protects the
device from inadvertent writes. Additionally, while the memory is being programmed or erased, or when
the Status Register is being written, all instructions except for Read Status Register will be ignored until
the program or erase cycle has completed.
10.2.1 Manufacturer and Device Identification
MANUFACTURER ID
(M7-M0)
Winbond Serial Flash
EFH
Device ID
(ID7-ID0)
(ID15-ID0)
Instruction
ABh, 90h
9Fh
W25X64
16h
3017h
- 14 -
W25X64
10.2.2 Instruction Set
INSTRUCTION
NAME
BYTE 1
CODE
Write Enable
06h
Write Disable
Read Status
Register
Write Status
Register
Read Data
04h
Fast Read
(1)
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
05h
(S7–S0)(1)
01h
S7–S0
03h
A23–A16
A15–A8
A7–A0
(D7–D0)
(Next byte)
0Bh
A23–A16
A15–A8
A7–A0
dummy
(D7–D0)
N-BYTES
(2)
Fast Read Dual
Output
3Bh
A23–A16
A15–A8
A7–A0
dummy
I/O =
(D6,D4,D2,D0)
O=
(D7,D5,D3,D1)
Page Program
02h
A23–A16
A15–A8
A7–A0
(D7–D0)
(Next byte)
D8h
A23–A16
A15–A8
A7–A0
20h
A23–A16
A15–A8
A7–A0
ABh
dummy
dummy
dummy
(ID7-ID0)(4)
(M7-M0)
Block Erase
(64KB)
Sector Erase
(4KB)
Chip Erase
Power-down
Release Powerdown / Device ID
Manufacturer/
Device ID (3)
C7h
B9h
90h
dummy
dummy
00h
JEDEC ID
9Fh
(M7-M0)
Manufacturer
(ID15-ID8)
Memory
Type
(ID7-ID0)
Capacity
continuous
(Next Byte)
continuous
(one byte
per 4
clocks,
continuous)
Up to 256
bytes
(ID7-ID0)
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data
being read from the device on the DO pin.
2. The Status Register contents will repeat continuously until /CS terminates the instruction.
3. See Manufacturer and Device Identification table for Device ID information.
4. The Device ID will repeat continuously until /CS terminates the instruction.
- 15 -
Publication Release Date: December 19, 2008
Revision A
W25X64
10.2.3 Write Enable (06h)
The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register to a
1. The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase and
Write Status Register instruction. The Write Enable instruction is entered by driving /CS low, shifting the
instruction code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then driving /CS high.
Figure 4. Write Enable Instruction Sequence Diagram
10.2.4 Write Disable (04h)
The Write Dissable instruction (Figure 5) resets the Write Enable Latch (WEL) bit in the Status Register
to a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into
the DIO pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and
upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip
Erase instructions.
Figure 5. Write Disable Instruction Sequence Diagram
- 16 -
W25X64
10.2.5 Read Status Register (05h)
The Read Status Register instruction allows the 8-bit Status Register to be read. The instruction is
entered by driving /CS low and shifting the instruction code “05h” into the DIO pin on the rising edge of
CLK. The status register bits are then shifted out on the DO pin at the falling edge of CLK with most
significant bit (MSB) first as shown in figure 6. The Status Register bits are shown in figure 3 and include
the BUSY, WEL, BP2-BP0, TB and SRP bits (see description of the Status Register earlier in this
datasheet).
The Status Register instruction may be used at any time, even while a Program, Erase or Write Status
Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the
cycle is complete and if the device can accept another instruction. The Status Register can be read
continuously, as shown in Figure 6. The instruction is completed by driving /CS high.
Figure 6. Read Status Register Instruction Sequence Diagram
- 17 -
Publication Release Date: December 19, 2008
Revision A
W25X64
10.2.6 Write Status Register (01h)
The Write Status Register instruction allows the Status Register to be written. A Write Enable instruction
must previously have been executed for the device to accept the Write Status Register Instruction
(Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by driving /CS
low, sending the instruction code “01h”, and then writing the status register data byte as illustrated in
figure 7. The Status Register bits are shown in figure 3 and described earlier in this datasheet.
Only non-volatile Status Register bits SRP, TB, BP2, BP1 and BP0 (bits 7, 5, 4, 3 and 2) can be written
to. All other Status Register bit locations are read-only and will not be affected by the Write Status
Register instruction.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done
the Write Status Register instruction will not be executed. After /CS is driven high, the self-timed Write
Status Register cycle will commence for a time duration of t W (See AC Characteristics). While the Write
Status Register cycle is in progress, the Read Status Register instruction may still accessed to check
the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a 0 when the
cycle is finished and ready to accept other instructions again. After the Write Register cycle has finished
the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.
The Write Status Register instruction allows the Block Protect bits (TB, BP2, BP1 and BP0) to be set for
protecting all, a portion, or none of the memory from erase and program instructions. Protected areas
become read-only (see Status Register Memory Protection table). The Write Status Register instruction
also allows the Status Register Protect bit (SRP) to be set. This bit is used in conjunction with the Write
Protect (/WP) pin to disable writes to the status register. When the SRP bit is set to a 0 state (factory
default) the /WP pin has no control over the status register. When the SRP pin is set to a 1, the Write
Status Register instruction is locked out while the /WP pin is low. When the /WP pin is high the Write
Status Register instruction is allowed.
Figure 7. Write Status Register Instruction Sequence Diagram
- 18 -
W25X64
10.2.7 Read Data (03h)
The Read Data instruction allows one more data bytes to be sequentially read from the memory. The
instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h” followed by
a 24-bit address (A23-A0) into the DIO pin. The code and address bits are latched on the rising edge of
the CLK pin. After the address is received, the data byte of the addressed memory location will be
shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is
automatically incremented to the next higher address after each byte of data is shifted out allowing for a
continuous stream of data. This means that the entire memory can be accessed with a single instruction
as long as the clock continues. The instruction is completed by driving /CS high. The Read Data
instruction sequence is shown in figure 8. If a Read Data instruction is issued while an Erase, Program
or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the
current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of fR (see AC
Electrical Characteristics).
Figure 8. Read Data Instruction Sequence Diagram
- 19 -
Publication Release Date: December 19, 2008
Revision A
W25X64
10.2.8 Fast Read (0Bh)
The Fast Read instruction is similar to the Read Data instruction except that it can operate at the
highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding
eight “dummy” clocks after the 24-bit address as shown in figure 9. The dummy clocks allow the devices
internal circuits additional time for setting up the initial address. During the dummy clocks the data value
on the DIO pin is a “don’t care”.
Figure 9. Fast Read Instruction Sequence Diagram
- 20 -
W25X64
10.2.9 Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction
except that data is output on two pins, DO and DIO, instead of just DO. This allows data to be
transferred from the W25X64 at twice the rate of standard SPI devices. The Fast Read Dual Output
instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for applications
that cache code-segments to RAM for execution.
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight
“dummy” clocks after the 24-bit address as shown in figure 10. The dummy clocks allow the device's
internal circuits additional time for setting up the initial address. The input data during the dummy clocks
is “don’t care”. However, the DIO pin should be high-impedance prior to the falling edge of the first data
out clock.
Figure 10. Fast Read Dual Output Instruction Sequence Diagram
- 21 -
Publication Release Date: December 19, 2008
Revision A
W25X64
10.2.10 Page Program (02h)
The Page Program instruction allows up to 256 bytes of data to be programmed at previously erased to
all 1s (FFh) memory locations. A Write Enable instruction must be executed before the device will
accept the Page Program Instruction (Status Register bit WEL must equal 1). The instruction is initiated
by driving the /CS pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0)
and at least one data byte, into the DIO pin. The /CS pin must be held low for the entire length of the
instruction while data is being sent to the device. The Page Program instruction sequence is shown in
figure 11.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address
bits) should be set to 0. If the last address byte is not zero, and the number of clocks exceed the
remaining page length, the addressing will wrap to the beginning of the page. In some cases, less than
256 bytes (a partial page) can be programmed without having any effect on other bytes within the same
page. One condition to perform a partial page program is that the number of clocks can not exceed the
remaining page length. If more than 256 bytes are sent to the device the addressing will wrap to the
beginning of the page and overwrite previously sent data.
As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last
byte has been latched. If this is not done the Page Program instruction will not be executed. After /CS is
driven high, the self-timed Page Program instruction will commence for a time duration of tpp (See AC
Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may
still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program
cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions
again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status
Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is
protected by the Block Protect (BP2, BP1, and BP0) bits (see Status Register Memory Protection
table).
Figure 11. Page Program Instruction Sequence Diagram
- 22 -
W25X64
10.2.11 Sector Erase (20h)
The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of
all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “20h” followed a 24-bit sector address (A23-A0) (see Figure 2). The
Sector Erase instruction sequence is shown in figure 12.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done
the Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector Erase
instruction will commence for a time duration of t SE (See AC Characteristics). While the Sector Erase
cycle is in progress, the Read Status Register instruction may still be accessed for checking the status
of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is
finished and the device is ready to accept other instructions again. After the Sector Erase cycle has
finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase
instruction will not be executed if the addressed page is protected by the Block Protect (TB, BP2, BP1,
and BP0) bits (see Status Register Memory Protection table).
Figure 12. Sector Erase Instruction Sequence Diagram
- 23 -
Publication Release Date: December 19, 2008
Revision A
W25X64
10.2.12 Block Erase (D8h)
The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of
all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0) (see Figure 2). The
Block Erase instruction sequence is shown in figure 13.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done
the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase
instruction will commence for a time duration of t BE (See AC Characteristics). While the Block Erase
cycle is in progress, the Read Status Register instruction may still be accessed for checking the status
of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is
finished and the device is ready to accept other instructions again. After the Block Erase cycle has
finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase
instruction will not be executed if the addressed page is protected by the Block Protect (TB, BP2, BP1,
and BP0) bits (see Status Register Memory Protection table).
Figure 13. Block Erase Instruction Sequence Diagram
- 24 -
W25X64
10.2.13 Chip Erase (C7h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write
Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status
Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the
instruction code “C7h”. The Chip Erase instruction sequence is shown in figure 14.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase
instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will
commence for a time duration of t CE (See AC Characteristics). While the Chip Erase cycle is in
progress, the Read Status Register instruction may still be accessed to check the status of the BUSY
bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is
ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable Latch
(WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed if any
page is protected by the Block Protect (BP2, BP1, and BP0) bits (see Status Register Memory
Protection table).
Figure 14. Chip Erase Instruction Sequence Diagram
- 25 -
Publication Release Date: December 19, 2008
Revision A
W25X64
10.2.14 Power-down (B9h)
Although the standby current during normal operation is relatively low, standby current can be further
reduced with the Power-down instruction. The lower power consumption makes the Power-down
instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC Characteristics).
The instruction is initiated by driving the /CS pin low and shifting the instruction code “B9h” as shown in
figure 15.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power-down
instruction will not be executed. After /CS is driven high, the power-down state will entered within the
time duration of t DP (See AC Characteristics). While in the power-down state only the Release from
Power-down / Device ID instruction, which restores the device to normal operation, will be recognized. All
other instructions are ignored. This includes the Read Status Register instruction, which is always
available during normal operation. Ignoring all but one instruction makes the Power Down state a useful
condition for securing maximum write protection. The device always powers-up in the normal operation
with the standby current of ICC1.
Figure 15. Deep Pow er-dow n Instruction Sequence Diagram
- 26 -
W25X64
10.2.15 Release Power-down / Device ID (ABh)
The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to
release the device from the power-down state, obtain the devices electronic identification (ID) number or
do both.
When used only to release the device from the power-down state, the instruction is issued by driving the
/CS pin low, shifting the instruction code “ABh” and driving /CS high as shown in figure 16. After the time
duration of t RES1 (See AC Characteristics) the device will resume normal operation and other instructions
will be accepted. The /CS pin must remain high during the t RES1 time duration.
When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by
driving the /CS pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device ID
bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure
17. The Device ID value for the W25X64 is listed in Manufacturer and Device Identification table. The
Device ID can be read continuously. The instruction is completed by driving /CS high.
When used to release the device from the power-down state and obtain the Device ID, the instruction is
the same as previously described, and shown in figure 17, except that after /CS is driven high it must
remain high for a time duration of t RES2 (See AC Characteristics). After this time duration the device will
resume normal operation and other instructions will be accepted.
If the Release from Power-down / Device ID instruction is issued while an Erase, Program or Write cycle
is in process (when BUSY equals 1) the instruction is ignored and will not have any effects on the current
cycle
Figure 16. Release Pow er-dow n Instruction Sequence
- 27 -
Publication Release Date: December 19, 2008
Revision A
W25X64
Figure 17. Release Pow er-dow n / Device ID Instruction Sequence Diagram
Note: ** See Section 10.2.1
- 28 -
W25X64
10.2.16 Read Manufacturer / Device ID (90h)
The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device
ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID.
The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device ID
instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code “90h”
followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Winbond (EFh)
and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown
in figure 18. The Device ID value for the W25X64 is listed in Manufacturer and Device Identification table.
If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the
Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the
other. The instruction is completed by driving /CS high.
Figure 18. Read Manufacturer / Device ID Diagram
Note: ** See Section 10.2.1
- 29 -
Publication Release Date: December 19, 2008
Revision A
W25X64
10.2.17 JEDEC ID (9Fh)
For compatibility reasons, the W25X64 provides several instructions to electronically determine the
identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI
compatible serial memories that was adopted in 2003.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “9Fh”. The JEDEC
assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type (ID15-ID8) and
Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant bit (MSB) first as
shown in figure 19. For memory type and capacity values refer to Manufacturer and Device Identification
table.
Figure 19. Read JEDEC ID
- 30 -
W25X64
11 ELECTRICAL CHARACTERISTICS
11.1 Absolute Maximum Ratings (1)
PARAMETERS
SYMBO
L
Supply Voltage
VCC
Voltage applied to any Pin
VIO
Transient Voltage on any Pin
VIOT
Storage Temperature
TSTG
Lead Temperature
CONDITIONS
VESD
UNIT
–0.6 to +4.0
V
Relative to Ground
–0.6 to VCC +0.4
V
<20nS Transient
Relative to Ground
–2.0V to VCC+2.0V
V
–65 to +150
°C
(2)
°C
TLEAD
Electrostatic Discharge Voltage
RANGE
See Note
Human Body
Model(3)
–2000 to +2000
V
Notes:
1.
This device has been designed and tested for the specified operation ranges. Proper operation
outside of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device
reliability. Exposure beyond absolute maximum ratings may cause permanent damage.
2.
Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and
the European directive on restrictions on hazardous substances (RoHS) 2002/95/EU.
3.
JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 ohms, R2=500 ohms).
11.2 Operating Ranges
PARAMETER
Supply Voltage
Ambient Temperature,
Operating
SYMBOL
VCC
TA
SPEC
CONDITIONS
UNIT
MIN
MAX
FR = 75MHz, fR = 33MHz
2.7
3.6
V
Industrial
–40
+85
°C
- 31 -
Publication Release Date: December 19, 2008
Revision A
W25X64
11.3 Power-up Timing and Write Inhibit Threshold
PARAMETER
SPEC
SYMBOL
MIN
UNIT
MAX
VCC (min) to /CS Low
t VSL(1)
10
Time Delay Before Write Instruction
t PUW(1)
1
10
ms
Write Inhibit Threshold Voltage
VWI
1
2
V
(1)
Note:
1. These parameters are characterized only.
Figure 20. Pow er-up Timing and Voltage Levels
- 32 -
µs
W25X64
11.4 DC Electrical Characteristics
PARAMETER
SYMBOL
SPEC
CONDITIONS
MIN
Input Capacitance
CIN(1)
Output Capacitance
Cout
Input Leakage
UNIT
TYP
MAX
6
pF
8
pF
ILI
±2
µA
I/O Leakage
ILO
±2
µA
Standby Current
ICC1
/CS = VCC,
VIN = GND or VCC
25
50
µA
Power-down Current
ICC2
/CS = VCC,
VIN = GND or VCC
<1
10
µA
Current Read Data /
Dual Output Read
ICC3
C = 0.1 VCC / 0.9 VCC
DO = Open
5/6
7/8
mA
ICC3
C = 0.1 VCC / 0.9 VCC
DO = Open
7/8
11/12
mA
ICC3
C = 0.1 VCC / 0.9 VCC
DO = Open
9/10
13/15
mA
ICC3
C = 0.1 VCC / 0.9 VCC
DO = Open
11/12
16/18
mA
Current Page
Program
ICC4
/CS = VCC
20
25
mA
Current Write Status
Register
ICC5
/CS = VCC
10
18
mA
Current Sector/Block
Erase
ICC6
/CS = VCC
20
25
mA
Current Chip Erase
ICC7
/CS = VCC
20
25
mA
Input Low Voltage
VIL
–0.5
VCC x 0.3
V
Input High Voltage
VIH
VCC x0.7
VCC +0.4
V
Output Low Voltage
VOL
IOL = 1.6 mA
0.4
V
Output High Voltage
VOH
IOH = –100 µA
1MHz
(2)
Current Read Data /
Dual Output Read
33MHz (2)
Current Read Data /
Dual Output Read
50MHz
(2)
Current Read Data /
Dual Output Read
75MHz (2)
VIN = 0V(2)
(1)
VOUT = 0V
(2)
VCC –0.2
V
Notes:
1. Tested on sample basis and specified through design and characterization data. TA=25° C, VCC 3V.
- 33 -
Publication Release Date: December 19, 2008
Revision A
W25X64
2. Checker Board Pattern.
- 34 -
W25X64
11.5 AC Measurement Conditions
PARAMETER
SPEC
SYMBOL
MIN
Load Capacitance
30
CL
Load Capacitance for FR1 only
Input Rise and Fall Times
15
TR, TF
Input Pulse Voltages
Input Timing Reference Voltages
Output Timing Reference Voltages
UNIT
MAX
5
pF
ns
VIN
0.2 VCC to 0.8 VCC
V
IN
0.3 VCC to 0.7 VCC
V
OUT
0.5 VCC to 0.5 VCC
V
Note:
1. Output Hi-Z is defined as the point w here data out is no longer driven.
Figure 21. AC Measurement I/O Waveform
- 35 -
Publication Release Date: December 19, 2008
Revision A
W25X64
11.6 AC Electrical Characteristics
DESCRIPTION
SYMBOL
SPEC
ALT
MIN
Clock frequency
for all instructions, except Read Data (03h)
2.7V-3.6V VCC & Industrial Temperature
FR
Clock freq. Read Data instruction 03h
fC
TYP
UNIT
MAX
D.C.
75
MHz
fR
D.C.
33
MHz
Clock High, Low Time, for Fast Read (0Bh, 3Bh) /
other instructions except Read Data (03h)
t CLH,
t CLL(1)
6/7
ns
Clock High, Low Time for Read Data (03h)
instruction
t CRLH,
t CRLL(1)
8
ns
Clock Rise Time peak to peak
t CLCH(2)
0.1
V/ns
Clock Fall Time peak to peak
t CHCL(2)
0.1
V/ns
5
ns
5
ns
/CS Active Setup Time relative to CLK
t SLCH
/CS Not Active Hold Time relative to CLK
t CHSL
Data In Setup Time
t DVCH
t DSU
2
ns
Data In Hold Time
t CHDX
t DH
5
ns
/CS Active Hold Time relative to CLK
t CHSH
5
ns
/CS Not Active Setup Time relative to CLK
t SHCH
5
ns
/CS Deselect Time (for Array Read Array Read /
Erase or Program Read Status Register)
t SHSL
t CSH
50/100
ns
t SHQZ(2)
t DIS
7
ns
2.7V-3.6V / 3.0V-3.6V
t CLQV
tV
7/6
ns
Output Hold Time
t CLQX
t HO
Output Disable Time
t CSS
Clock Low to Output Valid
0
ns
Continued – next page
- 36 -
W25X64
11.7 AC Electrical Characteristics (cont’d)
DESCRIPTION
SYMBOL
SPEC
ALT
MIN
TYP
UNIT
MAX
/HOLD Active Setup Time relative to CLK
t HLCH
5
ns
/HOLD Active Hold Time relative to CLK
t CHHH
5
ns
/HOLD Not Active Setup Time relative to CLK
t HHCH
5
ns
/HOLD Not Active Hold Time relative to CLK
t CHHL
5
ns
/HOLD to Output Low-Z
t HHQX(2)
t LZ
7
ns
/HOLD to Output High-Z
t HLQZ(2)
t HZ
12
ns
Write Protect Setup Time Before /CS Low
t WHSL(3)
20
ns
Write Protect Hold Time After /CS High
t SHWL(3)
100
ns
t DP(2)
3
µs
/CS High to Standby Mode without Electronic
Signature Read
t RES1(2)
3
µs
/CS High to Standby Mode with Electronic
Signature Read
t RES2(2)
1.8
µs
/CS High to Power-down Mode
Write Status Register Time
tW
10
15
ms
Byte Program Time (First Byte) (4)
tBP1
30
50
µs
Additional Byte Program Time (After First Byte) (4)
tBP2
6
12
µs
Page Program Time
t PP
1.6
3
ms
Sector Erase Time (4KB)
t SE
150
300
ms
Block Erase Time (64KB)
t BE
.8
2
s
Chip Erase Time W25X64
t CE
25
40
s
Notes:
1.
2.
3.
4.
Clock high + Clock low must be less than or equal to 1/f C .
Value guaranteed by design and/or characterization, not 100% tested in production.
Only applicable as a constraint for a Write Status Register instruction w hen Sector Protect Bit is set to 1.
For multiple bytes after first byte w ithin a page, t BPN = t BP1 + t BP2 * N (typical) and t BPN = t BP1 + t BP2 * N (max), w here N
= number of bytes programmed.
- 37 -
Publication Release Date: December 19, 2008
Revision A
W25X64
11.8 Serial Output Timing
11.9
Input Timing
11.10 Hold Timing
- 38 -
W25X64
12
PACKAGE SPECIFICATION
12.1 8-Pin PDIP 300-mil (Package Code DA)
B1
8
Seating Plane
5
Base Plane
A2
A
E1
L
1
4
A1
e1
S
D
B
E
C
eA
α
SYMBOL
MILLIMETERS
INCHES
MIN
TYP.
MAX
MIN
TYP.
MAX
A
---
---
5.33
---
---
0.210
A1
0.38
---
---
0.015
---
---
A2
3.18
3.30
3.43
0.125
0.130
0.135
B
0.41
0.46
0.56
0.016
0.018
0.022
B1
1.47
1.52
1.63
0.058
0.060
0.064
c
0.20
0.25
0.36
0.008
0.010
0.014
D
9.02
9.27
10.16
0.355
0.365
0.400
E
7.37
7.62
7.87
0.290
0.300
0.310
E1
6.22
6.35
6.48
0.245
0.250
0.255
e1
2.29
2.54
2.79
0.090
0.100
0.110
L
2.92
3.30
3.81
0.115
0.130
0.150
α
0
7
15
0
7
15
eA
8.51
9.02
9.53
0.335
0.355
0.375
S
---
---
1.14
---
---
0.045
- 39 -
Publication Release Date: December 19, 2008
Revision A
W25X64
12.2 8-Contact 8x6mm WSON (Package Code ZE)
E2
L
D
M E TA L PA D A R E A
b
E
D2
(4 )
e
C
A1
MILLIMETERS
SYMBOL
INCHES
MIN
TYP.
MAX
MIN
TYP.
MAX
A
0.70
0.75
0.80
0.0276
0.0295
0.0315
A1
0.00
0.02
0.05
0.0000
0.0008
0.0019
b
0.35
0.40
0.48
0.0138
0.0157
0.0189
C
0.19
.0.20
0.25
0.0075
0.0079
0.0098
D
7.90
8.00
8.10
0.3110
0.3150
0.3189
D2
4.60
4.65
4.70
0.1811
0.1831
0.1850
E
5.90
6.00
6.10
0.2323
0.2362
0.2402
E2
5.15
5.20
5.25
0.2028
0.2047
0.2067
e
L
1.27 BSC
0.45
0.50
0.0500 BSC
0.55
- 40 -
0.0177
0.0197
0.0217
W25X64
12.3 16-Pin SOIC 300-mil (Winbond Package Code SF)
SYMBOL
MILLIMETERS
INCHES
MIN
MAX
MIN
MAX
A
2.36
2.64
0.093
0.104
A1
0.10
0.30
0.004
0.012
b
0.33
0.51
0.013
0.020
C
0.18
0.28
0.007
0.011
10.08
10.49
0.397
0.413
10.01
10.64
0.394
0.419
7.39
7.59
0.291
0.299
(3)
D
E
(3)
E1
(2)
e
1.27 BSC
0.050 BSC
L
0.39
1.27
0.015
0.050
θ
0o
8o
0o
8o
y
---
0.076
---
0.003
Notes:
1. Controlling dimensions: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
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Publication Release Date: December 19, 2008
Revision A
W25X64
3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of
the package.
ORDERING INFORMATION (1)
13
64
=
64M-bit
V
=
2.7V to 3.6V
SF
DA
ZE
=
=
=
16-pin SOIC 300-mil
8-pin DIP 300-mil
8-pad WSON 8x6mm
G or Z = Green Package (Lead-f ree, RoHS Compliant, Halogen-f ree(TBBA ), A ntimony-Oxide-f ree Sb 2O3)
Notes:
1a. Only the 2nd letter is used for the part marking; WSON package type ZE is not used for the top marking.
1b. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as
Tape and Reel (shape T), when placing orders.
1c. The “W” prefix is not included on the part marking.
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W25X64
Valid Part Numbers and Top Side Marking:
The following table provides the valid part numbers for the 25X64 SpiFlash Memory. Please contact
Winbond for specific availability by density and package type. Winbond SpiFlash memories use an 11digit Product Number for ordering. However, due to limited space, the Top Side Marking on all packages
use an abbreviated 9-digit number.
PACKAGE TYPE
SF
SOIC-16 300mil
ZE
WSON-8 8x6mm
DA
PDIP-8 300mil
DENSITY
PRODUCT NUMBER
TOP SIDE MARKING
64M-bit
W25X64VSFIG
25X64VFIG
64M-bit
W25X64VZEIG
25X64VIG
64M-bit
W25X64VDAIZ
25X64VAIZ
Notes:
1.
For WSON packages, the package type ZE are not used in the top side marking.
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Publication Release Date: December 19, 2008
Revision A
W25X64
14 REVISION HISTORY
VERSION
DATE
A
12/19/08
PAGE
DESCRIPTION
New Create
Trademarks
Winbond and SpiFlash are trademarks of Winbond Electronics Corporation.
All other marks are the property of their respective owner.
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in
systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, or for other applications intended to support or sustain life. Further more, Winbond products
are not intended for applications wherein failure of Winbond products could result or lead to a situation
wherein personal injury, death or severe property or environmental damage could occur. Winbond
customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Winbond for any damages resulting from such improper use or sales.
Information in this document is provided solely in connection with Winbond products. Winbond reserves
the right to make changes, corrections, modifications or improvements to this document and the
products and services decribed herein at any time, without notice.
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