TI DAC5674

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8
SLWS148 − SEPTEMBER 2003

FEATURES
D Differential Scalable Current Outputs: 2 mA to
D 200-MSPS Maximum Input Data Rate
D 400-MSPS Maximum Update Rate DAC
D 76-dBc SFDR Over Full First Nyquist Zone
D On-Chip 1.2-V Reference
D 1.8-V Digital and 3.3-V Analog Supply
With Single Tone Input Signal (Fout = 21 MHz)
D 74-dBc ACPR W-CDMA at 15.36 MHz IF
D 69-dBc ACPR W-CDMA at 30.72 MHz IF
D Selectable 2x or 4x Interpolation Filter
−
−
−
−
−
Linear Phase
0.05-dB Passband Ripple
80-dB Stopband Attenuation
Stopband Transition 0.4−0.6 Fdata
nterpolation Filters Configurable in Either
Low-Pass or High-Pass Mode, Allows For
Selection Higher Order Image
D On-chip 2x/4x PLL Clock Multiplier, PLL
Bypass Mode
20 mA
D
D
D
Operation
1.8/3.3-V CMOS Compatible Interface
Power Dissipation: 435 mW at 400 MSPS
Package: 48-Pin TQFP
APPLICATIONS
D Cellular Base Transceiver Station Transmit
D
D
D
Channel
− CDMA: W−CDMA, CDMA2000, IS−95
− TDMA: GSM, IS−136, EDGE/UWC−136
Test and Measurement: Arbitrary Waveform
Generation
Direct Digital Synthesis (DDS)
Cable Modem Termination System
DESCRIPTION
The DAC5674 is a 14-bit resolution high-speed digital-to-analog converter (DAC) with integrated
4x-interpolation filter, on-board clock multiplier, and on-chip voltage reference. The device has been designed
for high-speed digital data transmission in wired and wireless communication systems, high-frequency
direct-digital synthesis (DDS) and waveform reconstruction in test and measurement applications.
The 4x-interpolation filter is implemented as a cascade of two 2x-interpolation filters, each of which can be
configured for either low-pass or high-pass response. This enables the user to select one of the higher order
images present at multiples of the input data rate clock while maintaining a low date input rate. The resulting
high IF output frequency allows the user to omit the conventional first mixer in heterodyne transmitter
architectures and directly up-convert to RF using only one mixer, thereby reducing system complexity and
costs.
In 4x-interpolation low-pass response mode, the DACs excellent spurious free dynamic range (SFDR) at
intermediate frequencies located in the first Nyquist zone (up to 40 MHz) allows for multicarrier transmission
in cellular base transceiver stations (BTS). The low-pass interpolation mode thereby relaxes image filter
requirements by filtering out the images in the adjacent Nyquist zones.
The DAC5674 PLL clock multiplier controls all internal clocks for the digital filters and DAC core. The differential
clock input and internal clock circuitry provides for optimum jitter performance. Sine wave clock input signal is
supported. The PLL can be bypassed by an external clock running at the DAC core update rate. The clock
divider of the PLL ensures that the digital filters operate at the correct clock frequencies.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
!"#$%&!" ! '($$)"& % # *(+,!'%&!" -%&). $-('&
'"#$ & *)'!#!'%&!" *)$ &/) &)$ # )% "&$()"& &%"-%$- 0%$$%"&1.
$-('&!" *$')!"2 -) "& ")')%$!,1 !"',(-) &)&!"2 # %,, *%$%)&)$.
Copyright  2003, Texas Instruments Incorporated
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SLWS148 − SEPTEMBER 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
The DAC5674 operates from an analog supply voltage of 3.3 V and a digital supply voltage of 1.8 V. The digital
I/O’s are 1.8-V and 3.3-V CMOS compatible. Power dissipation is 500 mW at maximum operating conditions.
The DAC5674 provides a nominal full-scale differential current-output of 20 mA, supporting both single-ended
and differential applications. The output current can be directly fed to the load with no additional external output
buffer required. The device has been specifically designed for a differential transformer coupled output with a
50-Ω doubly terminated load. For a 20-mA full-scale output current both a 4:1 impedance ratio (resulting in an
output power of 4 dBm) and 1:1 impedance ratio transformer (−2-dBm output power) are supported. The latter
configuration is preferred for optimum performance at high output frequencies and update rates.
An accurate on-chip 1.2-V temperature compensated bandgap reference and control amplifier allows the user
to adjust the full-scale output current from 20 mA down to 2 mA. This provides 20-dB gain range control
capabilities. Alternatively, an external reference voltage may be applied for maximum flexibility. The device
features a SLEEP mode, which reduces the standby power to approximately 10 mW, thereby optimizing the
power consumption for the system’s need.
The DAC5674 is available in a 48-pin HTQFP Powerpad plastic quad flatpack package. The device is
characterized for operation over the industrial temperature range of −40°C to 85°C.
AVAILABLE OPTIONS
TA
PACKAGED DEVICES
48-HTQFP PowerPAD Plastic Quad Flatpack
DAC5674IPHP
−40°C
−40
C to 85
85°C
C
DAC5674IPHPR
NOTE: PowerPAD is a trademark of Texas Instruments.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
Supply voltage range
AVDD(2), CLKVDD(2), IOVDD(2), PLLVDD(2)
DVDD(3)
Voltage between AGND, DGND, CLKGND, PLLGND, and IOGND
D[13..0](3), HP1, HP2, DIV0(3), DIV1(3), PLLLOCK(3), RESET(3), X4(3)
Supply voltage range
IOUT1, IOUT2(2)
EXTIO(2), EXTLO(2), BIASJ(2), SLEEP(2), CLK(2), CLKC(2), LPF(2)
Peak input current (any input)
Peak total input current (all inputs)
−0.5 V to 4 V
−0.5 V to 2.3 V
−0.5 V to 0.5 V
−0.5 V to IOVDD + 0.5 V
−1 V to AVDD + 0.5 V
−0.5 V to AVDD + 0.5 V
20 mA
−30 mA
Operating free-air temperature range, TA: DAC5674I
−40°C to 85°C
Storage temperature range
−65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds
260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Measured with respect to AGND.
(3) Measured with respect to DGND.
2
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SLWS148 − SEPTEMBER 2003
DC ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V,
IOUTFS = 20 mA, Rset = 1.91 kΩ, internal reference, unless otherwise noted
PARAMETER
TEST CONDITIONS
RESOLUTION
MIN
TYP
MAX
UNIT
14
Bits
DC ACCURACY(1)
INL
Integral nonlinearity
DNL
Differential nonlinearity
1 LSB = IOUTFS/214, TMIN to TMAX
Monotonicity
−3.5
3.5
−2.14e−4
2.14e−4
LSB
−2
2
IOUTFS
LSB
−1.22e−4
1.22e−4
IOUTFS
Montonic to 12 bits
ANALOG OUTPUT
Offset error
Gain error
0.02
Without internal reference
2.3
With internal reference
1.3
FSR
%FSR
Minimum full-scale output
current(2)
2
mA
Maximum full-scale output
current(2)
20
mA
Output compliance range(3)
IOUTFS = 20 mA
−1
Output resistance
Output capacitance
1.25
V
300
kΩ
5
pF
REFERENCE OUTPUT
Reference voltage
1.14
Reference output current(4)
1.2
1.26
100
V
nA
REFERENCE INPUT
VEXTIO
Input voltage range
0.1
Input resistance
1.25
V
1
MΩ
Small signal bandwidth
1.4
MHz
Input capacitance
100
pF
TEMPERATURE COEFFICIENTS
Offset drift
Without internal reference
0
ppm of
FSR/°C
±50
ppm of
FSR/°C
±100
ppm of
FSR/°C
±50
ppm/°C
Gain drift
With internal reference
Reference voltage drift
POWER SUPPLY
AVDD
Analog supply voltage
DVDD
Digital supply voltage
CLKVDD
Clock supply voltage
IOVDD
I/O supply voltage
PLLVDD
PLL supply voltage
IAVDD
Analog supply current
3
3.3
3.6
V
1.65
1.8
1.95
V
3
3.3
3.6
V
3.6
V
3.3
3.6
V
41
55
mA
1.65
3
Including output current through the load
resistor, AVDD = 3.3 V, DVDD = 1.8 V, 4x
interpolation,PLL on, 9-MHz IF, 400 MSPS
Specifications subject to change without notice.
(1) Measured differentially across IOUT1 and IOUT2 into 50 Ω.
(2) Nominal full-scale current, IOUTFS, equals 32X the IBIAS current.
(3) The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown, resulting
in reduced reliability of the DAC5674 device. The upper limit of the output compliance is determined by the load resistors and full-scale output
current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.
(4) Use an external buffer amplifier with high impedance input to drive any external load.
3
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SLWS148 − SEPTEMBER 2003
DC ELECTRICAL CHARACTERISTICS (CONTINUED)
over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V,
IOUTFS = 20 mA, Rset = 1.91 kΩ, internal reference, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY (CONTINUED)
IDVDD
Digital supply current
AVDD = 3.3 V, DVDD = 1.8 V, 4x interpolation,PLL
on, 9-MHz IF, 400 MSPS
ISLEEP3.3
ISLEEP1.8
Sleep mode
Sleep mode
IPLLVDD
107
140
mA
Sleep mode, supply current 3.3 V
6
12
mA
Sleep mode, supply current 1.8 V
0.5
3
mA
PLL supply current(1)
Fdata = 100 MSPS, Fupdate = 400 MSPS,
DIV[1:0] = ’00’, AVDD = 3.3 V, DVDD = 1.8 V, 4x
interpolation,PLL on, 9-MHz IF, 400 MSPS
23
35
mA
IIOVDD
Buffer supply current
AVDD = 3.3 V, DVDD = 1.8 V, 4x interpolation,PLL
on, 9-MHz IF, 400 MSPS
4
10
mA
ICLKVDD
Clock supply current(1)
AVDD = 3.3 V, DVDD = 1.8 V, 4x interpolation,PLL
on, 9-MHz IF, 400 MSPS
6
10
mA
PD
Power dissipation
AVDD = 3.3 V, DVDD = 1.8 V, 4x interpolation,
PLL on, 9-MHz IF, 400 MSPS
435
550
mW
APSRR
Power supply rejection ratio
−0.2
0.2
DPSRR
−0.2
0.2
Operating range
−40
85
%FSR/V
°C
Specifications subject to change without notice.
(1) PLL enabled
AC ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 1.8 V, DVDD = 1.8 V,
IOUTFS = 20 mA, differential transformer coupled output, 50-Ω doubly terminated load (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG OUTPUT
fCLK
ts(DAC)
Maximum output update rate
tr(IOUT)
tf(IOUT)
Output rise time 10% to 90%(1)
Output fall time 90% to 10%(1)
Output settling time to 0.1%
Output noise
400
Mid-scale transition
IOUTFS = 20 mA
IOUTFS = 2 mA
MSPS
20
ns
1.4
ns
1.5
ns
55
30
pA/√HZ
AC LINEARITY 1:1 IMPEDANCE RATIO TRANSFORMER
SFDR
Spurious free dynamic range (First
Nyquist zone < fDATA/2) X4 LL-mode
SNR
Signal-to-noise ratio (First Nyquist
zone < fDATA/2) X4 LL-mode
ACPR
Adjacent channel power ratio
W-CDMA signal with 3.84 MHz BW
5-MHz channel spacing
IMD3
IMD
Third-order two-tone intermodulation
(each tone at −6 dBFS)
Four-tone Intermodulation to Nyquist
(each tone at –12 dBFS)
(1) Measured single ended into 50-Ω load.
4
fDATA = 52 MSPS, fOUT = 14 MHz, TA = 25_C
fDATA = 100 MSPS, fOUT = 21 MHz, TMIN to TMAX
85
fDATA = 100 MSPS, fOUT = 41 MHz, TMIN to TMAX
fDATA = 78 MSPS, fOUT = 20 MHz, TMIN to TMAX
71
fDATA = 100 MSPS, fOUT = 20 MHz, TMIN to TMAX
70
fDATA = 61.44 MSPS, IF = 15.360 MHz, X4 LL-mode
74
fDATA = 122.88 MSPS, IF = 30.72 MHz, X2 L-mode
69
fDATA = 61.44 MSPS, fOUT = 45.4 and 46.4 MHz,
X4 HL-mode
68
fDATA = 61.44 MSPS, fOUT = 15.1 and 16.1 MHz,
X4 LL-mode
82
fDATA = 78 MSPS fOUT = 15.6 MHz, 15.8 MHz,
16.2 MHz, 16.4 MHz, X4 LL-mode
76
fDATA = 52 MSPS fOUT = 68.8 MHz, 69.6 MHz,
71.2 MHz, 72 MHz, X4 HH-mode
64
76
dBc
71
dB
dB
dBc
dBc
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SLWS148 − SEPTEMBER 2003
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V,
IOUTFS = 20 mA, differential transformer coupled output, 50-Ω doubly terminated load (unless otherwise noted)
DIGITAL SPECIFICATIONS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CMOS INTERFACE
VIH
VIL
High-level input voltage for SLEEP and EXTLO
VIH
VIL
High-level input voltage other digital inputs
IIH
IIL
High-level input current
Low-level input current
0.7xAVDD
0
Low-level input voltage for SLEEP and EXTLO
V
0.3xAVDD
0.7xIOVDD
0
Low-level input voltage other digital inputs
Input capacitance
V
V
10
0.3xIOVDD
30
V
µA
−1
10
µA
1
5
pF
TIMING INTERNAL CLOCK MODE
tSU
tH
Input setup time
0.6
Input hold time
0.6
tLPH
tlat_2x
Input latch pulse high time
ns
ns
2
ns
Data in to DAC out latency − 2X interpolation
26
clk
tlat_4x
Data in to DAC out latency − 4X interpolation
TIMING − EXTERNAL CLOCK MODE
35
clk
tsu
th
Input setup time
5
tlph
td_clk
Input latch pulse high time
Clock delay time
3.6
ns
tlat_2x
tlat_4x
Data in to DAC out latency − 2X interpolation
26
clk
Data in to DAC out latency − 4X interpolation
35
clk
Input hold time
ns
−1.75
ns
2
ns
PLL
Input data rate supported
Phase noise
5
200
At 600-kHz offset
−124
At 6-MHz offset
−134
MSPS
dBc/Hz
DIGITAL FILTER SPECIFICATIONS
fDATA
Input data rate
FIR1 and FIR2 DIGITAL FILTER CHARACTERISTICS
200
0.005 db
Passband width
MSPS
0.407
0.01 dB
0.41
0.1 dB
0.427
3 dB
0.481
fOUT/
fDATA
5
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SLWS148 − SEPTEMBER 2003
PIN OUT DIAGRAM
DVDD
DVDD
AVDD
AVDD
AGND
IOUT1
IOUT2
AGND
BIASJ
EXTIO
EXTLO
AGND
PHP PACKAGE
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
DGND
DGND
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
D3
D2
D1
D0
HP1
HP2
DGND
IOGND
DVDD
IODVDD
X4
DGND
13 14 15 16 17 18 19 20 21 22 23 24
6
SLEEP
LPF
PLLVDD
PLLGND
CLKVDD
CLKGND
CLKC
CLK
DIV0
DIV1
RESET
PLLLOCK
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SLWS148 − SEPTEMBER 2003
Terminal Functions
TERMINAL
NAME
NO.
AGND
37, 41, 44
AVDD
BIASJ
I/O
DESCRIPTION
I
Analog ground return
45, 46
I
Analog supply voltage
40
O
Full-scale output current bias
CLK
29
I
External clock input
CLKC
30
I
Complementary external clock input
CLKGND
31
I
Ground return for internal clock buffer
CLKVDD
32
I
Internal clock buffer supply voltage
D[13..0]
3−16
I
Data bits 0 through 13
D13 is most significant data bit (MSB)
D0 is least significant data bit (MSB)
DIV[1..0]
27,28
I
PLL prescaler divide ratio settings
DGND
1, 2, 19, 24
I
Digital ground return
DVDD
21, 47, 48
I
Digital supply voltage
EXTIO
39
I/O
EXTLO
38
I
For internal reference connect to AGND. Connect to AVDD to disable the internal reference
HP1
17
I
Filter 1 high-pass setting. Active high
HP2
18
I
Filter 2 high-pass setting. Active high
IOGND
20
I
Input digital ground return
IOVDD
22
I
Input digital supply voltage
IOUT1
43
O
DAC current output. Full scale when all input bits are set 1
IOUT2
42
O
DAC complementary current output. Full scale when all input bits are 0
LPF
35
I
PLL loop filter connection
PLLGND
33
I
Ground return for internal PLL
PLLLOCK
25
O
PLL lock status bit. PLL is locked to input clock when high. Provides output clock equal to the data rate
when the PLL is disabled.
PLLVDD
34
I
Internal PLL supply voltage. Connect to PLLGND to disable PLL clock multiplier.
RESET
26
I
Reset internal registers. Active high
SLEEP
36
I
Asynchronous hardware power down input. Active high. Internally pull down.
X4
23
I
4x interpolation mode. Active high. Filter 1 is bypassed when connected to DGND
Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD).
Used as internal reference output when EXTLO = AGND, requires a 0.1-µF decoupling capacitor to AGND
when used as reference output
7
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SLWS148 − SEPTEMBER 2003
FUNCTIONAL BLOCK DIAGRAM
CLKVDD
CLKGND
CLK
PLLLOCK
LPF
PLLGND
PLLVDD
DIV[1:0]
HP1
PLL Clock
Multiplier
CLKC
HP2
X4
48-Pin TQFP
SLEEP
AVDD (2x)
AGND (3x)
Clock Generation / Mode Select
HP1
IOVDD
X4
HP2
IOGND
BIASJ
..., 1, −1,...
D[13:0]
..., 1, −1,...
1
x2
x2
0
Edge
Triggered
Input
Latches
IOUT2
FIR2
1.2-V
Reference
DVDD (3x)
DGND (4x)
Figure 1. Block Diagram
8
14-BIt DAC
0
0
FIR1
IOUT1
1
1
EXTIO
EXTLO
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SLWS148 − SEPTEMBER 2003
TYPICAL CHARACTERISTICS
INL − Integral Nonlinearity − LSB
INTEGRAL NONLINEARITY
vs
INPUT CODE
1.0
0.8
0.6
0.4
0.2
−0.0
−0.2
−0.4
−0.6
−0.8
−1.0
VCC = 3.3 V
IOUTfS = 20 mA
0
2000
4000
6000
8000
10000
12000
14000
16000
14000
16000
Input Code
Figure 2
DNL − Differential Nonlinearity − LSB
DIFFERENTIAL NONLINEARITY
vs
INPUT CODE
1.0
0.8
0.6
0.4
0.2
−0.0
−0.2
−0.4
−0.6
−0.8
−1.0
VCC = 3.3 V
IOUTfS = 20 mA
0
2000
4000
6000
8000
10000
12000
Input Code
Figure 3
9
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SLWS148 − SEPTEMBER 2003
SPURIOUS-FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY
90
VCC = 3.3 V
fS = 50 MSPS
IOUTfS = 20 mA
4x LL-Mode
85
80
SFDR − Spurious-Free Dynamic Range − dBc
SFDR − Spurious-Free Dynamic Range − dBc
90
−3 dBfS
75
0 dBfS
70
−6 dBfS
65
60
55
VCC = 3.3 V
fS = 100 MSPS
IOUTfS = 20 mA
4x LL-Mode
85
80
0 dBfS
75
70
−6 dBfS
−3 dBfS
65
60
55
50
50
0
3
6
9
12
15
0
18
5
10
Figure 4
Power − dBm
−40
−50
−60
−70
−80
−90
−100
25
50
75
100
125
f − Frequency − MHz
Figure 6
10
150
175
200
SFDR − In-Band Spurious-Free Dynamic Range − dBc
VCC = 3.3 V
fS = 100 MSPS
IOUTfS = 20 mA
4x LL-Mode
Fout = 10 MHz
0
30
35
IN-BAND
SPURIOUS-FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY
0
−30
25
Figure 5
POWER
vs
FREQUENCY
−20
20
fO − Output Frequency − MHz
fO − Output Frequency − MHz
−10
15
90
VCC = 3.3 V
fS = 100 MSPS
IOUTfS = 20 mA
4x LL-Mode
In Band = 0 − 50 MHz
85
80
0 dBfS
75
−6 dBfS
70
−12 dBfS
65
60
55
50
0
5
10
15
20
25
30
35
fO − Output Frequency − MHz
Figure 7
40
45
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OUT-OF-BAND
SPURIOUS-FREE DYNAMIC RANGE
vs
OUTPUT FREQUENCY
POWER
vs
FREQUENCY
−20
80
VCC = 3.3 V
fS = 100 MSPS
IOUTfS = 20 mA
4x LL-Mode
Out-of-Band = 50 − 100 MHz
75
70
65
60
55
−6 dBfS
50
−12 dBfS
0 dBfS
45
VCC = 3.3 V
fS = 61.44 MSPS
fcarrier = 15.36 MHz
IOUTfS = 20 mA
ACPR = 73.25 dB
4x LL-Mode
−40
P − Power − dBm
SFDR − Out-of-Band Spurious-Free Dynamic Range − dBc
SLWS148 − SEPTEMBER 2003
−60
−80
−100
40
35
−120
30
0
5
10
15
20
25
30
35
40
6
45
9
12
Figure 8
24
−20
VCC = 3.3 V
fS =76.80 MSPS
fcarrier = 19.20 MHz
VCC = 3.3 V
fS = 122.88 MSPS
fcarrier = 30.72 MHz
IOUTfS = 20 mA
ACPR = 70.23 dB
2x L-Mode
IOUTfS = 20 mA
ACPR = 70.22 dB
4x LL-Mode
−40
P − Power − dBm
P − Power − dBm
21
POWER
vs
FREQUENCY
−20
−60
−80
−60
−80
−100
−100
−120
17
18
Figure 9
POWER
vs
FREQUENCY
−40
15
f − Frequency − MHz
fO − Output Frequency − MHz
−120
21
25
29
33
37
f − Frequency − MHz
Figure 10
41
45
8
12
16
20
24
28
f − Frequency − MHz
Figure 11
11
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SLWS148 − SEPTEMBER 2003
POWER
vs
FREQUENCY
TWO-TONE IMD3
vs
OUTPUT FREQUENCY
−20
85
80
Two-Tone IMD3 − dBc
P − Power − dBm
−40
90
VCC = 3.3 V
fS = 61.44 MSPS
fcarrier = 15.36 MHz
IOUTfS = 20 mA
ACPR = 69.73 dB
4x LH-Mode
−60
−80
75
70
65
VCC = 3.3 V
fS = 78 MSPS
fout1 = fout
fout2 = fout + 1 MHz
IOUTfS = 20 mA
4x LL-Mode
60
−100
55
−120
32
50
36
40
44
48
52
56
60
0
5
f − Frequency − MHz
10
Figure 13
TWO-TONE IMD3
vs
OUTPUT FREQUENCY
90
85
Two-Tone IMD3 − dBc
80
75
70
65
VCC = 3.3 V
fS = 78 MSPS
fout1 = fout
fout2 = fout + 4 MHz
IOUTfS = 20 mA
4x LL-Mode
60
55
50
0
20
25
fO − Output Frequency − MHz
Figure 12
5
10
15
20
25
fO − Output Frequency − MHz
Figure 14
12
15
30
35
30
35
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DETAILED DESCRIPTION
Figure 1 shows a simplified block diagram of the DAC5674. The CMOS device consists of a segmented array
of PMOS current sources, capable of delivering a full-scale output current up to 20 mA. Differential current
switches direct the current of each current source to either one of the complementary output nodes IOUT1 or
IOUT2. The complementary output currents thus enable differential operation, canceling out common mode
noise sources (digital feed-through, on-chip, and PCB noise), dc offsets, even order distortion components, and
increase signal output power by a factor of two.
The full-scale output current is set using an external resistor RBIAS in combination with an on-chip bandgap
voltage reference source (1.2 V) and control amplifier. The current IBIAS through resistor RBIAS is mirrored
internally to provide a full-scale output current equal to 32 times IBIAS. The full-scale current can be adjusted
from 20 mA down to 2 mA.
Interpolation Filter
The interpolation filters FIR1 and FIR2 can be configured for either low-pass or high-pass response. In this way,
higher order images can be selected. This is shown in Table 1. Table 2 shows the DAC IF output range for the
different filter response combinations, for both the first and second Nyquist zone (after interpolation). Table 3
lists the DAC IF output ranges for two popular GSM data rates. Table 3 shows the W-CDMA IF carrier center
frequency for an input data rate of 61.44 MSPS and a fundamental input IF of 15.36 MHz. Figure 15 shows the
spectral response; the corresponding nonzero tap weights are:
D [5, −20, 50, −108, 206, −361, 597, −947, 1467, −2267, 3633, −6617, 20746, 32768]
AMPLITUDE
vs
FREQUENCY
AMPLITUDE
vs
FREQUENCY
0.005
−50
Amplitude − dB
Amplitude − dB
0
0.000
−100
−150
0.0
0.2
0.4
0.6
0.8
1.0
−0.005
0.0
0.2
f / fin
0.4
0.6
0.8
1.0
f / fin
Figure 15. FIR1 and FIR2 Magnitude Spectrum
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SLWS148 − SEPTEMBER 2003
Table 1. Interpolation Filters Configuration
FILTER 1
CONFIGURATION
FILTER 2
CONFIGURATION
Low pass
Low pass
Low pass
High pass
High pass
Low pass
High pass
High pass
IF OUTPUT RANGE 1
(FIRST NYQUIST ZONE)
IF OUTPUT RANGE 2
(SECOND NYQUIST ZONE)
FREQUENCY
SINX/X ATT. [dB]
FREQUENCY
SINX/X ATT. [dB]
0…0.4Fdata
1.6…2Fdata
0…0.14
2.42…3.92
3.6…4Fdata
2…2.4Fdata
3.92…5.94
0.6…0.8Fdata
1.2…1.4Fdata
0.32…0.58
1.33…1.83
19.2…∞
3.2…3.4Fdata
2.6…2.8Fdata
12.6…15.4
7.20…8.69
Table 2. Interpolation Filters Configuration: Example Frequencies GSM
FILTER 1
CONFIGURATION
FILTER 2
CONFIGURATION
IF OUTPUT RANGE 1
(FIRST NYQUIST ZONE)
IF FREQUENCY [MHz]
IF OUTPUT RANGE 2
(SECOND NYQUIST ZONE)
IF FREQUENCY [MHz]
Low pass
Low pass
Fdata = 52 MSPS
0…20.8
Fdata = 78 MSPS
0…31.2
Fdata = 52 MSPS
187.2…208
Fdata = 78 MSPS
280.8…312
Low pass
High pass
83.2…108
124.8…156
104…124.8
156…187.2
High pass
Low pass
31.2…41.6
46.8…62.4
166.4…176.8
249.6…265.2
High pass
High pass
62.4…72.8
93.6…109.2
135.2…145.6
202.8…218.4
Table 3. Interpolation Filters Configuration: Example Frequencies W-CDMA, IF = Fdata/4, FDATA = 61.44
MSPS: Fupdate = 245.76 MSPS
14
IF FREQUENCY [MHZ]
(FIRST NYQUIST ZONE)
IF FREQUENCY [MHZ]
(SECOND NYQUIST ZONE)
FILTER 1
CONFIGURATION
FILTER 2
CONFIGURATION
IF CENTER [MHz]
SINX/X ATT. [dB]
IF CENTER [MHz]
SINX/X ATT. [dB]
Low pass
Low pass
15.36
0.05
230.4
23.6
Low pass
High pass
107.52
2.93
138.24
5.11
High pass
Low pass
46.08
0.51
199.68
13.2
High pass
High pass
76.8
1.44
168.96
8.29
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SLWS148 − SEPTEMBER 2003
Low-Pass/Low-Pass 4x Interpolation Filter Operation
Figure 16 shows the low-pass/low-pass interpolation operation where the 4x FIR filter is implemented as a
cascade of two 2x interpolation filters. The user can place their IF signal at a maximum of 0.4 times the FIR
filter input (i.e. DAC5674 input) data rate. For a 100-MSPS data rate, this would translate into a pass-band
extending to 40 MHz.
Normalized IF:IFmax+0.4 Fdata
Input Spectrum
Output DUC
0
IF
Fdata
Transition Band+(Fdata*2IF)ńFdata
First
2x Interpolation
Filter
2Fdata
3Fdata
4Fdata
Normalized Transition Band+(1*2 0.4)ń1+0.2
80 dB
0
IF
Fdata
2Fdata
3Fdata
4Fdata
0
IF
Fdata
2Fdata
3Fdata
4Fdata
Spectrum After
2x Interpolation
Transition Band+(Fdata*IF)ńFdata
Second
2x Interpolation
Filter
Normalized Transition Band+(1*0.4)ń1+0.6
80 dB
0
IF
Fdata
2Fdata
3Fdata
4 Fdata
0
IF
Fdata
2Fdata
3Fdata
4Fdata
=
Fupdate
Spectrum After
4x Interpolation
Figure 16. Low-Pass/Low-Pass 4x Interpolation Filter Operation
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Low-Pass/High-Pass 4x Interpolation Filter Operation
By configuring the low-pass filters as high-pass filters the user can select one of the images present at multiples
of the clock. Figure 17 shows the low-pass/high-pass filter response. After digital filtering, the DAC transmits
at
2Fdata − IF and 2Fdata + IF. This configuration is equivalent to sub-sampling receiver systems where a
high-speed analog-to-digital converter samples high IF frequencies with relatively low sample rates, resulting
in low (output) data rates.
The placement of the IF in the first Nyquist zone combined with the DAC5674 input data determines the final
output signal frequency. For Fdata = 100 MSPS and a fundamental IF of 0.4 x Fdata = 40 MHz, this would translate
into images located at 160 MHz and 240 MHz. Note that this is the equivalent of mixing a 40-MHz analog IF
signal with a 200-MHz sine wave. By doing this, the first mixer in the total transmission chain is eliminated.
Input Spectrum
Output DUC
0
IF
Fdata
Transition Band+(Fdata*2IF)ńFdata
First
2x Interpolation
Filter
2Fdata
3Fdata
4Fdata
Normalized Transition Band+(1*2 0.4)ń1+0.2
80 dB
0
IF
Fdata
2Fdata
3Fdata
4Fdata
0
IF
Fdata
2Fdata
3Fdata
4Fdata
Spectrum After
2x Interpolation
Transition Band+(Fdata*IF)ńFdata
Second
2x Interpolation
Filter
Normalized Transition Band+(1*0.4)ń1+0.6
80 dB
0
IF
0
IF
Fdata
2Fdata
3Fdata
4 Fdata
Spectrum After
4x Interpolation
Fdata Fdata)IF
2Fdata
3Fdata*IF 3Fdata
Figure 17. Low-Pass 2x, High-Pass 2x Interpolation Filter Operation
16
4Fdata
=
Fupdate
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SLWS148 − SEPTEMBER 2003
High-Pass/Low-Pass 4x Interpolation Filter Operation
Figure 18 shows the high-pass/low-pass filter configuration. Images at Fdata − IF and 3Fdata + IF can be
selected. Note that the latter image severely attenuates by the sinx/x response. The transition bands of filter
1 and filter 2 of 0.2 allow for the placement of the fundamental IF between 0.2…0.4Fdata. This results in an output
IF of 0.6…0.8Fdata.
Input Spectrum
Output DUC
0
IF
Fdata
2Fdata
Transition Band+(Fdata*2IF)ńFdata
First
2x Interpolation
Filter
3Fdata
4Fdata
Normalized Transition Band+(1*2 0.4)ń1+0.2
80 dB
0
IF
Fdata
2Fdata
3Fdata
4Fdata
0
IF
Fdata
2Fdata
3Fdata
4Fdata
Spectrum After
2x Interpolation
Transition Band+2IFń2Fdata
Second
2x Interpolation
Filter
Normalized Transition Band+2 0.2ń2+0.2
80 dB
0
IF
0
IF
Fdata
2Fdata
3Fdata
4 Fdata
Spectrum After
4x Interpolation
Fdata Fdata)IF
2Fdata
3Fdata*IF 3Fdata
4Fdata
=
Fupdate
Figure 18. High-Pass 2x, Low-Pass 2x Interpolation Filter Operation
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High-Pass/High-Pass 4x Interpolation Filter Operation
Figure 19 shows the high-pass/high-pass filter configuration. The transition bands of filter 1 and filter 2 allow
for the placement of the fundamental IF between 0.2…0.4Fdata. In this configuration the user can select the
images at Fdata + IF and 3Fdata – IF. For Fdata = 100 MSPS and a fundamental IF of 0.4 x Fdata = 40 MHz, this
would translate into images located at 140 MHz and 260 MHz. Note that this is the equivalent of mixing a 60-MHz
analog IF signal with a 200-MHz sine wave.
Input Spectrum
Output DUC
0
IF
Fdata
Transition Band+(Fdata*2IF)ńFdata
First
2x Interpolation
Filter
2Fdata
3Fdata
4Fdata
Normalized Transition Band+(1*2 0.4)ń1+0.2
80 dB
0
IF
Fdata
2Fdata
3Fdata
4Fdata
0
IF
Fdata
2Fdata
3Fdata
4Fdata
Spectrum After
2x Interpolation
Transition Band+2IFń2Fdata
Second
2x Interpolation
Filter
Normalized Transition Band+2 0.2ń2 1+0.2
80 dB
0
IF
0
IF
Fdata
2Fdata
3Fdata
4 Fdata
Spectrum After
4x Interpolation
Fdata Fdata)IF
2Fdata
3Fdata*IF 3Fdata
Figure 19. High-Pass/High-Pass 4x Interpolation Filter Operation
18
4Fdata
=
Fupdate
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SLWS148 − SEPTEMBER 2003
*1.83 dB
”Sinx/x”
Attenuation
*7.2 dB
Fupdate+65 MSPS
0
IF=26
65
91
130
*1.83 dB
169
195
”Sinx/x”
Attenuation
*7.2 dB
Fupdate+80 MSPS
0
IF=32
80
112
160
*1.83 dB
208
240
IF=40
100
140
200
260
320
”Sinx/x”
Attenuation
*7.2 dB
Fupdate+100 MSPS
0
260
300
400
Figure 20. High-Pass 4x Interpolation Filter Operation: Example Frequencies
Clock Generation Function
An internal PLL or external clock can be used to derive the internal clocks (1x, 2x, and 4x) for the logic, FIR
interpolation filters, and DAC. Basic functionality is depicted in Figure 21. Power for the internal PLL blocks
(PLLVDD and PLLGND) is separate from the other clock generation blocks power (CLKVDD and CLKGND),
thus minimizing phase noise within the PLL. The PLLVDD pin establishes internal/external clock mode: when
PLLVDD is grounded, external clock mode is active and when PLLVDD is 3.3 V, internal clock mode is active.
In external clock mode, the user provides a differential external clock on pins CLK/CLKC. This clock becomes
the 4x clock and is twice divided down to generate the 2x and 1x clocks. The 2x or 1x clock is multiplexed out
on the PLLLOCK pin to allow for external clock synchronization.
In internal clock mode, the user provides a differential external reference clock on CLK/CLKC. A type four
phase-frequency detector (PFD) in the internal PLL compares this reference clock to a feedback clock and
drives the PLL to maintain synchronization between the two clocks. The feedback clock is generated by dividing
the VCO output by 1x, 2x, 4x, or 8x, as selected by the prescaler (DIV[1:0]). The output of the prescaler is the
4x clock, and is divided down twice to generate the 2x and 1x clocks. Pin X4 selects the 1x or 2x clock to clock
in the input data; the selected clock is also fed back to the PFD for synchronization. The PLLLOCK pin is an
output indicating when the PLL has achieved lock. An external RC low-pass PLL filter is provided by the user
at pin LPF. See the Low-Pass Filter section for filter setting calculations. Table 4 provides a summary of the
clock configurations with corresponding data rate ranges.
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SLWS148 − SEPTEMBER 2003
LPF
DIV[1:0]
PLLVDD
DAC5674
CLK
Charge
Pump
PFD
CLKC
/1
/2
/4
/8
VCO
Clk_4x
Clk
Buffer
PLLVDD
PLLGND
0
0
/2
Clk_2x
1
s
/2
Clk_1x
CLKVDD
1
s
CLKGND
PLLLOCK
PLLVDD
Data
D[13:0]
X4
Figure 21. Clock Generation Functional Diagram
Table 4. Clock Mode Configuration
CLOCK MODE
PLLVDD
DIV[1:0]
X4
DATA RANGE (MHz)
PLLLOCK PIN FUNCTION
External 2X
0V
XX
0
DC to 200
External clock/2
External 4X
0V
XX
1
DC to 100
External clock/4
Internal 2X
3.3 V
00
0
100 to 200
Internal PLL lock indicator
Internal 2X
3.3 V
01
0
50 to 100
Internal PLL lock indicator
Internal 2X
3.3 V
10
0
25 to 50
Internal PLL lock indicator
Internal 2X
3.3 V
11
0
12 to 25
Internal PLL lock indicator
Internal 4X
3.3 V
00
1
50 to 100
Internal PLL lock indicator
Internal 4X
3.3 V
01
1
25 to 50
Internal PLL lock indicator
Internal 4X
3.3 V
10
1
12 to 25
Internal PLL lock indicator
Internal 4X
3.3 V
11
1
5 to 12
Internal PLL lock indicator
Low-Pass Filter
The PLL consists of a type four phase-frequency detector (PFD), charge pump, external low-pass loop filter,
voltage to current converter, and current controlled oscillator (ICO) as shown in Figure 22. The DAC5674
evaluation board comes with component values R = 200, C1 = 0.01 µF, and C2 = 100 pF. These values have
been designed to give the phase margins and loop bandwidths listed in Table 5 for the five divide down factors
of prescaling and interpolation. Note that the values derived were based on a charge pump current output of
1 mA and a VCO gain of 300 MHz/V (nominal at Fvco = 400 MHz). With this filter, the settling time from a phase
or frequency disturbance is about 2.5 µs. If different PLL dynamics are required, DAC5674 users can design
a second order filter for their application using PLL Loop Filter Components section.
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SLWS148 − SEPTEMBER 2003
DAC5674
LPF
Fref
PFD
Fvco
R
C2
PN
C1
ICO
ref
External Loop Filter
Figure 22. PLL Functional Block Diagram
Table 5. DAC5674 Evaluation Board PLL Loop Filter Parameters
N(1)
PHASE MARGIN (DEGREES)
BANDWIDTH (MHZ)
2
60
1.6
4
71
1.4
8
77
1
16
78
0.7
32
74
0.4
(1) N is the VCO divide-down factor from prescale and interpolation.
Digital Inputs
Figure 23 shows a schematic of the equivalent CMOS digital inputs of the DAC5674. The CMOS-compatible
inputs have logic thresholds of IOVDD/2 ±20%. The 14-bit digital data input follows the offset positive binary
coding scheme.
IOVDD (AVDD for SLEEP and EXTLO)
D[13:0]
SLEEP
EXTLO
DIV[1:0]
RESET
HP1, HP2
Internal
Digital In
IOGND
Figure 23. CMOS/TTL Digital Equivalent Input
Clock Input and Timing
Figure 24 shows the clock and data input timing diagram for internal and external clock modes, respectively.
Note that a negative value indicates a reversal of the edge positions as shown in the timing diagram. Figure 24
also shows the delay (td) of the 1x/2x data clock (PLLLOCK) from CLK in external clock mode (typical td = 4.1
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SLWS148 − SEPTEMBER 2003
ns). The latency from data to DAC is defined by Figure 25. The DAC5674 features a differential clock input.
In internal clock mode, the internal data clock is a divided down version of the PLL clock (/2 or /4), depending
on the level of interpolation (2x or 4x). In external mode, the internal data clock is a divided down version of the
input CLK (/2 or /4), depending on the level of interpolation (2x or 4x). Internal edge-triggered flip-flops latch
the input word on the rising edge of the positive data clock.
D[13:0]
Valid Data
tsu
D[13:0]
th
Valid Data
tsu
PLLLOCK
th
td_clk
tlph
CLK
CLK
CLKC
CLKC
Figure 24. Internal (Left) and External (Right) Clock Mode Timing
tlat_nx
2x Interpolation
DAC
D[13:0] 0
0
2000
3FFF
2000
0
0
4x Interpolation
DAC
Typical tsu = 0.5 ns, th = 0.1 ns
Figure 25. Data to DAC Latency
22
Typical tsu = 2.9 ns, th = −2.3 ns, td = 3.6 ns
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SLWS148 − SEPTEMBER 2003
Figure 26 shows an equivalent circuit for the clock input.
AVDD
CLKVDD
R1
10 kΩ
AVDD
R1
10 kΩ
Internal
Digital In
CLK
CLKC
R2
10 kΩ
R2
10 kΩ
CLKGND
Figure 26. Clock Input Equivalent Circuit
Figure 27, Figure 28, Figure 29, and Figure 30 show various input configurations for driving the differential
clock input (CLK/CLKC).
Optional, May Be Bypassed
for Sine Wave Input
Swing Limitation
CAC
0.1 µF
1:4
CLK
RT
200 Ω
CLKC
Termination Resistor
Figure 27. Preferred Clock Input Configuration
Ropt
22 Ω
TTL/CMOS
Source
Optional, Reduces
Clock Feed-Through
CAC
0.01 µF
1:1
Ropt
22 Ω
CLK
CLKC
TTL/CMOS
Source
0.01 µF
CLK
CLKC
Node CLKC
Internally Biased
to IVDDń2
Figure 28. Driving the DAC5674 With a Single-Ended TTL/CMOS Clock Source
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CAC
0.01 µF
+
Differential
ECL
or
(LV)PECL
Source
CLK
CAC
0.01 µF
−
CLKC
RT
50 Ω
RT
50 Ω
VTT
Figure 29. Driving the DAC5674 With Differential ECL/PECL Clock Source
Single-Ended
ECL
or
(LV)PECL
Source
ECL/PECL
Gate
CAC
0.01 µF
CLK
CAC
0.01 µF
CLKC
RT
50 Ω
RT
50 Ω
VTT
Figure 30. Driving the DAC5674 With a Single-Ended ECL/PECL Clock Source
Supply Inputs
The DAC5674 comprises separate analog and digital supplies at AVDD, DVDD, and IOVDD. These supplies
can range from 3 V to 3.6 V for AVDD, 1.65 to 1.95 V for DVDD, and 1.65 to 3.6 for IOVDD.
DAC Transfer Function
The DAC5674 delivers complementary output currents IOUT1 and IOUT2. The DAC supports straight binary
coding, with D13 being the MSB and D0 the LSB. Output current IOUT1 equals the approximate full-scale output
current when all input bits are set high, i.e., the binary input word has the decimal representation 16383.
Full-scale output current flows through terminal IOUT2 when all input bits are set low (mode 0, straight binary
input). The relation between IOUT1 and IOUT2 can thus be expressed as:
IOUT1 = IOUTFS – IOUT2
Where IOUTFS is the full-scale output current. The output currents can be expressed as:
IOUT1 + IOUT
FS
CODE
16384
IOUT2 + IOUT
FS
16383 * CODE
16384
Where CODE is the decimal representation of the DAC data input word. Output currents IOUT1 and IOUT2
drive resistor loads (RL) or a transformer with equivalent input load resistance (RL). This would translate into
single-ended voltages VOUT1 and VOUT2 at terminal IOUT1 and IOUT2, respectively, of:
VOUT1 + IOUT1
24
R +
L
16384
CODE
IOUT
FS
R
L
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SLWS148 − SEPTEMBER 2003
VOUT2 + IOUT2
(16383–CODE)
R +
L
16384 IOUT
R
FS
L
The differential output voltage VOUTDIFF can thus be expressed as:
VOUT
DIFF
+ VOUT1–VOUT2 +
(2CODE–1683)
16384 IOUT
R
FS
L
The latter equation shows that applying the differential output results in doubling of the signal power delivered
to the load. Since the output currents IOUT1 and IOUT2 are complementary, they become additive when
processed differentially. Note that care should be taken not to exceed the compliance voltages at node IOUT1
and IOUT2, which would lead to increased signal distortion.
Reference Operation
The DAC5674 comprises a bandgap reference and control amplifier for biasing the full-scale output current.
The full-scale output current is set by applying an external resistor RBIAS. The bias current IBIAS through resistor
RBIAS is defined by the on-chip bandgap reference voltage and control amplifier. The full-scale output current
equals 32 times this bias current. The full-scale output current IOUTFS can thus be expressed as:
IOUT
FS
+ 32
I
BIAS
+
32
V
R
EXTIO
BIAS
where VEXTIO is the voltage at terminal EXTIO. The band-gap reference voltage delivers an accurate voltage
of 1.2 V. This reference is active when terminal EXTLO is connected to AGND. An external decoupling capacitor
CEXT of 0.1 µF should be connected externally to terminal EXTIO for compensation. The band-gap reference
can additionally be used for external reference operation. In that case, an external buffer with high impedance
input should be applied in order to limit the band-gap load current to a maximum of 100 nA. The internal
reference can be disabled and overridden by an external reference by connecting EXTLO to AVDD. Capacitor
CEXT may hence be omitted. Terminal EXTIO serves as either input or output node.
The full-scale output current can be adjusted from 20 mA down to 2 mA by varying resistor RBIAS or changing
the externally applied reference voltage. The internal control amplifier has a wide input range, supporting the
full-scale output current range of 20 mA.
Analog Current Outputs
Figure 31 shows a simplified schematic of the current source array output with corresponding switches.
Differential switches direct the current of each individual PMOS current source to either the positive output node
IOUT1 or its complementary negative output node IOUT2. The output impedance is determined by the stack
of the current sources and differential switches, and is typically >300 kΩ in parallel with an output capacitance
of 5 pF.
The external output resistors are referred to an external ground. The minimum output compliance at nodes
IOUT1 and IOUT2 is limited to −1 V, determined by the CMOS process. Beyond this value, transistor breakdown
may occur resulting in reduced reliability of the DAC5674 device. The maximum output compliance voltage at
nodes IOUT1 and IOUT2 equals 1.25 V. Exceeding the maximum output compliance voltage adversely affects
distortion performance and integral nonlinearity. The optimum distortion performance for a single-ended or
differential output is achieved when the maximum full-scale signal at IOUT1 and IOUT2 does not exceed 0.5
V.
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AVDD
S(1)
S(1)C
IOUT1
S(2)
S(2)C
S(N)C
Current Source Array
IOUT2
RLOAD
S(N)
RLOAD
Figure 31. Equivalent Analog Current Output
The DAC5674 can be easily configured to drive a doubly terminated 50-Ω cable using a properly selected RF
transformer. Figure 19 and Figure 20 show the 50-Ω doubly terminated transformer configuration with 1:1 and
4:1 impedance ratio, respectively. Note that the center tap of the primary input of the transformer has to be
grounded to enable a DC current flow. Applying a 20-mA full-scale output current would lead to a 0.5 VPP for
a 1:1 transformer and a 1 VPP output for a 4:1 transformer.
Figure 21 shows the single-ended output configuration, where the output current IOUT1 flows into an equivalent
load resistance of 25 Ω. Node IOUT2 should be connected to AGND or terminated with a resistor of 25 Ω to
AGND. The nominal resistor load of 25 Ω gives a differential output swing of 1 VPP when applying a 20-mA
full-scale output current.
50 Ω
1:1
IOUT1
100 Ω
AGND
RLOAD
50 Ω
IOUT2
50 Ω
Figure 32. Driving a Doubly Terminated 50-Ω Cable Using a 1:1 Impedance Ratio Transformer
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SLWS148 − SEPTEMBER 2003
100 Ω
4:1
IOUT1
RLOAD
50 Ω
AGND
IOUT2
100 Ω
Figure 33. Driving a Doubly Terminated 50-Ω Cable Using a 4:1 Impedance Ratio Transformer
IOUT1
RLOAD
50 Ω
IOUT2
50 Ω
50 Ω
AGND
Figure 34. Driving a Doubly Terminated 50-Ω Cable Using Single-Ended Output
Sleep Mode
The DAC5674 features a power-down mode that turns off the output current and reduces the supply current
to less than 5 mA over the supply range of 3 V to 3.6 V and temperature range. The power-down mode is
activated by applying a logic level 1 to the SLEEP pin (e.g., by connecting pin SLEEP to AVDD). An internal
pulldown circuit at node SLEEP ensures that the DAC5674 is enabled if the input is left disconnected. Power-up
and power-down activation times depend on the value of external capacitor at node SLEEP. For a nominal
capacitor value of 0.1-µF power-down takes less than 5 µs, and power-up takes approximately 3 ms.
DAC5674 Evaluation Board
There is a combo EVM board for the DAC5674 digital-to-analog converter for evaluation. This board allows the
user the flexibility to operate the DAC5674 in various configurations. Possible output configurations include
transformer coupled, resistor terminated, inverting/noninverting and differential amplifier outputs. The digital
inputs are designed to interface with a TMS320 DSP SDK or to be driven directly from various pattern
generators with the on-board option to add a resistor network for proper load termination.
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SLWS148 − SEPTEMBER 2003
PLL LOOP FILTER COMPONENTS
For the external second order filter shown in Figure 35, the components R, C1, and C2 are calculated for a
desired phase margin and loop bandwidth. The resistance R3 = 200 Ω and the capacitance is C3 = 8 pF are
internal to the DAC5674.
External
Internal
R3
C1
C2
C3
R1
Figure 35. External Second Order Filter
VCO GAIN
vs
FREQUENCY
500
450
VCO Gain − MHz
400
350
300
250
200
150
100
50
0
0
100
200
300
Frequency − MHz
400
500
600
Figure 36. Typical DAC5674 GVCO at 25°C
The VCO gain (GVCO) as a function of VCO frequency for the DAC5674 is shown in Figure 36. For a desired
VCO frequency, the loop filter values can be calculated using the equation below.
Nominal PLL design parameters include:
charge pump current: iqp = 1 mA
vco gain: Kvco = 2πxGvco rad/A
prescale/interpolation divide: N = {2,4,8,16,32}
phase detector gain: Kd = iqpx(2πN)−1 A/rad
Let,
desired loop band width = ωd
desired phase margin = φd
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SLWS148 − SEPTEMBER 2003
then,
ǒ
Ǔ
C1 + t1 1– t2
t3
C2 + t1–t2
t3
R+
t32
t1(t3–t2)
where
ǒ
Ǔ
K Kvco
t1 + d
tanf ) secf
d
d
2 ù
d
t2 +
1
w
d
ǒtanfd ) secfdǓ
t3 +
tanf ) secf
d
d
w
d
Example:
φd = 70 degrees, ωd = 1 MHz
then,
N
R (Ω)
C1 (ΜF)
C2 (PF)
2
43
0.02
670
4
86
0.01
335
8
173
0.005
167
16
346
0.002
84
32
692
0.001
42
The calculated phase margin and loop band width can be verified by plotting the gain and phase of the open
loop transfer function given by:
H(s) +
K vcoKd() sRC1)
s 3RC1C2 ) s 2(C1 ) C2)
Figure 37 shows the open loop gain and phase for the DAC5674 evaluation board loop filter.
GAIN
vs
FREQUENCY
PHASE
vs
FREQUENCY
−100
60
N = 2, 4, 8, 16, 32
40
−120
Phase − °
Gain − dB
20
0
−140
−20
−160
−40
−60
0.01
0.1
1
f − Frequency − MHz
10
100
−180
0.01
0.1
1
10
100
f − Frequency − MHz
Figure 37. Open Loop Phase and Gain Plots for the DAC5674 Evaluation Board
The phase error (φerr) phase and frequency step responses are given by the equations below and are plotted
in Figure 24 for the DAC5674 evaluation board loop filter.
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SLWS148 − SEPTEMBER 2003
f err + Df
ƪ1 ) w t–ǒw tǓ ƫ
f err + Dw
wn
ƪw t–ǒw tǓ ƫ
2
n
n
2
n
n
e –wnt
Phase step response
e –w nt
Frequency step response
NORMALIZED PHASE ERROR
vs
TIME
NORMALIZED PHASE ERROR
vs
TIME
1.0
1.0
Response to a Phase Step at Time 0
Response to a Frequency Step at Time 0
N = 2, 4, 8, 16, 32
0.8
Normalized Phase Error
Normalized Phase Error
N = 2, 4, 8, 16, 32
Increasing N
0.5
0.0
Increasing N
0.6
0.4
0.2
−0.5
0.0
0.5
1.0
1.5
2.0
2.5
t − Time − µs
3.0
3.5
4.0
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
t − Time − µs
Figure 38. Phase and Frequency Step Responses for the DAC5674 Evaluation Board
30
3.5
4.0
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