WINBOND W681307DG

W681307 Product Datasheet
USB1.1 CODEC Microprocessor
Control Unit with 32KB Mask ROM
and 4KB RAM.
-1-
Publication Release Date: May, 2007
Revision 1.3
W681307
AMENDMENT HISTORY
Changes (•: modified, √: added, ×: removed)
Ver
Date
1.0 2006/11/22
Filename
W681307_Data Sheet_V1.0
Author
MCSu
1.1 2006/12/02
W681307_Data Sheet_V1.1
MCSu
• Modify register 0x14C4.
• Modify Figure 14-2.
1.2 2006/12/28
W681307_Data Sheet_V1.2
MCSu
• Modify register 0x14E5.
1.3 2007/07/23
W681307_Data Sheet_V1.3
TYChiu • Modify endpoint table 18.2.1.
-2-
Reference
W681307_Data
Sheet_V1.0
W681307_Data
Sheet_V1.1
W681307_Data
Sheet_V1.2
Publication Release Date: May, 2007
Revision 1.3
W681307
CONTENTS
1.
GENERAL DESCRIPTION ..................................................................................................... - 9 2.
FEATURES ........................................................................................................................... - 10 3.
PIN CONFIGURATION ....................................................................................................... - 11 4.
PINS DESCRIPTION ............................................................................................................ - 12 5.
SYSTEM DIAGRAM............................................................................................................. - 17 5.1
Function Block Diagram................................................................................................... - 17 5.2
I/O Cells in Winbond MCU Chip .................................................................................... - 18 6.
ELECTRICAL CHARACTERISTICS ..................................................................................... - 20 6.1
Absolute Maximum Ratings............................................................................................. - 20 6.2
DC Characteristics............................................................................................................ - 20 6.3
Analog Transmission Characteristics ............................................................................... - 21 6.3.1
Amplitude Response for Analog Transmission Performance ....................................... - 21 6.3.2
Distortion Characteristics for Analog Transmission Performance ................................ - 21 6.4
Analog Electrical Characteristics ...................................................................................... - 22 6.5
Power Drivers – PO1, 2 .................................................................................................... - 22 6.6
Programmable Output Linear Regulator .......................................................................... - 23 6.7
USB PHY Electronic Characteristics ( 25°C, VDD_USB = 3.3V, DVDD1, 3 =1.9V) ............. - 23 6.8
USB PLL Electronic Characteristics ( 25°C, AVDD = 3.3V, DVDD1, 3 =1.9V).................... - 24 6.9
The Crystal Specification Requirement............................................................................. - 24 6.10
Recommended Crystal Specification ................................................................................ - 25 7.
MEMORY AND REGISTER MAP......................................................................................... - 26 7.1
Program Memory Map..................................................................................................... - 26 7.2
Data Memory Map........................................................................................................... - 26 7.3
Register Map.................................................................................................................... - 27 7.3.1
Mixer and Speech Logic Registers Overview ............................................................... - 27 7.3.2
Support Logic Registers Overview............................................................................... - 27 7.3.3
Interface Logic Registers Overview.............................................................................. - 28 7.3.4
Speech Interface Registers Overview ........................................................................... - 28 7.3.5
Processor Interface Registers Overview ....................................................................... - 29 7.3.6
Transcoder DSP Registers Overview............................................................................ - 29 7.3.7
Echo Canceller Registers Overview ............................................................................. - 30 7.3.8
Soft Clip Registers Overview ....................................................................................... - 31 7.3.9
CODEC Digital Part..................................................................................................... - 31 7.3.10
Sounder Path Select ..................................................................................................... - 31 7.3.11
Frequency Adjustment of Crystal Oscillator ................................................................ - 31 7.3.12
Specific Register........................................................................................................... - 31 7.3.13
VAG Selection ............................................................................................................. - 32 7.3.14
CODEC Control Register Overview............................................................................. - 32 7.3.15
Specific Registers ......................................................................................................... - 32 7.3.16
Test Cases and Debugging Registers Overview ........................................................... - 32 7.3.17
Charge Park Detection................................................................................................. - 32 7.3.18
DA High Pass Filter Selection ...................................................................................... - 33 7.3.19
TI PATH Selection ....................................................................................................... - 34 7.3.20
Network side / Acoustic side Power Measurement..................................................... - 34 7.3.21
PCM Highway Channel Registers Overview ............................................................... - 35 7.3.22
SPI Interface Registers Overview ................................................................................. - 35 7.3.23
Data Flash SPI Interface Registers Overview................................................................ - 36 -3-
Publication Release Date: May, 2007
Revision 1.3
W681307
7.3.24
W2S Interface Registers Overview ............................................................................... - 36 7.3.25
USB Control Registers Overview ................................................................................. - 37 7.3.26
ISP Mode ..................................................................................................................... - 38 8.
SUPPORT LOGIC ................................................................................................................. - 39 8.1
Clock Control & Reset 32K ............................................................................................... - 40 8.1.1
Overview..................................................................................................................... - 40 8.1.2
Functionality ............................................................................................................... - 40 8.1.3
Clock Enable Register .................................................................................................. - 40 8.2
Interrupt Control.............................................................................................................. - 41 8.2.1
Overview..................................................................................................................... - 41 8.2.2
Functionality ............................................................................................................... - 41 8.2.3
Interrupt Registers....................................................................................................... - 43 8.2.4
Extends of interrupt..................................................................................................... - 44 8.3
Ringer Tone Generator..................................................................................................... - 45 8.3.1
Overview..................................................................................................................... - 45 8.3.2
Functionality ............................................................................................................... - 45 8.3.3
Sounder Tone Register Definition ................................................................................ - 46 8.3.4
Sounder Volume Register Definition ........................................................................... - 46 8.3.5
Example of use ............................................................................................................ - 46 8.3.6
Sounder Registers........................................................................................................ - 47 8.4
PIEZO Tone Generator..................................................................................................... - 48 8.4.1
Overview..................................................................................................................... - 48 8.4.2
Functionality ............................................................................................................... - 48 9.
INTERFACE LOGIC ............................................................................................................. - 49 9.1
Keypad Scanner ............................................................................................................... - 49 9.1.1
Overview..................................................................................................................... - 49 9.1.2
Use of the Keypad Scanner .......................................................................................... - 50 9.1.3
Use of a Software Keypad Scanner............................................................................... - 50 9.2
I/O Ports.......................................................................................................................... - 50 9.3
Keypad Control Registers ................................................................................................ - 51 9.3.1
Key Location and Size Programming........................................................................... - 53 9.4
Timers.............................................................................................................................. - 53 9.4.1
Watch Dog Control...................................................................................................... - 54 9.4.2
Timer 1ms Control1 ..................................................................................................... - 54 9.4.3
Timer Control .............................................................................................................. - 54 9.4.4
1S Counter................................................................................................................... - 55 9.4.5
Watch Dog Kick........................................................................................................... - 55 9.4.6
1ms Counter ................................................................................................................ - 55 10. SPEECH INTERFACE........................................................................................................... - 56 10.1
Overview ......................................................................................................................... - 56 10.2
Functionality .................................................................................................................... - 56 10.3
PCM Serial Interface......................................................................................................... - 57 10.3.1
Use with Additional External Lines ............................................................................. - 57 10.3.2
I/O Ports ..................................................................................................................... - 57 10.3.3
Status of Speech Interface When Reset......................................................................... - 58 10.4
Internal CODEC Control .................................................................................................. - 58 10.5
PCM Interface Registers ................................................................................................... - 58 10.5.1
Speech Control 0.......................................................................................................... - 58 -4-
Publication Release Date: May, 2007
Revision 1.3
W681307
10.5.2
Specific Register........................................................................................................... - 58 10.5.3
Speech IO Direction ..................................................................................................... - 59 10.5.4
Speech IO Input Data................................................................................................... - 59 10.5.5
Speech IO Output Data................................................................................................ - 59 10.5.6
Speech IO Mask ........................................................................................................... - 60 10.5.7
Fsync Counter ............................................................................................................. - 60 10.6
The multiplexer to connect 5 PCM channels to 4 processor channels................................ - 60 10.6.1
Multiplexer control register ......................................................................................... - 60 10.7
PCM Highway Interface................................................................................................... - 61 10.7.1
The Introduction of PCM Modes ................................................................................. - 61 10.7.2
The Description of PCM Highway Interface Registers ................................................. - 63 10.8
Digital Gain Multiplexer .................................................................................................. - 66 10.8.1
Fine-Tuning Gain Stage Registers ................................................................................ - 66 11. PROCESSOR INTERFACE.................................................................................................... - 70 11.1
Overview ......................................................................................................................... - 70 11.2
Functionality .................................................................................................................... - 70 11.3
Processor Access Sequencer ............................................................................................. - 70 11.4
Read Multiplexer ............................................................................................................. - 73 11.5
Processor Interface Control Registers ............................................................................... - 73 11.5.1
AuxOpPort .................................................................................................................. - 73 11.5.2
DiagSel ........................................................................................................................ - 74 11.5.3
Diag_CS....................................................................................................................... - 75 11.5.4
Diag_CS3..................................................................................................................... - 76 11.5.5
Multiplier_Enable........................................................................................................ - 77 11.6
In System Programming Mode......................................................................................... - 77 11.6.1
Hardware Setting Usage.............................................................................................. - 77 11.6.2
Software Command Usage .......................................................................................... - 77 11.6.3
ISP_CTRL (Hardware & Watchdog Reset Control Register)......................................... - 78 11.6.4
Specific Register........................................................................................................... - 78 11.7
MASK ROM Mode........................................................................................................... - 79 11.7.1
Usage........................................................................................................................... - 79 12. SPEECH PROCESSOR .......................................................................................................... - 80 12.1
Transcoder DSP................................................................................................................ - 80 12.2
The Description of the Activation Registers...................................................................... - 81 12.2.1
MIXER_EN .................................................................................................................. - 81 12.2.2
SPEECH LOGIC_EN ................................................................................................... - 81 12.3
The Description of Transcoder DSP Registers................................................................... - 81 12.3.1
Connect0...................................................................................................................... - 82 12.3.2
Specified Register ........................................................................................................ - 82 12.3.3
Specified Register ........................................................................................................ - 82 12.3.4
Specified Register ........................................................................................................ - 82 12.3.5
PCMmode0.................................................................................................................. - 83 12.3.6
InputGain0 .................................................................................................................. - 83 12.3.7
OutputGain0 ............................................................................................................... - 83 12.3.8
ToneFreqA0................................................................................................................. - 83 12.3.9
ToneFreqB0 ................................................................................................................. - 84 12.3.10
ToneVolA0 .................................................................................................................. - 84 12.3.11
ToneVolB0 ................................................................................................................... - 84 -5-
Publication Release Date: May, 2007
Revision 1.3
W681307
12.3.12
ToneEna0..................................................................................................................... - 84 12.3.13
SideTone...................................................................................................................... - 85 12.3.14
Loopback_EN .............................................................................................................. - 85 12.3.15
Specified Register ........................................................................................................ - 85 12.3.16
Connect1 ~ ToneEna1 .................................................................................................. - 85 12.3.17
Connect2 ~ ToneEna2 .................................................................................................. - 85 12.3.18
SideToneChannel_Ena................................................................................................. - 86 12.3.19
Connect3 ~ ToneEna3 .................................................................................................. - 86 12.4
PCM Mixer Matrix ........................................................................................................... - 86 12.5
Gain Tables ...................................................................................................................... - 86 13. ECHO CANCELLER ............................................................................................................ - 89 13.1
Half AEC Block Diagram ................................................................................................. - 89 13.1.1
Acoustics Suppression ................................................................................................. - 89 13.1.2
Network Power Estimation.......................................................................................... - 90 13.1.3
Acoustic Power Estimation .......................................................................................... - 90 13.1.4
Auto Gain Control ....................................................................................................... - 91 13.2
The Software Interface of Speech Processor...................................................................... - 91 13.3
Activation Registers ......................................................................................................... - 91 13.3.1
UP_CONFIG................................................................................................................ - 91 13.3.2
UP_RESET................................................................................................................... - 92 13.3.3
EC_BELTA .................................................................................................................. - 92 13.3.4
Specific Register........................................................................................................... - 92 13.4
Performance Adjustment Registers .................................................................................. - 92 13.4.1
Acoustic Suppressor Register ...................................................................................... - 92 13.4.2
Acoustic Side Control Registers ................................................................................... - 93 13.4.3
Network Side Control Registers................................................................................... - 95 13.4.4
ACOUSTIC / NETWORK Active Status ...................................................................... - 98 13.4.5
AGC Control Registers ................................................................................................ - 98 13.4.6
Noise Suppressor Registers........................................................................................ - 100 13.4.7
AEC Soft Clip ............................................................................................................ - 101 13.5
Acoustic Side / Network Side Power Measurement....................................................... - 106 13.5.1
ACOUSTIC_SHORT_TERM_POWER ....................................................................... - 106 13.5.2
ACOUSTIC_LONG_TERM_POWER ......................................................................... - 106 13.5.3
ACOUSTIC_POWER_DEVIATION........................................................................... - 107 13.5.4
ACOUSTIC / NETWORK Active Status .................................................................... - 107 13.5.5
NETWORK_SHORT_TERM_POWER ....................................................................... - 107 13.5.6
NETWORK_LONG_TERM_POWER ......................................................................... - 108 13.5.7
NETWORK_POWER_DEVIATION........................................................................... - 108 13.5.8
ACOUSTIC / NETWORK Active Status .................................................................... - 108 14. SYSTEM FUNCTION.......................................................................................................... - 109 14.1
Power On Reset.............................................................................................................. - 109 14.1.1
CODEC On/Off Scheme............................................................................................ - 109 14.1.2
CODEC Digital Part................................................................................................... - 110 -
-6-
Publication Release Date: May, 2007
Revision 1.3
W681307
14.2
ADC Adaptive Bit Flip Probability................................................................................. - 110 14.3
Sounder Signal Selection ................................................................................................ - 111 14.4
Frequency Adjustment of Crystal Oscillator................................................................... - 112 14.5
Specific Register ............................................................................................................. - 113 14.6
VAG Selection................................................................................................................ - 113 14.7
TG Gain Register............................................................................................................ - 114 14.8
PO Gain Register............................................................................................................ - 115 14.9
The PCM CODEC .......................................................................................................... - 117 14.9.1
Block Diagram ........................................................................................................... - 117 14.9.2
Analog Interface and Signal Path............................................................................... - 117 14.9.3
Control Register: CODEC_CTRL ............................................................................... - 118 14.9.4
Specific Register......................................................................................................... - 119 14.9.5
Specific Register......................................................................................................... - 119 14.10
RECEIVE_DIAG............................................................................................................. - 119 14.11
Specific Register ............................................................................................................. - 121 14.12
EnAllClock..................................................................................................................... - 121 14.13
CODEC_Test_Sel ........................................................................................................... - 121 14.14
Test_SYSCLKOUT.......................................................................................................... - 122 14.15
BGP_LPF_EN................................................................................................................. - 122 14.16
CODEC Status Indicator................................................................................................. - 122 14.17
BandGap Voltage Adjustment........................................................................................ - 123 14.18
Specific Register ............................................................................................................. - 123 14.19
Linear Regulator Voltage Controller Register................................................................. - 123 14.20
Core PWR_Det ............................................................................................................... - 124 14.21
DA High Pass Filter Selection......................................................................................... - 124 14.22
TI Path Selection............................................................................................................. - 125 15. SERIAL PERIPHERAL INTERFACE................................................................................... - 127 15.1
Serial Peripheral Interface – SPI signals.......................................................................... - 127 15.1.1
SPI_Control 0............................................................................................................. - 128 15.1.2
SPI_Control 1............................................................................................................. - 128 15.1.3
SPI Status................................................................................................................... - 129 15.1.4
SPI Interrupt Enable .................................................................................................. - 129 15.1.5
DumpByte ................................................................................................................. - 129 15.1.6
Write TX FIFO ........................................................................................................... - 129 15.1.7
Read RX FIFO ............................................................................................................ - 130 15.1.8
SPI_Transfer_Size ...................................................................................................... - 130 15.1.9
SPI_Start_rtx.............................................................................................................. - 130 16. SPI FOR SERIAL DATA FLASH ......................................................................................... - 131 16.1
Introduction to SPI of Serial Data Flash .......................................................................... - 131 16.2
Block Diagram ............................................................................................................... - 131 16.3
Data Format ................................................................................................................... - 132 16.4
FSM................................................................................................................................ - 134 16.5
FIFO/RAM .................................................................................................................... - 134 16.6
Interrupt ........................................................................................................................ - 134 16.7
DF_SPI Register Group .................................................................................................. - 134 16.7.1
DF_CLK..................................................................................................................... - 134 16.7.2
DF_CMD_LEN .......................................................................................................... - 135 16.7.3
DF_DATA_LEN ........................................................................................................ - 135 -7-
Publication Release Date: May, 2007
Revision 1.3
W681307
16.7.4
DF_INTR_REG .......................................................................................................... - 135 16.7.5
DF_CMD_B1 ~ DF_CMD B5...................................................................................... - 136 16.7.6
DF_CLK_FORMAT ................................................................................................... - 137 16.7.7
DF_FIFO_DATA........................................................................................................ - 138 16.7.8
DF_CNT .................................................................................................................... - 138 16.7.9
DF_WR_CNT............................................................................................................. - 139 16.7.10
DF_RD_CNT ............................................................................................................. - 139 16.8
Example of W25X20/40/80 Serial Flash ......................................................................... - 139 17. WINBOND 2-WIRE SERIAL BUS ....................................................................................... - 141 17.1
Introduction to Winbond 2-Wire Serial bus .................................................................... - 141 17.2
The Description of W2S Register .................................................................................... - 141 17.2.1
W2S_Enable............................................................................................................... - 141 17.2.2
EEPROM_Config....................................................................................................... - 142 17.2.3
Prescale_Lo................................................................................................................ - 142 17.2.4
Prescale_Hi................................................................................................................ - 142 17.2.5
RdWrFIFO ................................................................................................................. - 143 17.2.6
Force_Activity ........................................................................................................... - 143 17.2.7
W2S_Status................................................................................................................ - 143 17.2.8
FIFORdPtr ................................................................................................................. - 144 17.2.9
FIFOWrPtr................................................................................................................. - 144 17.2.10
ForceAckFail.............................................................................................................. - 144 17.2.11
W2S_Misc .................................................................................................................. - 144 18. USB DEVICE CONTROLLER AND TRANSCEIVER .......................................................... - 145 18.1
Overview ....................................................................................................................... - 145 18.2
Functionality .................................................................................................................. - 145 18.2.1
Endpoints .................................................................................................................. - 146 18.2.2
Descriptor Rom ......................................................................................................... - 146 18.2.3
Configurations and Interfaces.................................................................................... - 147 18.2.4
Audio Class ............................................................................................................... - 148 18.2.5
HID Class .................................................................................................................. - 149 18.2.6
USB ISP mode............................................................................................................ - 150 18.2.7
Vendor Command ..................................................................................................... - 150 18.3
USB Registers................................................................................................................. - 150 18.3.1
USB Enable Register .................................................................................................. - 150 18.3.2
USB Interrupt Register A ........................................................................................... - 150 18.3.3
USB Interrupt Register B............................................................................................ - 151 18.3.4
EndPoint 0 – Control In/Out Registers ...................................................................... - 152 18.3.5
EndPoint 1 and 2 – ISO In/Out Registers................................................................... - 153 18.3.6
EndPoint 3 – Bulk In Registers................................................................................... - 155 18.3.7
EndPoint 4 – Bulk Out Registers ................................................................................ - 156 18.3.8
EndPoint 5 – Interrupt In Registers............................................................................ - 157 18.3.9
Specific Register......................................................................................................... - 158 18.3.10
Specific Register......................................................................................................... - 158 18.3.11
Specific Register......................................................................................................... - 158 19. PACKAGE DIMENSIONS .................................................................................................. - 159 -
-8-
Publication Release Date: May, 2007
Revision 1.3
W681307
1.
GENERAL DESCRIPTION
：
The main product targets for the USB CODEC MCU chip are
•
•
•
•
•
•
27.648MHz four cycle 8032 MCU
Support external Flash and easy transfer to low cost Mask ROM production
Universal Serial Bus (USB) v1.1 compliant device controller and PHY, capable of full speed communication (12MHz) with up
to 5 configuration end –points
8KHz voice sampling rate and 16bits of ADC/DAC
Support AEC/AGC for on-chip speaker phone support
Support Keypad function
Winbond MCU chip will be available in the following package
Device
Package
Description
W681307D xxxx
100 pin LQFP
Normal mode, Mask ROM 32K, x2 CLK
-9-
Publication Release Date: May, 2007
Revision 1.3
W681307
2.
FEATURES
Micro controller
•
Embedded 27.648MHz WINBOND Turbo 8032 Micro-Controller with 4 Clocks per Machine Cycle
•
4K system RAM, 32K MASK ROM
•
Core 1.9V, I/O 3.3V
•
Power on Reset circuit
•
Software Power Down mode
•
In system Programming (ISP) for 29/39/49 series flash ROM
•
Built-in Keypad Scan, Watchdog, Wait State
Speech Processor/Interface
•
4 Processor Channels
•
Programmable input/output gain stage
•
Programmable Auto Gain Control (AGC) stage
•
Programmable Soft Clip gain stage
•
Acoustic Echo Cancellation (AEC) with half duplex, absolute/relative mode
•
PCM interface for External CODEC or PCM interface
•
SNDR output
•
Built in DTMF tone generator
PCM CODEC
•
One Built-in PCM CODEC
•
Analogue input amplifier with Internal programmable gain stage
•
Analog output amplifier: Push pull drive, Internal programmable gain stage
USB 1.1
•
Universal Serial Bus USB v1.1 compliant device controller and PHY, capable of full speed communication (12MHz) with up to
5 configuration end –points.
UART
•
T8032 UART for data transmit application.
PCM Highway
•
The 1st PCM Highway has four channels..
•
All channels support 8/16 bits pcm format, and IOM2 mode.
•
Works in master or slave modes with external CODEC.
W2S
•
Support three EEPROM format page modes.
•
Support six kinds of W2S bus clocks.
SPI interface
•
Works in master or slave modes.
SPI Flash interface
•
Works in master with the Winbond SPI interface of series flash.
ISP
•
In-system-Programming capability with software command via UART or USB interface.
Package
•
100 pin LQFP package
- 10 -
Publication Release Date: May, 2007
Revision 1.3
W681307
VGAP
VAG
REG_CTRL
RESETC
AVDD1
AVDD2
PO2N
PO2 P
PO1N
83
82
81
80
79
78
77
76
T I1
87
84
TI2
88
85
T I2
89
TI 1
VSS_REG
90
AGND1
VDD_REG
91
86
DGND1
DVDD1
92
PLL_LPF
94
93
USB_DP
USB_DN
VSS_USB
VDD_USB
97
95
NC
98
96
SNDR_REF_CLK
99
PIN CONFIGURATION
100
3.
－ ＋ － ＋
KR0
1
75
PO1P
KR1
2
74
AGND 2
KR2
3
73
NC
KR3
4
72
NC
KR4
5
71
NC
KC0
6
70
NC
KC1
7
69
NC
KC2
8
68
NC
KC3
9
67
NC
PCM_IN
10
66
NC
PCM_ OUT
11
65
NC
PCM_ CLK
12
64
NC
PCM_FSC
13
ISP_WR
14
PSEN
ALE
W681307 D
100 PIN
LQFP
MASK ROM
63
NC
62
SYSCLKOUT
15
61
NC
16
60
DGND5
DVDD4
17
59
DVDD5
AD7
18
58
RESET_ OUT
AD6
19
57
GND_ OSC
XTAL2
AD5
20
56
AD4
21
55
XTAL1
AD3
22
54
VDD_ OSC
AD2
23
53
DVDD3
AD1
24
52
DGND3
AD0
25
51
EXT_ROM
P1.0
P1.1
P1.3/SCL
P1.2/SDA
50
48
49
47
P1.5/MOSI/SD I / CS3
P1.4/SCK
P1.6/MISO/SDO
46
44
RD
WR
45
43
CS1/ DF_CS
42
NC
41
A14
P3.0(RXD0)
35
A13
CS2 / SPI_CS (ISP_EN)
34
A12
40
33
A11
P3.1(TXD0)
32
A10
39
31
A9
38
30
A8
P3.5 /A1
29
DGND2
P3.4 /A0
28
DVDD2
37
27
36
26
- 11 -
Publication Release Date: May, 2007
Revision 1.3
W681307
PINS DESCRIPTION
4.
Pin
no.
Pin name
I/O
1
KR0
I/O
2
KR1
I/O
3
KR2
I/O
4
KR3
I/O
5
KR4
I/O
6
KC0
I/O
7
KC1
I/O
8
KC2
I/O
9
KC3
I/O
10
PCM_IN
I/O
11
PCM_OUT
I/O
12
PCM_CLK
I/O
13
PCM_FSC
I/O
14
ISP_ WR
O
15
PSEN
O
16
ALE
I/O
17
DVDD4
PWR
18
AD7
I/O
19
AD6
I/O
20
AD5
I/O
21
AD4
I/O
22
AD3
I/O
23
AD2
I/O
24
AD1
I/O
25
AD0
I/O
26
27
DVDD2
DGND2
PWR
PWR
State
during
Reset
Input
H
Input
H
Input
H
Input
H
Input
H
Input
L
Input
L
Input
L
Input
L
Input
H
Input
H
Input
L
Input
L
State
after
Reset
Input
H
Input
H
Input
H
Input
H
Input
H
Input
L
Input
L
Input
L
Input
L
Input
H
Input
H
Input
L
Input
L
Input
H
Input
H
Input
H
Input
H
Output
H
PC3B02U
8032T for Program Memory Strobe Enable
Output H
PC3B02U
Output address latch enable (ALE) function
-
-
PVDDC
Input
H
Input
H
Input
H
Input
H
Input
H
Input
H
Input
H
Input
H
-
Input
H
Input
H
Input
H
Input
H
Input
H
Input
H
Input
H
Input
H
-
Pin type
section
Function Description
Alternative Function
PC3B01U
Keypad Scan row output
GPIO
PC3B01U
Keypad Scan row output
GPIO
PC3B01U
Keypad Scan row output
GPIO
PC3B01U
Keypad Scan row output
GPIO
PC3B01U
Keypad Scan row output
GPIO
PC3B01D
Keypad Scan column input
GPIO
PC3B01D
Keypad Scan column input
GPIO
PC3B01D
Keypad Scan column input
GPIO
PC3B01D
Keypad Scan column input
GPIO
PC3B02U PCM high way, Data input
GPIO
PC3B02U PCM high way, Data output
GPIO
PCM high way, Clock
GPIO
In/Output
PCM high way, Frame pluse
GPIO
PC3B02D
In/Output
In the normal mode operation, this pin is high. In the inPC3B02U system-programming (PROG) state, this pin is used for
WR function for writing flash memory program.
PC3B02D
Digital supply voltage 4 (for digital I/O pads power)
PC3B02U
8032T Multiplexed Address/Data pin 7
PC3B02U
8032T Multiplexed Address/Data pin 6
PC3B02U
8032T Multiplexed Address/Data pin 5
PC3B02U
8032T Multiplexed Address/Data pin 4
PC3B02U
8032T Multiplexed Address/Data pin 3
PC3B02U
8032T Multiplexed Address/Data pin 2
PC3B02U
8032T Multiplexed Address/Data pin 1
PC3B02U
8032T Multiplexed Address/Data pin 0
PVDDR
PVSSR
Digital supply voltage 2 (for digital I/O pads power)
Digital ground 2 (I/O ground)
- 12 -
Publication Release Date: May, 2007
Revision 1.3
W681307
Input
H
Input
H
Input
H
Input
H
Input
H
Input
H
Input
H
Input
H
Input
H
Input
H
Input
H
Output
H
Output
H
Output
H
Output
H
Output
H
Output
H
Output
H
Input
H
Input
H
Input
H
Input
H
I/O
Input
H
Output
H
PC3T02
External Chip Select
General Purpose Output
I/O
Input
H
Output
H
PC3T02
External Chip Select
General Purpose Output
I/O
Input
H
Input
H
PC3B02U
8032T Read Strobe
P3.7 is 8032 I/O
Input
H
Input
H
Input
H
Input
H
PC3B02U
8032T Write Strobe
P3.6 is 8032 I/O
PC3B02U
Port 1 Bit 6
SPI function
Input
H
Input
H
PC3B02U
Port 1 Bit 5
SPI function or External
Chip Select
Input
H
Input
H
Input
H
Input
H
Input
H
Input
H
Input
H
Input
H
Input
H
Input
H
Input
H
29
A9
I/O
30
A10
I/O
31
A11
I/O
32
A12
I/O
33
A13
I/O
34
A14
I/O
35
NC
I/O
P3.5
/A1
P3.4
/A0
36
37
I/O
I/O
38
P3.1 /TXD0
I/O
39
P3.0 /RXD0
I/O
40
CS2 /
SPI _ CS
CS1 /
41
DF _ CS
RD
42
43
44
45
/P3.7
WR
/ P3.6
P1.6
/MISO/SDI
P1.5
/MOSI/SDO
/
I/O
I/O
I/O
CS3
P1.4
/SCK
P1.3
/SCL
P1.2
/SDA
I/O
49
P1.1
I/O
50
P1.0
I/O
51
EXT_ROM
I
52
DGND3
PWR
53
DVDD3
54
55
56
57
46
47
48
I/O
I/O
PC3B02U
8032T Address Line 9
PC3B02U
8032T Address Line 10
PC3B02U
8032T Address Line 11
PC3B02U
8032T Address Line 12
PC3B02U
8032T Address Line 13
PC3B02U
8032T Address Line 14
PC3B02U
No connection
PC3B02U
Port3 Bit 5 of 8032T
PC3B02U
Port3 Bit 4 of 8032T
PC3B02U
PC3B02U
PC3B02U
PC3B02U
PC3B02U
Port 3 Bit 1 or TXD serial transmit data port of internal 8032
Turbo
Port 3 Bit 0 or RXD serial receive data port of internal 8032
Turbo
Port 1 Bit 4 or SPI interface
This pin also supports wait
clock output
state function.
Port 1 Bit 3 or W2S interface clock output of programming
EEPROM.
Port 1 Bit 2 or W2S interface serial data of programming
EEPROM.
PC3B02U
Port 1 Bit 1
PC3B02U
Port 1 Bit 0
Input
PC3D01U
When set this pin to high then the chip goes into external
ROM mode.
-
-
PVSSC
PWR
-
-
PVDDC
VDD_OSC
XTAL1
XTAL2
PWR
I
O
Active
Active
Active
Active
PVDDC
PAnalog
PAnalog
Digital supply voltage 3 for core power, which should
connect to DVDD1.
Oscillation circuits supply voltage.
13.824Mhz Crystal oscillator output
13.824Mhz Crystal oscillator input
GND_OSC
PWR
-
-
PVSSC
Oscillation circuits ground
Digital ground 3 (core power ground)
- 13 -
Publication Release Date: May, 2007
Revision 1.3
W681307
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
RESETOUT
DVDD5
DGND5
NC
SYSCLKOUT
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AGND2
O
PWR
PWR
O
O
O
O
O
O
O
O
O
O
O
O
I
PWR
L
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Hi-Z
-
H
Tristate
L
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Tristate
Hi-Z
-
PC3o01
PVDDC
PVSSC
PC3T02
PC3T02
PC3T02
PC3T01
PC3B01
PC3T01
PC3T01
PC3T02
PC3T02
PC3T02
PC3T01
Analog
Analog
PVSSC
75
PO1P
O
Tristate
Tristate
PAnalog
76
PO1N
O
Tristate
Tristate
PAnalog
77
PO2P
O
Tristate
Tristate
PAnalog
78
PO2N
O
Tristate
Tristate
PAnalog
79
80
AVDD2
AVDD1
PWR
PWR
-
-
PVDDC
PVDDC
81
RESETC
O
Tristate
Tristate
PAnalog
82
REG_CTRL
O
Active
Active
PAnalog
83
VAG
O
Tristate
1.5V
PAnalog
84
VBGP
O
1. 0V
1.0V
Panalog
Chip reset indication output. Active high after the reset state.
Digital supply voltage 5 (for digital I/O pads power)
Digital ground 5 (I/O ground)
No connection
13.824 MHz system clock output
No connection
No connection
No connection
No connection
No connection
No connection
No connection
No connection
No connection
No connection
No connection
Analog ground for OP2 output amplifier
Power amplifier output (non-inverting) - This pin is the noninverting power amplifier output, which is an inverted
version of the signal at PO1N. This pin is capable of driving
a 120 Ω load to PO1N at 3V supply power. This pin is D.C.
referred to the VAG pin. This pin is tri-state when the chip is
in analog CODEC power down mode.
Power amplifier output (inverting) - This pin is the inverting
power amplifier output. This pin is capable of driving a 120
Ω load to PO1P at 3V supply voltage. This pin is D.C.
referenced to the VAG pin. The PO1P and PO1N outputs are
differential. This pin is tri-state when the chip is in analog
CODEC power down mode.
Power amplifier output (non-inverting) - This pin is the noninverting power amplifier output, which is an inverted
version of the signal at PO2N. This pin is capable of driving
a 16 Ω load to PO2N at 3V supply power. This pin is D.C.
referred to the VAG pin. This pin is tri-state when the chip is
in analog CODEC power down mode.
Power amplifier output (inverting) - This pin is the inverting
power amplifier output. This pin is capable of driving a 16 Ω
load to PO2P at 3V supply voltage. This pin is D.C.
referenced to the VAG pin. The PO2P and PO2N outputs are
differential. This pin is tri-state when the chip is in analog
CODEC power down mode.
Analog supply voltage for OP2 amplifier
Analog supply voltage
It should connect a capacitor for internal power on reset
circuit.
Output signal of 3V linear regulator to drive the PNP
transistor.
Analog reference voltage. This pin possesses the analog
virtual ground of internal CODEC circuits.
The Band gap output voltage. It is 1.0V volt typically.
85
AGND1
PWR
-
-
PVSSC
Analog ground
86
TI1+
I
Hi-Z
Hi-Z
PAnalog
87
TI1-
I
Hi-Z
Hi-Z
PAnalog
88
TI2+
I
Hi-Z
Hi-Z
PAnalog
89
TI2-
I
Hi-Z
Hi-Z
PAnalog
This is the non-inverting input of the transmission
operational amplifier TG1.
This is the inverting input of the transmission operational
amplifier TG1.
This is the non-inverting input of the transmission
operational amplifier TG2.
This is the non-inverting input of the transmission
operational amplifier TG2.
- 14 -
Publication Release Date: May, 2007
Revision 1.3
W681307
90
VSS_REG
PWR
-
-
PVSSC
Ground of 3.0V linear regulator.
91
VDD_REG
PWR
-
-
PVDDC
3.3V input of 3.0V linear regulator.
92
DVDD1
PWR
-
-
PVDDC
93
DGND1
PWR
-
-
PVSSC
94
PLL_LPF
O
Tristate
Tristate
Panalog
95
VSS_USB
PWR
-
-
PVSSC
96
USB_DP
Analog
I/O
Hi-Z
Hi-Z
PAnalog
97
USB_DN
Analog
I/O
Hi-Z
Hi-Z
PAnalog
98
VDD_USB
PWR
-
-
PVDDC
99
NC
I
Input
Input
PC3D21
100
SNDR
O
Output
L
Output
L
PC3B02U
1.9V linear regulator output for internal digital core power
supply. Connect a large capacitor (>10uF) for output
regulation.
Digital ground 1
(core power ground)
Internal 48MHz PLL charge pump output. Put a passive LPF
filter in the pin to ground.
USB analog front end ground.
USB D+ connection. Series termination resistors (22Ω±1%)
are required for impedance of USB bus. The USB Spec1.1
states that the impedance of each driver is required to be
between 28 and 44Ω. This chip drive output resistance is 8 to
10Ω. Therefore, the 22Ω±1% series resistors are used.
USB D- connection. Series termination resistors (22Ω±1%)
are required for impedance of USB bus. The USB Spec1.1
states that the impedance of each driver is required to be
between 28 and 44Ω. This chip drive output resistance is 8 to
10Ω. Therefore, the 22Ω±1% series resistors are used.
USB analog front end supply power. Full speed devices are
identified by pulling D+ to 3.3V±0.3 Volts via a 1.5kΩ±5 %
resistor. The baseband chip inside has been built in the
1.5kΩ±20% resistor and the default is disconnected to
VDD_USB. The
No connection
Sounder output - This is a control pin to turn on/off the
external transistor, which is used to supply the high peak
currents that magnetic sounders typically require.
* When /CS2 is pull low in the initial power on state. Then the chip will enter into the hardware ISP mode to
download the system program code via UART or USB ports.
、
：
* P1.2; P1.3 and P1.4 multiple functions
W2S_ENA 0x1740[7 ]&
(W2 S_ Prot_Sel 0x1740[6 ])
W2S_ENA 0x1740[7 ]&
~(W2S_Prot_Sel 0x1740 [6])
W2 S_ENA 0x1740[7] &
~(W2S_Prot_Sel 0x1740 [6])
P1.3
P1. 2
0
P1.2
SDA
0
0
1
SDA
1
P1.3
1
SCL
Piezo_ENB
0x144 B[ 0]
P1. 4
0
Piezo_CLK
1
SPI_ENB
0x1720 [7]
DF _ENB
0x1730[7]
W2 S_ENA 0x1740[7] &
(W2S_ Prot_Sel 0x1740[6 ])
0
0
SPI_SCK
1
0
DF_SCK
1
P1.4
SCL
- 15 -
1
Publication Release Date: May, 2007
Revision 1.3
W681307
：
* P1.5 and P1.6 multiple functions
P1.5_ Sel [B2]
( 0x150C [B2] )
CS3_Enable [B4]
( 0x150C [B4] )
/CS3
SPI_ ENB
X
1
0
1
0
0
P1.5
3
X
2
X
1
P1.6
0
1
SDI
(DF_SPI)
P1.6_ Sel [1:0]
( 0x150C [1:0] )
P1.6
P1.5/ MOSI / SDI / /CS3
MOSI
( SPI Master Output ;
Slave Input)
SPI_ ENB
DF_ ENB
0
MISO
( SPI Master Input ;
Slave Output )
0
1
SDO
(DF_SPI)
P1.6/MISO / SDO
1
：
* P3.4 and P3.5 multiple functions
P3.4_A0_Sel
150C[5]
P3.4
A0
0
1
X
UART_RXD1
SIM_CLK
P3.5_A1_Sel
150C[6]
P3.5
UART_EN &
SIM_EN
1554[7-6]
00
01
10
11
P3.4/ A0/
RXD1/SIM_CLK
UART_EN
1554[7]
0
0
A1
1
P3.5/ A1/ TXD1
UART_TXD1
1
- 16 -
Publication Release Date: May, 2007
Revision 1.3
W681307
5.
5.1
SYSTEM DIAGRAM
Function Block Diagram
：
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
The function block diagrams of the MCU chip and speech interface are shown below
75
1
74
2
KeyPad
3
USB
73
CODEC
4
72
5
71
6
70
7
69
PCM & MIXER
8
AEC
68
9
67
10
66
11
65
12
64
63
13
32K
MASK
ROM
14
15
16
Winbond
Turbo
8032
17
18
19
20
62
4K
RAM
61
60
59
58
57
56
55
21
54
22
UART
23
SPI
W2S
53
24
52
25
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
- 17 -
Publication Release Date: May, 2007
Revision 1.3
W681307
5.2
I/O Cells in Winbond MCU Chip
Chartered Semiconductor (Artisan) 0.25um Integral I/O cell library
PC3B02U
3V CMOS 3-State I/O Pad with Pull-up Resistor, 2mA
VDD
OEN
I
PAD
CIN
Figure 5-1: PC3B02U pad
PC3B02D
3V CMOS 3-State I/O Pad with Pull-down Resistor, 2mA
OEN
I
PAD
CIN
VSS
Figure 5-2: PC3B02D pad
PC3o02
3V CMOS Output Pad, 2mA
I
PAD
Figure 5-3: PC3o02 pad
PC3D01D
3V CMOS Input only Pad with Pull-down Resistor
CIN
PAD
VSS
Figure 5-4: PC3D01D pad
- 18 -
Publication Release Date: May, 2007
Revision 1.3
W681307
PC3D01U
3V CMOS Input only Pad with Pull-up Resistor
VDD
CIN
PAD
Figure 5-5: PC3D01U pad
PC3D21U
3V CMOS Schmitt non inverting Input only Pad with Pull-up Resistor
VDD
CIN
PAD
Figure 5-6: PC3D01D pad
PC3T01/02
3V CMOS 3-State Output Pad, 1mA/2mA
OEN
I
PAD
Figure 5-7: PC3T01 pad
- 19 -
Publication Release Date: May, 2007
Revision 1.3
W681307
6.
ELECTRICAL CHARACTERISTICS
6.1
Absolute Maximum Ratings
(Voltage Referenced to AGND pin)
PARAMETER
SYMBOL
RATING
UNIT
Core Power Supply Voltage, pin 53, 92
DVDD
1.9
V
I/O Power Supply Voltage, pin 17, 26, 59
IOVDD
2.7 ~ 3.6
V
AVDD
3.0 ~ 3.6
V
Power Supply Voltage , pin 80
DC Supply Voltage for USB Ouput Stage
VDD_USB
3.0 ~ 3.6
Operating Temperature
TOP
-10 to +55
Storage Temperature
TSTG
-85 to +85
V
℃
℃
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
6.2
DC Characteristics
(AGND = 0 volt TOP = -10 to +55
PARAMETER
℃)
SYM.
CONDITION
MIN.
TYP.
MAX
.
UNIT
Core Operating Current
Icore
-
6
-
mA
I/O Operating Current
II/O
-
6
-
mA
Analog Operating Current
IANA
5
mA
Input High Voltage
VIH
All digital input pins
VDD
×0.7
Input Low Voltage
VIL
All digital input pins
0
-
VDD
×0.3
V
Output High Voltage
VOH
DT, SSP Tx
VDD×
0.75
-
-
V
Output Low Voltage
VOL
DT, SSP Tx
0
-
Input High Current
IIL
AGND ≤ Vin ≤ AVDD
-10
Input Low Current
IIH
Input Capacitance
CIN
AGND ≤ Vin ≤ AVDD
All digital input pins to
AGND
- 20 -
-
-
V
-
VDD×
0.25
+10
µA
-10
-
+10
µA
-
-
10
pF
V
Publication Release Date: May, 2007
Revision 1.3
W681307
6.3
Analog Transmission Characteristics
(AVDD =+3.0V ±5%, AGND = 0 volt , Top = -10 to +55° C ; all analog signal referenced to VAG; 64 Kbps PCM; FST = FSR = 8 KHz; BCLKT =
BCLKR = 1.536 MHz; MCLK = 13.824 MHz ; Unless otherwise noted)
6.3.1
Amplitude Response for Analog Transmission Performance
PARAMETER
Absolute Level *
Max. Transmit Level
Frequency Response,
Relative to 0 dbm0 @
1020Hz
Gain Variation vs Level
Tone
(1020 Hz relative to -10
dBm0)
6.3.2
SYM.
CONDITION
A/D
TYP.
D/A
UNIT
MIN.
MAX.
MIN.
MAX.
LABS
0 dBm0 = -3.0 dBm
@ 600
0.549
---
---
---
---
Vrms
TXMAX
---
VAG 1dB
---
---
---
---
Vpk
15 Hz
---
---
---
-60
-0.5
50 Hz
---
---
---
-40
-0.5
100 Hz
---
---
---
-20
-0.5
200 Hz
---
---
-3
-5
-0.5
300 to 3000 Hz
---
---
-0.20
+0.15
-0.20
3300 Hz
---
---
-0.35
+0.15
-0.35
3400 Hz
---
---
-0.5
0
-0.5
4000 Hz
---
---
---
-12
---
4600 to 7000 Hz
---
---
---
-40
---
+3 to -40 dBm0
---
-0.3
+0.3
-0.2
+0.2
-40 to -50 dBm0
---
-1.0
+1.0
-0.4
+0.4
-50 to -55 dBm0
---
-1.6
+1.6
-0.8
+0.8
GRTV
GLT

dB
dB
Distortion Characteristics for Analog Transmission Performance
PARAMETER
Absolute Group Delay
Group Delay
Referenced to 1600 Hz
Total Distortion vs.
Level Tone
(1020 Hz, Mu-Law, CMessage)
SYM.
CONDITION
TRANSMIT
RECEIVE
TYP
.
MA
X.
MI
N.
MA
X.
UNIT
MIN.
DABS
1600 Hz
---
---
250
---
200
µS
DRTV
500 to 600 Hz
600 to 1000 Hz
1000 to 2600 Hz
2600 to 2800 Hz
2800 to 3000 Hz
-----------
-----------
250
200
70
100
145
-----------
30
20
70
120
200
µS
DLT
+3 dBm0
0 to -30 dBm0
-40 dBm0
-45 dBm0
---------
36
36
29
25
---------
34
36
30
25
---------
dBC
- 21 -
Publication Release Date: May, 2007
Revision 1.3
W681307
6.4
Analog Electrical Characteristics
(OP Amplifer TG and VAG; AVDD = +3.0V ±5%, AGND = 0V; Top = -10 to +55° C)
PARAMETER
SYM.
CONDITIONS
MIN.
TYP.
MAX.
TI1+, TI1TI2+, TI2-
---
±0.01
±1.0
Input Current of TG
AC Input Impedance to VAG
for TG (1 kHz)
RTIIN
TI1+, TI1TI2+, TI2-
---
1.0
Input Capacitance of TG
CTIIN
TI1+, TI1TI2+, TI2-
---
---
Input Offset voltage of TG
VOFIN
TI1+, TI1TI2+, TI2-
---
---
Input Common Mode Voltage
of TG
VCMV
TI1+, TI1TI2+, TI2-
0.5
---
Input Common Mode
Rejection Ratio of TG
TI1+, TI1TI2+, TI2-
Gain Bandwidth Product of
TI1+, TI1TI2+, TI2-
TG

µA
M
pF
25
mV
AVDD–
0.8
60
V
dB
100
KHz
975
Rload ≥ 10 K
(10kHz)
DC Open Loop Gain of TG
Rload ≥ 10 K
TI1+, TI1TI2+, TI2-

6.5
UNIT
80
dB
95
Bandgap voltage
VBGAP
Ref to AGND
1.0
V
VAG Output Voltage
VVAG
Ref to AGND
1.5
V
VAG Output Current with less
than 50 mV change in output
voltage
IVAG
VVAG
1
mA
Power Supply Rejection Ratio
PSRR
50mV
TG
---
55
dB
---
Power Drivers – PO1, 2
( AVDD = +3.0V ±5%, AGND = 0V; Top = -10 to +55° C)
PARAMETER
SYM.
Output Offset Voltage of PO1+
(PO2+) relative to PO1-(PO2-)
CONDITIONS
MIN.
TYP.
Inverted Unity Gain
for PO-
MAX.
30
UNIT
mV
PO1+(PO2+), PO1-(PO2-) Output
Current @ VAG=1.5V, RL=120,
THD<1%
VAG-0.7 V ≤
PO+ ,PO- ≤
VAG+0.7 V
6
mA
PO1+(PO2+), PO1-(PO2-) Output
Resistance
Inverted Unity Gain
for PO-
10
Ω
Gain Bandwidth Product @ 10 kHz
Open Loop for PO-
433
kHz
Load Capacitance for PO
CLAP
PO- to PO+
---
Gain of PO1+(PO2+) relative to PO1(PO2-)
---
300
pF
0
0.2
dB
Load Resistance differentially for PO1
RLDAP
PO1- to PO1+
---
120
---
Load Resistance differentially for PO2
RLDAP
PO2- to PO2+
---
16
---
- 22 -
Ω
Ω
Publication Release Date: May, 2007
Revision 1.3
W681307
6.6
Programmable Output Linear Regulator
Linear Regulator 1 (REG1) T = 25°C, External Transistor PNP: BC807-25
PARAMETERS
Current Consumption during
Operation
TEST CONDITIONS
MIN.
TYP.
Idle,
Current Consumption during
Power off
Drop Out Voltage
Iout= 100mA
Input Voltage
6.7
MAX.
UNIT
50
uA
1
nA
0.3
V
3.3
3.6
V
3.0
3.3
V
Programmable Output Voltage
Range
Iout= 100mA
Maximum Output Current
(PNP)
The characteristics vary with the
associated external components (PNP).
250
mA
Load Regulation (PNP)
Vin= 3.3V, Vout=3.0V, Iout= 100mA
50
mV
Line Regulation (PNP)
Vin=3.3V...3.6V, Vout=3.0V,
Iout= 100mA
50
dB
REG_CTRL Sink Current
Vin=3.3V, Vout=3.0V*0.95
Tbf
mA
REG_CTRL leakage Current
during Power Off
Vin= 3.3V, Vout= tristate
0.1
uA
USB PHY Electronic Characteristics ( 25°C, VDD_USB = 3.3V, DVDD1, 3 =1.9V)
PARAMETER
SYM.
DC Supply Voltage for USB
Ouput Stage
VDD_USB
MIN.
TYP.
MAX.
3.0
3.3
3.6
USB_DP
USB_DN
0
VDD_USB
3.6
Input High
VIH
2.0
Input Low
VIL
Differential Input Sensitivity
VDI
0.2
Differential Common-mode
Range
VCM
0.8
Single-end Receiver
threshold
VSE
0.8
Output Low
VOL
Output High
VOH
2.8
Output signal cross Voltage
VCRV
1.3
Pull-up Resistor
RUP
Driver Output Resistance
ZDRV
Transceiver Capacitance
CIN
Driver Rise Time
TR
Input Voltage Range for
USB_DP/DN
CONDITIONS
---
2.5
2.0
- 23 -
4
V
V
V
V
V
1.5
8
CL = 50pF
V
V
0.3
1.2
V
V
0.8

UNIT
8
2.0
V
1.8
KΩ
12
Ω
20
pF
15
ns
Publication Release Date: May, 2007
Revision 1.3
W681307
Driver Fall Time
6.8
TF
8
15
ns
90
100
111
%
Rise and Fall Time Matching
TLRLF
TLRLF = TLR/ TLF
VDD_USB Supply Current
* (exclude internal pull high
resistor)
IUSB
Standby
10
nA
Input Mode
2
mA
Output Mode
2
mA
USB PLL Electronic Characteristics ( 25°C, AVDD = 3.3V, DVDD1, 3 =1.9V)
PARAMETER
Operation Current
PLL Shut-Down Current
Operation Voltage
SYM.
CONDITIONS
IPLL
VCOFREQ =
96MHz,
FOUTFREQ =
48MHz
MIN.
TYP.
MAX.
UNIT
mA
IPLL_DN
uA
VPLL
3.0
3.3
3.6
V
Input Clock Frequency Range
FIN
13.824
MHz
Comparison Frequency
FREF
768
KHz
PLL Output Frequency
FOUT
48
MHz
VCO Frequency
FVCO
Ouput Duty Cycle
6.9
4
---
96
---
MHz
40
50
60
%
PLL Short-Term Peak To Peak
Output Jitter
TJITTER
ps
PLL Lock In Time
TREADY
ms
The Crystal Specification Requirement
The below figure is shown the electrical equivalent circuit for a crystal and the parameters are used for the crystal circuit.
C O = 5 .1 p F
R c = 3 0 o h m
L c = 5 .9 9 m H
- 24 -
C c = 2 2 .1 2 fF
Publication Release Date: May, 2007
Revision 1.3
W681307
6.10
Recommended Crystal Specification
The following crystal specifications are recommended for a proper cooperation between the crystal and baseband crystal oscillator.
Correct coordination guarantees great reliability and low failure rates in production.
Parameter
Min.
Frequency
Tolerance of center frequency
Tolerance over operation range
Crystal current
Load capacitance
Dynamic capacitance Cc
Resonance resistance Rc
Electrostatic capacitance
Aging
Limit values
Type.
Max.
13.824
-10
-5
MHz
+10
+5
ppm
ppm
±3
pF
fF
Ω
pF
ppm/year
18
22.12
40
5.1
- 25 -
Unit
Condition
Fundamental
mode
25°C ±3°C
0°C to 55°C
Publication Release Date: May, 2007
Revision 1.3
W681307
7.
7.1
MEMORY AND REGISTER MAP
Program Memory Map
Program area memory is mapped from 0x0000 to 0xFFFF, this can be used by external ROM.
7.2
Data Memory Map
Data memory address
Size
Function
0x0000 - 0x0FFF
0x1000 - 0x143F
(except for 0x1401 and 0x1420)
0x1440 - 0x144F
0x1450 - 0x145F
(4KB)
(1KB)
Not allocated
Blocked for test modes (0x1401 and 0x1420 are activation registers)
(16B)
(16B)
0x1460 - 0x1466
0x1467
0x1468 - 0x146F
0x1470 - 0x1474, 0x150C
(0x1475 ~ 0x147F: To Be Defined)
0x1480 - 0x14BF
(0x1487, 0x1497, 0x149D ~ 0x149F,
0x14A7, 0x14AD ~ 0x14AE, 0x14B7,
0x14BD ~ 0x14BF: To Be Defined)
0x14C0 - 0x14FF
(07B)
(01B)
(15B)
(06B)
Support Logic
Interface Logic
Speech interface
Multiplexer to connect 5 PCM channels to 4 DSP channels
Fine tune gain
(0x14FA~ 0x14FF: To Be Defined)
0x1500 - 0x151F
Comment
Processor Interface (AuxOpPort,DiagSel,Diag_CS,Diag_CS3,Multiplier_enable)
(52B)
Transcoder DSP Registers
(58B)
Half Acoustic Echo Canceller Registers
(24B)
MCU System Register
(0x1516 ~ 0x1517, 0x1519, 0x151B ~
0x151F: To Be Defined)
0x1520 - 0x157F (except for 0x1521)
(96B)
Blocked for test modes (0x1521 is TI path selection register)
0x1580 - 0x15BF
0x15C0 - 0x15CF
(64B)
(14B)
(Reserved)
(0x15C7, 0x15CF: To Be Defined)
Acoustic side / Network side Power Measurement
0x15D0 - 0x16FF
(304B)
(Reserved)
0x1700 – 0x171F
(11B)
PCM highway
(0x1705 ~ 0x1707, 0x170D ~ 0x170F,
0x1711 ~ 0x171F: To Be Defined)
0x1720 – 0x1728
(9B)
Master or slave SPI interface
0x1729 ~ 0x172F: To Be Defined)
0x1730 ~ 0x173F
(16B)
Data Flash SPI interface
0x1740 – 0x175F
(11B)
W2S interface
(0x174B ~ 0x175F: To Be Defined)
0x1760 – 0x177B
(27B)
Blocked for test modes
(0x1764: To Be Defined)
0x1800 ~ 0x187F
(127)
USB control registers
0x1900 ~ 0x1901
(2B)
ISP mode control register
0x5000 - 0x6FFF
(8KB)
Reserved for On-chip Expansion
0x7000 - 0x7FFF
(4KB)
On chip data RAM
*4
0x8000 - 0xEFFF
(4-28KB) External data RAM programmable selected by CS1
*2
0xF000 - 0xFFFF
(4KB)
External data RAM selected by CS2
*3
*1. Specific registers are blocked for test modes of hardware logic functions.
*2. The On-chip RAM is contiguous with CS1, which is used for off chip RAM.CS2 is the same.
*3. CS1 is a programmable address range, CS1 can be programmable range starting at 0x8000 and ending at 0xEFFF, with step 4K. CS2 is the same.
*4. In the event of further on chip RAM being required this can be put in this reserved location, hence on-chip and off chip RAM will remain contiguous.
The address decoding logic in this chip will not decode this area.
- 26 -
Publication Release Date: May, 2007
Revision 1.3
W681307
7.3
7.3.1
Register Map
Mixer and Speech Logic Registers Overview
Address
Name
0x1401
Mixer_En
Mode
Value At
Reset
R/W
0x00
Function
Enable the mixer block.
Enable the four channels of speech logic interface (which is
0x1420
SPEECH LOGIC_EN
R/W
0x04
not needed by the CODEC).
(0x1000 ~ 0x143F are blocked for test modes except for 0x1401 and 0x1420)
7.3.2
Support Logic Registers Overview
Address
Name
0x1440
0x1441
0x1442
0x1443
0x1444
0x1445
0x1446
0x1447
0x1448
0x1449
0x144A
0x144B
0x144C
0x144D
0x144E
0x144F
ClockEnable
IntrptSource0
IntrptSource1
IntrptEnable0
IntrptEnable1
IntrptPriority0
IntrptPriority1
SounderTone1
SounderTone2
SounderVol1
SounderVol2
PIEZO Function
PIEZO Clock output
IntrptSource2
IntrptEnable2
IntrptPriority2
Mode
Value At
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x78
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
- 27 -
Function
Clock 3, 4 & 5 Enable Bits and Reset 32K logic
Interrupt source register 0
Interrupt source register 1
Interrupt enable register 0
Interrupt enable register 1
Interrupt priority register 0
Interrupt priority register 1
Sounder frequency control register 1
Sounder frequency control register 2
Sounder volume control register 1
Sounder volume control register 2
PIEZO Enable and frequency select
Output the PIEZO driving clock
Interrupt source register 2
Interrupt enable register 2
Interrupt priority register 2
Publication Release Date: May, 2007
Revision 1.3
W681307
7.3.3
Interface Logic Registers Overview
Mode
Value At
Reset
KeyIoDR
R/W
0x1F
0x1451
0x1452
0x1453
0x1454
0x1455
0x1456
0x1457
KeyIoDC
KeyIoIpR
KeyIoIpC
KeyIoOpR
KeyIoOpC
KeyIoMskR
KeyIoMskC
R/W
R/W
R/W
0x1F
Undefined
Undefined
Undefined
Undefined
0x00
0x00
0x1458
KeyLocation
R
0x00
0x1459
KeyPadSize
R/W
0x00
0x145A
0x145B
0x145C
0x145D
0x145E
0x145F
Watch Dog Control
Timer 1ms Control1
Timer Control
1S Counter
Watch Dog Kick
1mS Counter
R/W
R/W
R/W
R/W
R/W
R
0x00
0x00
0x00
0x00
0x00
0x00
Address
Name
0x1450
7.3.4
Function
- Row Keys IO Port Direction Control &
Wake up enable
Col Keys IO Port Direction Control
Row Keys IO Port Input Data Register
Col Keys IO Port Input Data Register
Row Keys IO Port Output Data Register
Col Keys IO Port Output Data Register
Row keys IO Port Control Register for Mask
Col keys IO Port Control Register for Mask
Gives the Row and Column numbers of the last detected
key press
Sets the size of the Keypad scanned by the Keypad Scanner
function
Control watchdog and keypad bounce
Control the 1ms Timer
Reset the 1ms, 1S, 1min Timer
Second counter 0-59
Reset the watchdog
1ms counter, reset, enable bit and counter value
Speech Interface Registers Overview
Address
Name
0x1460
0x1461
0x1462
0x1463
0x1464
0x1465
0x1466
0x1467
0x1468
0x1469
0x146A
0x146B
0x146C
0x146D
0x146E
0x146F
Speech Control 0
Specific Register
Speech IO Direction
Speech IO Input Data
Speech IO Output Data
Speech IO Mask
Fsync counter
Multiplexer control register
FTInGain3
FTOutGain3
FTInGain2
FTOutGain2
FTInGain1
FTOutGain1
FTInGain0
FTOutGain0
Mode
Value At
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
- 28 -
Function
Configuration Register for PCM interface
Blocked for test modes
Speech I/O interface direction control
Speech I/O port input data
Speech I/O port Output data
Speech I/O port control register for mask
Frame sync counter within the speech interface
Multiplexer to connect 5 PCM channels to 4 DSP channels
Fine tune gain input stage
Fine tune gain output stage
Fine tune gain input stage
Fine tune gain output stage
Fine tune gain input stage
Fine tune gain output stage
Fine tune gain input stage
Fine tune gain output stage
Publication Release Date: May, 2007
Revision 1.3
W681307
7.3.5
Processor Interface Registers Overview
Mode
Value At
Reset
AuxOpPort
Reserved
R/W
0x00
Chip selects or output ports
Diag_CS
Diag_CS3
Mutiplier_enable
R/W
R/W
R/W
0x00
0x00
0x00
Chip selects or output ports
Chip selects or output ports
Address
Name
0x1470
0x1471
0x1472
0x1473
0x1474
0x14750x147F
7.3.6
Function
Fast 8x8 multiplier in T8032
Reserved
Transcoder DSP Registers Overview
Mode
Value At
Reset
Connect0
R/W
0x00
Specify mixing among four PCM channels
Specified Register
R/W
0x00
Blocked for test modes
PCMmode0
InputGain0
OutputGain0
RESERVED
ToneFreqA0
ToneFreqB0
ToneVolA0
ToneVolB0
ToneEna0
SideTone
Lookback_EN
Specified Register
R/W
R/W
R/W
0x00
0x00
0x00
Select between 14-bit linear, A-law and µ-law mode
PCM input gain
PCM output gain
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Set frequency of tone A
Set frequency of tone B
Set level of tone A
Set level of tone B
Enable addition of tones
Set sidetone gain
Test facilities for Transcoder DSP
Blocked for test modes
Connect1 ~ ToneEna1
R/W
0x00
The functions are the same as channel 0
R/W
0x00
The functions are the same as channel 0
SideToneChannel_Ena
R/W
0x01
Side tone enables for each active PCM channel
Connect3 ~ ToneEna3
R/W
0x00
The functions are the same as channel 0
Address
Name
0x1480
0x14810x1483
0x1484
0x1485
0x1486
0x1487
0x1488
0x1489
0x148A
0x148B
0x148C
0x148D
0x148E
0x148F
0x14900x149C
0x149D–
0x149F
0x14A00x14AC
0x14AD–
0x14AE
0x14AF
0x14B00x14BC
0x14BD–
0x14BF
Function
RESERVED
Connect2 ~ ToneEna2
RESERVED
RESERVED
- 29 -
Publication Release Date: May, 2007
Revision 1.3
W681307
7.3.7
Echo Canceller Registers Overview
Address
Name
Mode
0x14C0
UP_CONFIG
R/W
Value At
Reset
0x00
0x14C1
UP_RESET
R/W
0x08
0x14C2
0x14C3
EC_BELTA
Specific Register
R/W
R/W
0x03
0x03
0x14C4
LS_BUILD_UP_TIME
R/W
0x07
LS_MAX_ATTEN
R/W
0x1CA8
LS_MIN_ATTEN
R/W
0xFFFF
R/W
0x09
Attack time for long term acoustic power estimation
R/W
0x0B
Attack time for short term acoustic power estimation
R/W
0x0020
Define the inertial delay of the double talk detection
algorithm for acoustic side
R/W
0x0666
Define the instantaneous acoustic power change
R/W
0x0404
Define the power threshold
R/W
0x09
Attack time for long term network power estimation
R/W
0x0B
Attack time for short term network power estimation
R/W
0x0009
Define the inertial delay of the voice detection algorithm for
the network side
R/W
0x0666
Define the instantaneous network power change
0x14C50x14C6
0x14C70x14C8
Function
Configuration for the echo cancellation unit
Enables the three buffers used by the echo cancellation FIR
filter
The echo cancellation update gain
Blocked for test modes
Controls acoustic suppression factor convergence towards
target
Maximum attenuation value that will be utilised by the
acoustic suppression algorithm
Minimum attenuation value that will be utilised by the
acoustic suppression algorithm
0x14D30x14D4
0x14D50x14D6
DT_LONG_ACOUSTIC_ATTA
CK_TC
DT_SHORT_ACOUSTIC_ATT
ACK_TC
DT_ACOUSTIC_HANGOVER_
TIME
DT_ACOUSTIC_DEV_THRES
HOLD
DT_SHORT_ACOUSTIC_THR
ESHOLD
VD_LONG_NETWORK_ATTA
CK_TC
VD_SHORT_NETWORK_ATT
ACK_TC
VD_NETWORK_HANGOVER
_TIME
VD_NETWORK_DEV_THRES
HOLD
0x14D70x14D8
VD_LONG_NETWORK_THRE
SHOLD
R/W
0x0666
0x14D90x14DA
VD_SHORT_NETWORK_THR
ESHOLD
R/W
0x040E
0x14DB0x14DC
0x14DD
VD_CUT_OFF_NETWORK_P
OWER
Specific Register
ACOUSTIC / NETWORK
Active Status
R/W
0x0666
R/W
0x00
Blocked for test modes
R
0x00
Acoustic side and Network side active status
AGC_THRESHOLD
R/W
0x0800
AGC_NOISE_THRESHOLD
R/W
0x00C8
0x14E3
AGC_MAX_SG
R/W
0x02
The AGC module has maximum gain to amplifier the echo
cancelled input signal
0x14E4
Specific Register
R/W
0x0F
Blocked for test modes
0x14E5
AGC_LG_ATTACK_TC
R/W
0x0B
0x14E6
0x14E7
0x14E8
0x14E9
0x14EA
AGC_ST_ATTACK_TC
NS_STTACK_Tcand_GAIN
NS_ATTEN_DW_UP_TC
NS_Active_Power_MSB
NS_Active_Power_LSB
R/W
R/W
R/W
R/W
R/W
0x09
0x00
0x00
0x00
0x00
0x14C9
0x14CA
0x14CB0x14CC
0x14CD0x14CE
0x14CF0x14D0
0x14D1
0x14D2
0x14DE
0x14DF0x14E0
0x14E10x14E2
- 30 -
Minimum power level that constitutes speech over the
network interface, as measured by the long term power
estimation algorithm
Minimum power level that constitutes speech over the
network interface, as measured by the short term power
estimation algorithm
Configurable bias for network power estimation
The AGC threshold is set the maximum output power from
AGC module
The calculated input power is compared with the
AGC_NOISE_THRESHOLD
The field defines the inertial delay utilized for the long term
gain estimation
Attack time for short term AGC power estimation
Set Noise_Suppressor_Index and ShortTermPowerTC
Set Noise_rise_TC and Noise_fall_TC
Set noise threshold
Set noise threshold
Publication Release Date: May, 2007
Revision 1.3
W681307
7.3.8
Soft Clip Registers Overview
Mode
Value At
Reset
Soft Clip Control
VD Soft Clip Normal Index
VD Soft Clip Low Index
R/W
R/W
R/W
0x00
0x00
0x00
VD SC Threshold
R/W
0x0400
Address
Name
0x14EB
0x14EC
0x14ED
0x14EE
0x14EF
0x14F0
0x14F1
0x14F2
0x14F3
0x14F4
0x14F5
0x14F6
0x14F7
7.3.9
ShortTermPreNetworkPowerA
ttackTC
VDSC Attack TC
DT Soft Clip Normal Index
DT Soft Clip Low Index
R/W
0x07
R/W
R/W
R/W
0x07
0x00
0x00
DT SC Threshold
R/W
0x0400
R/W
0x07
R/W
0x07
ShortTermPostAcousticPower
AttackTC
DTSC Attack TC
Mode
Value At
Reset
CODEC_OnOff_Scheme
R/W
0x00
0x1501
CODEC Digital Part
R/W
0x80
0x1502
CODEC ADC ABF PROB
R/W
0xFF
Mode
Value At
Reset
R/W
0x00
Name
0x1500
Name
0x1503
Sounder path
Time constant use to calculate the short term network
power for VD soft clip
Smooth the gain change
Control the gain of DT soft clip module at normal mode
Control the gain of DT soft-clip module at low mode
Determine the selection of Soft Clip gain
Time constant use to calculate the short term acoustic
power for DT soft clip
Smoothing function, smooth the gain change
Function
Hardware scheme to arrange the procedure and timing for
CODEC_digital_disable and CODEC_analog_disable
Reset CODEC FIFO value or reset CODEC FIFO point
Adaptive bit flip probability of the ADC path in the CODEC
modulator
Function
Sounder signal select PDM or PWMnd reference clock
generation for external melody chip
Frequency Adjustment of Crystal Oscillator
Address
Name
Mode
Value At
Reset
0x1504
FACO
R/W
0x00
Mode
Value At
Reset
R/W
0x00
7.3.12
Determine the selection of Soft Clip gain
Sounder Path Select
Address
7.3.11
Enable the soft clipping function
Control the gain of VD soft clip module at normal mode
Control the gain of VD soft clip module at low mode
CODEC Digital Part
Address
7.3.10
Function
Function
Select the on-chip capacitance connected to XTAL1 and
XTAL2 respectively
Specific Register
Address
Name
0x1505
Specific Register
- 31 -
Function
Blocked for test modes
Publication Release Date: May, 2007
Revision 1.3
W681307
7.3.13
VAG Selection
Address
Name
0x1506
VAG Selection
7.3.14
Mode
Value At
Reset
R/W
0x00
Mode
Value At
Reset
TG1 Gain Register
R/W
0x00
0x1508
PO Gain Register
R/W
0x00
0x1509
CODEC_CTRL
R/W
0x00
Mode
Value At
Reset
R/W
R/W
0x00
0x00
Name
0x1507
Name
0x150A
0x150B
Specific Register
Specific Register
Set TG1 gain from 0dB, 6dB, 12dB, 18dB to 24dB or bypass
and doublt you selected gain. TG2 internal gain.
Set PO gain from -4dB, 2dB, 8dB or bypass
OP amp PO power down, CODEC analog loopback, CODEC
transmitter gain
Function
Blocked for test modes
Blocked for test modes
Test Cases and Debugging Registers Overview
Mode
Value At
Reset
RECEIVE_DIAG
Specific Register
EnAllClock
CODEC_Test_Sel
RSSI Mode
BGP_LPF_EN
CODEC Status Indicator
Bandgap Voltage Adjustment
Specific Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x1515
Linear Regulator Voltage
Controller Register
R/W
0x00
0x15160x1517
Reserved
Mode
Value At
Reset
R
0x00
Address
Name
0x150C
0x150D
0x150E
0x150F
0x1510
0x1511
0x1512
0x1513
0x1514
7.3.17
Function
Specific Registers
Address
7.3.16
Select the reference voltage at pin VAG.
CODEC Control Register Overview
Address
7.3.15
Function
Function
Register for diagnostic and output pins switch
Blocked for test modes
Enable all of test clock
Digital CODEC part test mode selection
Use for ISP mode protect
Enable the low pass filter at the BGP generator
CODEC DAC ADC FIFO point indicator
Bandgap Voltage Adjustment
Blocked for test modes
The adjustment possibilities of output voltage of the linear
regulator have been built in to compensate the bandgap
variation in process.
Charge Park Detection
Address
Name
0x1518
Core PWR_Det
- 32 -
Function
Monitor core power voltage
Publication Release Date: May, 2007
Revision 1.3
W681307
7.3.18
DA High Pass Filter Selection
Address
Name
0x151A
DA High Pass Filter Selection
Mode
Value At
Reset
R/W
0x00
- 33 -
Function
Codec D/A high pass filter control register
Publication Release Date: May, 2007
Revision 1.3
W681307
7.3.19
TI PATH Selection
Address
Name
0x1521
TI Path Selection
Mode
Value At
Reset
R/W
0x00
Function
Choose the signal to be processed in off-hook or on-hook
signalling
(0x1520 ~ 0x157F are bloked for test modes except for 0x1521)
7.3.20
Network side / Acoustic side Power Measurement
Address
Name
0x15C0~
0x15C1
0x15C2~
0x15C3
0x15C4~
0x15C5
ACOUSTIC_SHORT_TERM_
POWER
ACOUSTIC_LONG_TERM_
POWER
ACOUSTIC_POWER_DEVI
ATION
ACOUSTIC / NETWORK
Active Status
Reserved
NETWORK_SHORT_TERM_
POWER
NETWORK_LONG_TERM_
POWER
NETWORK_POWER_DEVI
ATION
ACOUSTIC / NETWORK
Active Status
0x15C6
0x15C7
0x15C8~
0x15C9
0x15CA~
0x15CB
0x15CC~
0x15CD
0x15CE
Mode
Value At
Reset
R
0x0000
R
0x0000
R
0x0000
R
0x00
R
0x0000
R
0x0000
R
0x0000
R
0x00
- 34 -
Function
Short Term Acoustic Power calculated by the double talk
detector (DT)
Long Term Power on Acoustic estimated by the double talk
detector (DT)
Acoustic Power Deviation estimated by the double talk
detector (DT)
Acoustic and Network active status
Short Term Network Power calculated by the voice detector
(VD)
Long Term Power on Network estimated by the voice
detector (VD)
Network Power Deviation estimated by the voice detector
(VD)
Acoustic and Network active status
Publication Release Date: May, 2007
Revision 1.3
W681307
7.3.21
PCM Highway Channel Registers Overview
Mode
Value At
Reset
PCM channel format and delay
control of 1st group
R/W
0x02
0x1701
TX delay1
R/W
0x00
0x1702
TX delay2
R/W
0x00
0x1703
RX delay1
R/W
0x00
0x1704
RX delay2
R/W
0x00
0x1705~
0x1707
Reserved
0x1708
PCM channel format and delay
control of 2nd group
R/W
0x02
0x1709
TX delay3
R/W
0x00
0x170A
TX delay4
R/W
0x00
0x170B
RX delay3
R/W
0x00
0x170C
RX delay4
R/W
0x00
0x170D~
0x170F
Reserved
0x1710
PCM channel format control of
2nd PCM highway
R/W
0x02
Address
Name
0x1700
7.3.22
Function
PCM channel format and delay control of 1st group in the 1st
PCM Highway
Set the values for delaying the transmitted bits of PCM
channel1 after the rising edge of the Fsync.
Set the values for delaying the transmitted bits of PCM
channel2 after the tail bit of PCM channel 1.
Set the values for delaying the received bits of PCM
channel1 after the rising edge of the Fsync.
Set the values for delaying the received bits of PCM
channel2 after the tail bit of RX PCM channel 1.
PCM channel format and delay control of 2nd group in the
1st PCM Highway
Set the values for delaying the transmitted bits of PCM
channel3 after the tail bit of PCM channel 2.
Set the values for delaying the transmitted bits of PCM
channel4 after the tail bit of PCM channel 3.
Set the values for delaying the received bits of PCM
channel3 after the tail bit of RX PCM channel 2.
Set the values for delaying the received bits of PCM
channel4 after the tail bit of RX PCM channel 3.
PCM channel format control of the 2nd PCM highway.
SPI Interface Registers Overview
Mode
Value At
Reset
Address
Name
0x1720
SPI_control0
R/W
0x00
Setting SPI interface control register.
0x1721
SPI_control1
R/W
0x00
Setting SPI interface control register.
0x1722
SPI Status
R
0x00
Read the SPI Status.
0x1723
SPI Interrupt Enable
R/W
0x00
Enable SPI interrupt.
0x1724
DumpByte
R
0x00
Show the received byte when 1720[3] is set.
0x1725
Write TX FIFO
W
0x00
0x1726
Read RX FIFO
R
0x00
0x1727
SPI_transfer_size
R/W
0x00
Setting the transfer size when Tx and Rx.
0x1728
SPI_start_rtx
R/W
0x00
Start to transmit at the rate of transfer size when Tx and Rx.
- 35 -
Function
Store data in SPI TX-FIFO when micro controller writes data
to this register.
Read data from SPI RX-FIFO when micro controller read data
from this register.
Publication Release Date: May, 2007
Revision 1.3
W681307
7.3.23
Data Flash SPI Interface Registers Overview
Name
0x1730
DF_CLK
R/W
0x00
Setting data flash SPI interface enable and clock rate.
0x1731
DF_CMD_LEN
R/W
0x00
Setting data flash SPI interface command length control
register.
0x1732
DF_DATA_LEN
RW
0x00
Setting data flash SPI interface data length control register.
0x1733
DF_INTR_REG
R/W
0x00
Enable data flash SPI interrupt.
0x1734 ~
0x1738
DF_CMD_B1 ~
DF_CMD B5
RW
0x00
Setting data flash SPI interface command contact register.
0x173B
DF_CLK_FORMAT
RW
0x00
Setting the data flash SPI interface format.
0x173C
DF_FIFO_DATA
RW
0x00
Read/write the data from the data flash SPI interface FIFO.
0x173D
DF_CNT
R
0x00
Current the data flash SPI interface FIFO counter value.
0x173E
DF_WR_CNT
R/W
0x00
CPU current Write-point for the data flash SPI interface FIFO.
0x173F
DF_RD_CNT
R/W
00
CPU current Read-point for the data flash SPI interface FIFO.
7.3.24
Mode
Value At
Reset
Address
Function
W2S Interface Registers Overview
Mode
Value At
Reset
Address
Name
0x1740
W2S_Enable
R/W
0x00
Enable W2S interface.
0x1741
EEPROM_Config
R/W
0x00
Setting the page mode of EEPROM.
0x1742
Prescale_Lo
R/W
0x00
Control W2S bus speed.
0x1743
Prescale_Hi
R/W
0x00
Control W2S bus speed.
0x1744
RdWrFIFO
R/W
0x00
Read /Write data into TX FIFO.
0x1745
Force_Activity
R/W
0x00
Force activities of W2S.
0x1746
W2S_Status
R
0x00
Read W2S status.
0x1747
FIFORdPtr
R
0x00
Monitor W2S FIFO read pointer.
0x1748
FIFOWrPtr
R
0x00
Monitor W2S FIFO write pointer.
0x1749
ForceAckFail
R/W
0x00
Enable Ack Fail Event.
0x174A
W2S_Misc
R
0x00
Monitor current finite state and interrupt indication.
- 36 -
Function
Publication Release Date: May, 2007
Revision 1.3
W681307
7.3.25
Address
0x1800
0x1801~
0x1803
0x1804 ~
0x1806
0x1810
USB Control Registers Overview
Mode
Value At
Reset
R/W
00
USB 1.1 function enables control register.
R/W
00
USB endpoints interrupt enable, status and clear.
R/W
00
USB endpoints interrupt enable, status and clear.
R/W
00
Control in/out Endpoint control register.
R/W
00
Control in Endpont Data. Internal FIFO has 8 bytes for Control
In transmission.
R
00
Control HID out receiving data.
R
00
Control Out Endpoint receiving data.
R/W
00
ISO In/Out Endpoint control register.
R/W
xx
ISO SYNC fine-tuning speed parameter register.
R/W
00
Bulk In Endpoint control register
W
00
Bulk_In transmission data register except final data.
W
00
Bulk_In transmission final data register.
R
00
Bulk_In transmission FIFO data empty flag.
R/W
00
Bulk Out Endpoint control register
R
00
Shown Bulk Out Endpoint receiving FIFO data length.
R
00
Bulk Out Endpoint receiving FIFO data.
R/W
00
Interrupt In Endpoint control register
R/W
00
Interrupt In Endpoint transmission data length
R/W
00
Total 16 bytes Interrupt In transmission data registers.
Specific Register
R/W
00
Blocked for test modes
Specific Register
R/W
00
Blocked for test modes
Name
USB Enable Register
USB Interrupt Register A.
Enable, status and clear
USB Interrupt Register B.
Enable, status and clear
EndPoint 0 – Control
In/Out Registers
Control In Data
0x1811
0x1820 ~
0x1827
0x1828 ~
0x182F
0x1830
0x1839 ~
0x1847
0x1848
0x1849
0x184A
0x184B
0x1850
0x1851
0x1852
0x1858
0x1859
0x1860~0x
186F
0x18700x1874
0x1875
Control HID Out Data
Control Out Data
EndPoint 1 and 2 – ISO
In/Out Registers
ISO SYNC Speed Register
EndPoint 3 – Bulk In
Registers-- Control
Register
Bulk In Data
Bulk In Final Data
Bulk In FIFO Empty Flag
EndPoint 4 – Bulk Out
Registers--- Control
Register
Bulk Out FIFO Length
Bulk Out Data
EndPoint 5 – Interrupt In
Registers--- Control
Register
USB Interrupt Data
Length
Interrupt In Data
- 37 -
Function
Publication Release Date: May, 2007
Revision 1.3
W681307
7.3.26
ISP Mode
Mode
Value At
Reset
ISP control register
R/W
00
ISP mode control and enable register
Specific Register
R/W
00
Blocked for test modes
Address
Name
0x1900
0x1901
- 38 -
Function
Publication Release Date: May, 2007
Revision 1.3
W681307
8.
SUPPORT LOGIC
：
The Support Logic provides the following functionality
•
•
•
System reset and Clock Control
Interrupt Processing / Control
Ringer Tone Generation
：
Figure 8-1 illustrates the functionality of the MCU Chip Support Logic
SysClock
ResetN
SysClock2En
SysClock3En
SysClock4En
SysReset
Reset32K
Reset &
Clock Control
KeyIntrpt
TimerIntrpt
SpeechIntrpt
IntrptSource
IntrptEnable
IntrptPriority
SysClock1
SysClock2
SysClock3
SysClock4
INT0
Interrupt
Control
INT1
SysClock4
SysReset
SounderTone1
SounderTone2
SounderVol1
SounderVol2
Reset &
Clock Control
SNDR
Figure 8-1 Illustration of the MCU Chip Support Logic
- 39 -
Publication Release Date: May, 2007
Revision 1.3
W681307
8.1
Clock Control & Reset 32K
8.1.1
Overview
、
Each register in the Speech Processor Support and Interface Logic is reset synchronously. The Reset & Clock Control function
ensures that the system reset signal is correctly generated. The system reset signal is also used to ensure that bi-directional signals are all
set to input during initialization. A separate reset signal is provided for registers operating at 32KHz.
The MCU chip has five internal 13.824MHz clocks. The clocks are gated to conserve power. Four clocks are of the same phase
and should be balanced during layout to allow data to be handled between the clock domains without additional logic. The clock to the
8032Turbo is of the opposite phase to the other four 13.824MHz clocks. The 32KHz clock is not gated or controlled on-chip.
8.1.2
Functionality
The System Reset signal SysReset is used to synchronously reset all the latches, which run from the 13.824MHz system clock:
Two asynchronous latches sample the reset input. These are clocked to the non-reset state when the system clock is running and
are used to ensure that the device is reset if the system clock is not running when the reset input is released.
•
All gated clocks are enabled and the SysReset signal is asserted for 4 system clock cycles after the end of the external reset
signal is detected by the asynchronous latches.
•
SysReset is asserted from the time the asynchronous latches are reset until the end of the reset sequence to ensure bi-directional
signals are forced to safe values during initialization.
A separate latch, controlled by a processor register bit Reset32k holds all 32768Hz logic in reset until set by the processor.
•
The 8032T is reset by SysReset.
•
•
•
•
•
•
Clock gating is performed with an OR function such that the clock signal is held high when disabled.
The Support and Interface Logic use 6 clocks: SysClock: Non-gated 13.824MHz clock.
SysClock1: Clock to the 8032Turbo.This clock is inverted relative to the other four SysClocks. Enabled for (clocks_unstable=0).
SysClock2: Clock to the Processor-Writeable registers. Controlled by the Processor Interface.
SysClock3: Clock to the Speech Interface Logic (which is not needed by the CODEC). Controlled by Processor-writeable
register.
SysClock4: Clock to the Ringer Tone Generator. Controlled by Processor-writeable register.
SysClock5:Clock to the Winbond Linear CODEC (and logic in the Speech Interface needed to support operation of the CODEC)
Care will be required in the physical design of the Support Logic to ensure balancing of all clocks.
All outputs from logic in the 32768Hz clock domain are re-timed on entering the 13.824MHz clock domain. This is done using serial
pairs of latches to give metastability protection.
Signals in Interface Logic are re-timed: •
KeyPress interrupt
•
WatchDog interrupt
•
WatchDog kick
•
1 millisecond timer interrupt
•
1 second timer interrupt
8.1.3
Clock Enable Register
Address
Access Mode
Value At Reset
0x1440
R/W
0xFD
Bit 7
Reset32K
Sysclock3En
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Blocked (for test modes)
Bit 2
Bit 1
Bit 0
SysClock5En
SysClock4En
SysClock3En
When set, enable system clock 3.
- 40 -
Publication Release Date: May, 2007
Revision 1.3
W681307
Sysclock4En
Sysclock5En
Reset32K
8.2
When set, enable system clock 4.
When set, enable system clock 5.
set low to reset the 32KHz clock source.
Interrupt Control
8.2.1
Overview
The Support and Interface Logic generate internal events, these interrupt events are conditioned by the Interrupt Control logic before it is
issued to the Processor. Figure 8-2 shows the interrupt structure.
8.2.2
Functionality
The Support and Interface Logic generate interrupt events as one-cycle pulses. The Support and Interface Logic generate the following
interrupts:
•
•
•
•
•
Hardware Keypad Scanner Interrupt
Keypad port input general purpose IO Interrupt
Timer Interrupt
Speech Interface Interrupt
WatchDog Interrupt
The Speech Interface generates the following interrupts: •
PCM Port Input General Purpose IO Interrupt
Three registers control the generation of interrupts in the MCU chip, the IntrptSource register, the IntrptEnable register and the
IntrptPriority register. Each interrupt has a corresponding bit in the IntrptSource, IntrptEnable and IntrptPriority registers.
•
•
•
•
•
The IntrptSource register is set when an interrupt event occurs and is cleared by Processor write.
When the Processor writes to IntrptSource, any bits that are set to 1 cause the corresponding bit of IntrptSource to be cleared,
bits set to 0 are not affected.
An Interrupt is generated when IntrptSource AND IntrptEnable =1 for any of the interrupt sources.
For each bit; if IntrptPriority =0, the interrupt is issued to INT0, if IntrptPriority =1, the interrupt is issued to INT1.
The watchdog interrupt is implemented for debug purposes only. The Watchdog must be kicked before attempting to clear its
associated source register.
- 41 -
Publication Release Date: May, 2007
Revision 1.3
W681307
Interrupt Registers
Interrupt
Source
&
&
INT0
&
INT1
Interrupt
Enable
Interrupt
Priority
Figure 8-2 Interrupt Structure
- 42 -
Publication Release Date: May, 2007
Revision 1.3
W681307
8.2.3
Address
Interrupt Registers
Name
Description
IntrptSource0
Interrupt source register 0
Read:
1 = Interrupt
0 = No Interrupt
Write:
1 = Clear
1442H
IntrptSource1
Interrupt source register 1
Read:
1 = Interrupt
0 = No Interrupt
Write:
1 = Clear
1443H
IntrptEnable0
Interrupt enable register 0
1 = Enabled
0 = Disabled
1444H
IntrptEnable1
Interrupt enable register 1
1 = Enabled
0 = Disabled
1445H
IntrptPriority0
Interrupt priority register 0
0 = INT0
1 = INT1
1446H
IntrptPriority1
Interrupt priority register 1
0 = INT0
1 = INT1
1441H
Bit
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
- 43 -
Description
Blocked(for test modes)
Blocked(for test modes)
Blocked(for test modes)
Blocked(for test modes)
Blocked(for test modes)
Timer1sIntrpt
Timer1msIntrpt
KeyPressIntrpt
SpeechIOIntrpt
WatchdogIntrpt
KeyIOIntrpt
Blocked(for test modes)
Blocked(for test modes)
Blocked(for test modes)
Blocked(for test modes)
Blocked(for test modes)
Blocked(for test modes)
Blocked(for test modes)
Blocked(for test modes)
Blocked(for test modes)
Blocked(for test modes)
Timer1sIntrpt
Timer1msIntrpt
KeyPressIntrpt
SpeechIOIntrpt
WatchdogIntrpt
KeyIOIntrpt
Blocked(for test modes)
Blocked(for test modes)
Blocked(for test modes)
Blocked(for test modes)
Blocked(for test modes)
Blocked(for test modes)
Blocked(for test modes)
Blocked(for test modes)
Blocked(for test modes)
Blocked(for test modes)
Timer1sIntrpt
Timer1msIntrpt
KeyPressIntrpt
SpeechIOIntrpt
WatchdogIntrpt
KeyIOIntrpt
Blocked(for test modes)
Blocked(for test modes)
Blocked(for test modes)
Blocked(for test modes)
Blocked(for test modes)
Value At
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Publication Release Date: May, 2007
Revision 1.3
W681307
8.2.4
Extends of interrupt
144DH
IntrptSource2
Interrupt source register 2
1 = Interrupt
0 = Cleared
144EH
IntrptEnable2
Interrupt enable register 2
1 = Enable
0 = Disable
144FH
IntrptPriority2
Interrupt priority register 2
0 = INT0
1 = INT1
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
- 44 -
Blocked(for test modes)
Reserved
SPIIntrpt
W2SIntrpt
Blocked(for test modes)
CPWRIntrpt
Reserved
USBIntrpt
Blocked(for test modes)
Reserved
SPIIntrpt
W2SIntrpt
Blocked(for test modes)
CPWRIntrpt
Reserved
USBIntrpt
Blocked(for test modes)
Reserved
SPIIntrpt
W2SIntrpt
Blocked(for test modes)
CPWRIntrpt
Reserved
USBIntrpt
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Publication Release Date: May, 2007
Revision 1.3
W681307
8.3
Ringer Tone Generator
8.3.1
Overview
The buzzer signal generates tones to signal an incoming call.
There are two buzzer signal can be selected to connect to SNDR pin. This subsection describes the Ringer Tone Generator with the PWM
(Pulse Width Modulation) format. The other buzzer signal of PDM (Pulse Density Modulation) format will be described on 1503[1:0].
8.3.2
Functionality
SounderTone1
Sysclk
/16
864KHz
/N
SounderVol1
3388Hz to 864KHz
/32
Decoder
105Hz to 27KHz
Sounder
Sysclk
/16
864KHz
/N
3388Hz to 864KHz
/32
SounderTone2
Decoder
105Hz to 27KHz
SounderVol2
Figure 8-3 The Ringer Tone Generator
The Ringer Tone Generator has two controllable tone sources, shown in Figure 8-3. This each gives a programmable output frequency of
between 105Hz and 27KHz. Each tone source has a programmable mark-to-space ratio. By controlling the mark to space ratio the volume
of the sounder can be controlled.
•
•
•
•
•
•
•
•
The ÷16 function produces a 864kHz pulse from the 13.824MHz system clock.
The ÷n function produces a 3388 to 864kHz pulse from its 864kHz input. The output frequency of this function and the
corresponding output frequency of the chip is determined by the SounderTone register.
The ÷ 32 function contains a counter, clocked by the system clock, which increments on each pulse at it input. The Decoder
uses the 4-bit output from this counter to produce a 105Hz to 27kHz with a programmable Mark-Space ratio defined by the
SounderVol register.
The tone source always starts in the same way (for a given set of programmed values)
The tone source stops cleanly, that is it stops in the inactive state (logic 0) without truncation of any ongoing high pulse.
The results of tone source one and tone source two are logically OR together to produce the output signal Sounder”.
Both tone generators have a common enable signal to allow them to be synchronized together.
- 45 -
Publication Release Date: May, 2007
Revision 1.3
W681307
8.3.3
Sounder Tone Register Definition
The registers SounderTone1 and SounderTone2 set the output frequency of the corresponding tone generator.
Each 8-bit register has a range of 1 to 255 (decimal) corresponding to an output frequency range of 105Hz to 27KHz, with a 10%
tolerance.
8.3.4
Sounder Volume Register Definition
The registers SounderVol1 and SounderVol2 set the mark to space register of the corresponding tone generator.
Bit 4
0
0
0
0
0
0
0
0
Bit 3
0
0
0
0
0
0
0
0
1
1
1
1
8.3.5
Table 8-1: SounderVol1 and SounderVol2 pulse generation ratio.
Bit 2
Bit 1
Bit 0
Mark
Space
0
0
0
No output (permanent low)
0
0
1
1
31
0
1
0
2
30
0
1
1
3
29
1
0
0
4
28
1
0
1
5
27
1
1
0
6
26
1
1
1
7
25
…………
1
1
0
30
2
1
1
1
31
1
Example of use
In order to generate a 794Hz frequency output from tone source one with a mark to space ratio of 1:1. Program the SounderTone1 register
with 00100010 (÷ n = 35) and program the SounderVol1 register with 10000.
To give a 1350Hz frequency output from tone source one with a mark to space ratio of 7:25. Program the SounderTone1 register with
00010100 (÷ n = 21) and program the SounderVol1 register with 00111.
- 46 -
Publication Release Date: May, 2007
Revision 1.3
W681307
8.3.6
Address
Sounder Registers
Name
Description
Bit
1447H
SounderTone1
Sounder frequency control
1448H
SounderTone2
Sounder frequency control
1449H
SounderVol1
Sounder volume control
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
144AH
SounderVol2
0
1
2
3
4
5
6
Sounder volume control
7
0
1
144BH
PIEZO Function
Enable PIEZO function
Select PIEZO frequency
144CH
PIEZO Clock output
Output twice clock count of this
register value
- 47 -
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Description
Sounder frequency control
Sounder frequency control
Sounder volume control
Reserved
Reserved
Tone generators
enable = 1
Value
at Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Sounder volume control
Reserved
Reserved
Tone generators
enable = 1
Enable
Frequency Select
0: 216KHz, 1: 108KHz
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PIEZO driving signal from
PCM0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Publication Release Date: May, 2007
Revision 1.3
W681307
8.4
8.4.1
PIEZO Tone Generator
Overview
The PIEZO signal can generated by the Ringer Tone generator, this subsection describe the PIEZO-driving clock from the Ringer tone
generator, shown in Figure 8-4.
8.4.2
Functionality
VCC
INDUCTOR
R
DIODE
PCM1/RT0
C
R
Piezo
R
SNDR
Figure 8-4 Piezo tone circuit
The PCM1/RTO pin generates the driving signal to obtain higher voltage. When set register 0x144B[0], will enable the functionality of
Piezo, 0x144B[1] select the frequency of 108KHz or 216KHz for driving signal. The register 0x144C[7:0] output the twice number of
clock for up conversion the voltage. The Soundertone and SounderVol register controls the melody of piezo.
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Publication Release Date: May, 2007
Revision 1.3
W681307
9.
INTERFACE LOGIC
：
The Interface logic consists of
•
•
•
A Keypad Scanner
Timers
Input/Output Ports
：
Figure 9-1 illustrates the operation of the Interface Logic
IntWriteData[7..0]
unstable_ck13m
IOReadData
32000Hz
/256
125Hz
Keypad
Scanner
State
Machine
IOReadValid
IntAddress [9..0]
KeyIntrpt
TimerIntrpt
IO Register
DogTimeout
KeyROx[5:0]
KeyCIx[5:0]
KeyRIx[5:0]
KeyCIx[4:0]
32KHz
/ 32
1ms
/1000
100Hz
KeyRO[6..0]
KeyRD [6..0]
KeyCO [6..0]
KeyCD [6..0]
Timer
Figure 9-1 The Interface Logic.
9.1
Keypad Scanner
9.1.1
Overview
The Keypad Scanner State Machine operates from the 32000Hz clock. The keypad scanner identifies which key has been pressed and
includes de-bouncing logic. Multiple concurrent key presses are not supported. Dividers provide 1Hz and 1ms timing signals. The 1 Hz
signal provides timing for keypad de-bouncing and the 1 Hz and 1ms signals are used for the Timer.
The KeySize register sets the size of the keypad, up to 9 of the unused signals can be used as IO Ports.
All active Row outputs are initially set high, each Column input has an external pull-down resistor. When a Key is pressed, the signal
from one Column will go high. The Keypad Scanner function operates as follows:
•
•
•
•
•
•
The State machine waits in a default state until a high is found at one of the Column inputs.
Each active Row output is set low in turn until a low is detected at the Column input. The Row and Column numbers are stored.
The State Machine waits for the de-bounce period set in the KeyBounce Register.
Each Row output is set low in turn until a low is detected at the Column input. The Row and Column numbers are stored.
The Row and Column numbers stored at 2 and 4 are compared. If these are the same, a valid keystroke has been detected.
The State Machine waits for unstable_ck13m to go low, asserts KeyIntrpt and returns to 1.
The KeyBounce register sets a de-bounce period of 8mS, 16mS, 24mS or 32mS (times are -0.0 mS +1.5 mS).
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Publication Release Date: May, 2007
Revision 1.3
W681307
9.1.2
Use of the Keypad Scanner
The software should set up the KeyPadSize register so that the keypad can be used. This register sets the keypad size and the de-bounce
period.
Once a key has been de-bounced a KeyIntrpt interrupt is generated and the key value is stored in the KeyLocation register. When the key
is released a further KeyIntrpt interrupt is generated. (Note that only two interrupts are generated in a key press release sequence and that
holding a key down for extended periods does not result in multiple interrupts.)
The KeyPress register bit in the KeyLocation states whether a key is pressed. When a key is pressed the bit is active once the key press
has been de-bounced and is removed once the key is released.
Where ports are being used with the hardware keypad scanner, the corresponding data bit in the Key IO port output data register must be
set to zero.
9.1.3
Use of a Software Keypad Scanner
If keypad scanning is done in software than the keypad scanner functionality is not used and the pins are treated as general purpose I/O
ports KeyC[3:0] and KeyR[4:0].
9.2
I/O Ports
Pins not used by the Keypad scanner are available as standard IO Ports, controlled by KeyIoDR, KeyIoDC, KeyIoIpR, KeyIoIpC,
KeyIoOpR and KeyIoOpC. An interrupt event will be generated if there is a change in the value of any one of KeyIoIp and the
corresponding bit of KeyIoMsk is set.
Note that the direction of KeyC[3:0] amd KeyR[4:0] are always controlled by the KeyIoDC[3:0], KeyIoDR[4:0] registers.
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Publication Release Date: May, 2007
Revision 1.3
W681307
9.3
Address
1450H
1451H
1452H
1453H
1454H
Keypad Control Registers
Name
KeyIoDR
Sysclock2
KeyIoDC
Sysclock2
KeyIoIpR
Sysclock2
KeyIoIpC
Sysclock2
KeyIoOpR
Sysclock2
Description
Key IO Port Direction
Control Register
0 = output
1 = input(Default)
Key IO Port
Direction Control
Register
0 = output
1 = input
Key IO Port Input
Data Register
Value =True
Key IO Port Input
Data Register
Value =True
Key IO Port Output
Data Register
Value =True
Bit
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Description
KeyIoDR[0]
KeyIoDR[1]
KeyIoDR[2]
KeyIoDR[3]
KeyIoDR[4]
Reserved
Blocked
(for test modes)
Reserved
KeyIoDC[0]
KeyIoDC[1]
KeyIoDC[2]
KeyIoDC[3]
Reserved
Reserved
Reserved
Reserved
KeyIoIR[0]
KeyIoIR[1]
KeyIoIR[2]
KeyIoIR[3]
KeyIoIR[4]
Reserved
Reserved
Reserved
KeyIoIC[0]
KeyIoIC[1]
KeyIoIC[2]
KeyIoIC[3]
Reserved
Reserved
Reserved
Reserved
KeyIoOR[0]
KeyIoOR[1]
KeyIoOR[2]
KeyIoOR[3]
KeyIoOR[4]
Reserved
Reserved
Reserved
- 51 -
Value at
Reset
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Physical
Mapping to
output ports
Row[0]
Row[1]
Row[2]
Row[3]
Row[4]
Col[0]
Col[1]
Col[2]
Col[3]
Row[0]
Row[1]
Row[2]
Row[3]
Row[4]
Col[0]
Col[1]
Col[2]
Col[3]
Row[0]
Row[1]
Row[2]
Row[3]
Row[4]
Publication Release Date: May, 2007
Revision 1.3
W681307
Address
1455H
1456H
Name
KeyIoOpC
Sysclock2
KeyIoMskR
Sysclock2
1457H
KeyIoMskC
Sysclock2
1458H
KeyPress
Location
Read Only
1459H
KeyPadSize
Description
0
1
2
Key IO Port Output
3
Data Register
4
Value =True
5
6
7
0
1
2
Key IO Port Control
3
Register For Mask
0= off=masked
4
1= on=unmasked
5
6
7
0
1
2
Key IO Port Control
Register For Mask
3
0=off=masked
4
1=on=unmasked
5
6
7
0
1
2
Gives the Row and
column
3
4
5
Shows
“1”
when 6
KeyPad is pressed
7
0
1
2
Sets the size of the
Keypad scanned by
3
the Keypad Scanner
4
function
5
6
7
Bit
Description
Value at
Reset
KeyIoOC[0]
KeyIoOC[1]
KeyIoOC[2]
KeyIoOC[3]
Reserved
Reserved
Reserved
Reserved
KeyIoM[0]
KeyIoM[1]
KeyIoM[2]
KeyIoM[3]
KeyIoM[4]
Reserved
Reserved
Reserved
KeyIoM[0]
KeyIoM[1]
KeyIoM[2]
KeyIoM[3]
Reserved
Reserved
Reserved
Reserved
KeyLocR[0]
KeyLocR[1]
KeyLocR[2]
KeyLocC[0]
KeyLocC[1]
KeyLocC[2]
KeyPressed
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
KeyRows[0]
KeyRows[1]
KeyRows[2]
KeyColumn[0]
KeyColumn[1]
KeyColumn[2]
KeyDb[0]
KeyDb[1]
0
0
0
0
0
0
0
0
0
Physical
Mapping to
output ports
Col[0]
Col[1]
Col[2]
Col[3]
Row[0]
Row[1]
Row[2]
Row[3]
Row[4]
Col[0]
Col[1]
Col[2]
Col[3]
The Timer1sReset bit and watchdog time bits cannot be altered once the watchdog is enabled.
The watchdog is reset every time the location WatchDogKick is written to.
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Publication Release Date: May, 2007
Revision 1.3
W681307
9.3.1
Key Location and Size Programming
Key Location and size registers, KeyLocR[*], KeyLocC[*], KeyRows[*] & KeyColumns[*] are defined as follows:-
Row/Column
Zero (see Note)
One
Two
Three
Four
Five
[2:0]
0x00
0x01
0x02
0x03
0x04
0x05
Note:
that zero is only valid for KeyRows[*] and KeyColumns[*], which means the keypad size=0 and all the keypad pins serve as GPIO. On
the other hand, the keyLocR[*] and keyLocR[*] are only checked when KeyPressed bit=1 (0x1458[7]) and meanwhile it should contain
non-zero value.
9.4
Timers
There are 3 timers: •
•
•
A programmable 1-millisecond timer
A 1 second timer
A programmable 1-second watchdog timer.
The programmable 1-millisecond timer can be enabled, reset and programmed to generate an pulse in the range 1 millisecond to 64
milliseconds (1 millisecond spacing).
The 1-second timer can be enabled, reset and always generates a pulse every 1 second.
The programmable 1 second watchdog timer can be enabled and programmed to generate a pulse in the range 1 second to 8 seconds (1
second spacing). Following reset the watchdog timer is disabled.
In normal operation the watchdog timer should be enabled by writing to the WatchDogEnable bit and the WatchDogResetEn bit. Once
written to these bits cannot be cleared except by a system reset, hence the watchdog cannot be disabled. Enabling the Watchdog timer also
prevents disabling of the 1-second timer.
The watchdog counts from the output of the 1-second timer. The expiry time is programmable and this value is set in the
WatchDogTime[0:2] register field. The software must clear the watchdog counter regularly. If the watchdog counter ever reaches the
expiry time, a reset and interrupt will occur.
Note: A write to the WatchDogKick location will not affect the 1-second timer from which the watchdog operates. Therefore if the
watchdog is set to 8 seconds, the timeout will occur between 7 to 8 seconds. The WatchDogKick location must be written to before 7
seconds, otherwise a reset and interrupt will occur. It is recommended that a setting of 1 second is not used.
In order to facilitate software debug the device has the Watchdog expiry generated reset disabled from reset. A watchdog interrupt is
provided to assist software debugging, this interrupt WatchDogIntrpt is generated by the watchdog timer if it expires. In this case the
WatchDogEnable bit would be set, but not the WatchDogResetEn bit.
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Publication Release Date: May, 2007
Revision 1.3
W681307
9.4.1
Watch Dog Control
Address
Access Mode
Value At Reset
0x145A
R/W
0x00
Bit 7
Bit 6
Bit 5
Reserved
WatchDog
ResetEn
WatchDogEn
WatchDogTimer [2:0]
WatchDogResetEn
Bit 4
Nominal Value
Bit 3
Watch Dog Timer [2:0]
Bit 2
Bit 1
WatchDogEn
Bit 0
KeyBounce[1:0]
When set, enable the watchdog, which use system clock source 2.
Controls the repetition rate of the watchdog timer 1 second to 8 seconds.
When set, it will reset whole baseband chip.
Key Debounce Period Selection.
KeyBounce[1:0]
The de-bounce period is defined as follows:
Key-Bounce Period
8 ms
16 ms
24 ms
32 ms
KeyBounce[1:0]
0x00
0x01
0x02
0x03
All times are +/- 0.5ms
9.4.2
Timer 1ms Control1
Address
Access Mode
Value At Reset
0x145B
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Timer1msLength[5:0]
Timer1msLength[5:0]
Timer1msEn
Bit 0
Timer1msEn
Timer1ms
Reset
1ms timer counter, which controls the repetition rate of the 1ms timer up to 64 ms.
When set to ‘1’, enable 1ms timer to proceed from it’s previous status. When reset to ‘0’, this just pause the
operation but not reset the content.
When reset to ‘0’, reset the 1ms timer. This timer will operate only when this bit remains ‘1’.
Timer1msReset
9.4.3
Bit 1
Timer Control
Address
Access Mode
Value At Reset
0x145C
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reset 1S
counter
Reserved
Reserved
Reset 1mS
counter
Reset 1S timer
1S timer reset
1mS counter reset
1S counter reset
when reset to “0”, reset the 1S timer.
when reset to “0”, reset the 1mS counter, but this bit does not affect the operation of 1ms timer which is
controlled by 0x145B.
when reset to “0”, reset the 1S counter value in 0x145D, but this bit does not affect the operation of 1S timer.
- 54 -
Publication Release Date: May, 2007
Revision 1.3
W681307
9.4.4
1S Counter
Address
Access Mode
Value At Reset
0x145D
R
0x00
Bit 7
Bit 6
Bit 5
Reserved
Reserved
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
1S Counter
1-second counter
This register records the time in 1 second resolution. Maximum value is 59.
9.4.5
Watch Dog Kick
Address
Access Mode
Value At Reset
0x145E
R/W
0x00
Bit 7
Bit 0
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
Bit 1
Bit 0
Watch Dog Kick
Write to this value will reset the watchdog timer.
9.4.6
1ms Counter
Address
Access Mode
Value At Reset
0x145F
R
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Counter value for 1mS timer
This register records the time in 1 ms resolution. Maximum value is 255.
Reset :145B[0]
enable: 145B[1]
Reset :145C[0]
1 ms
sysCl
k
1s
1ms Timer
counter for 1ms
interval INT
1s timer
1ms counter
0X145F
( 0~255 ms )
1min counter
= 1s counter
0x145D
( 0 ~ 59 sec )
Reset :145C[1]
Reset :145C[4]
1s INT
0X145B[7:2]
( 0~Timer1msLength[5:0])
comparetor
1ms INT
Note1: ALL THE RESET activities ARE LEVEL_TRIGGERED.
Note2: reset 145C[1] will not effect the waveform of 1ms INT.
- 55 -
Publication Release Date: May, 2007
Revision 1.3
W681307
10. SPEECH INTERFACE
10.1
Overview
The Speech Interface allows the MCU chip to be connected to one or more of the following:
•
•
•
External PCM CODEC and Echo Canceller.
IO Ports which can be used when the external Speech Expansion Interface is not required.
A test interface to and from the on-chip linear CODEC.
The Speech Interface Block also connects with the on-chip linear CODEC.
The Speech interface also contains three programmable outputs, which are used to control certain pins.
10.2
Functionality
Figure 10-1 shows the speech interface block diagram.
SPEECH PROCESSOR INTERFACE
]0
:3
1[
tu
o0
m
c
P
]0
:3
1[
ni
0
m
c
P
]0
:3
1[
tu
o1
m
c
P
]0
:3
1[
tu
o2
m
c
P
]0
:3
1[
ni
1
m
c
P
]0
:3
1[
ni
2
m
c
P
]0
:7
[t
nu
oc
_
m
cp
da
kc
ol
c_
m
cp
da
PcmI[0] (PcmIn0/PcmClockI)
PcmI[1]
(PcmIn1)
PcmO[1]
PcmD[1]
PcmI[2]
PcmO[2]
(PcmOut1)
PcmD[2]
PcmI[3]
PcmO[3]
PcmD[3]
PcmI[4]
PcmO[4]
PcmD[4]
PcmI[5]
PcmO[5]
PcmD[5]
PCM
Serial
Interface
SpeechIntrpt
SpeechCtrl1
IntWriteData[7..0]
SpeechIoD
SpReadData[7:0]
SpeechIoIp
(PcmOut0)
SpeechIoOp
SpeechIoMsk
SpeechCtrl0
(PcmClock)
Speech
Interface
Register
SpReadValid
IntAddress[9..0]
SysClock2
SysClock2
SysClock3
SysClock3
SysClock5
(PcmSyncO)
dr rw
D A
A D
lkc
vo
k2
f3e
r
k8
fe
r
]0
:3
1[
ni
A
F
D
]0
3:1
[
D
M
D
5k
co
l
C
sy
S
hp
SI
D
et
u
M
x
T
0]:
[3
L
R
T
C
D
A
R
ON CHIP CODEC INTERFACE
Figure 10-1 Speech Interface Block Diagram
- 56 -
Publication Release Date: May, 2007
Revision 1.3
W681307
10.3
PCM Serial Interface
：
The PCM Serial Interface
•
•
•
•
Formats parallel PCM data to/from the Speech Processor for use by external devices
PCM serial interface supports to convert serial pcm data of external devices to parallel pcm data of Speech Processor. PCM
highway supports 4 external devices by 4 slots pcm channels (B1 ~ B4). The internal USB ISO endpoint and the 4th slot of PCM
highway are shared with the same PCM channel (B4). When the USB_EN bit is set to high, the internal USB ISO endpoint will
be automatically connected to the PCM channel (B4). All channels supports 8/16 bits pcm format, and IOM2 mode.
PCM highway interface can support maste or slave modes with external devices.
Implements a 4-bit general purpose IO port when the PCM Serial Interface function is not required
Routing diagram as below Figure 10-2
：
Serial/Parallel
Figure 10-2 W681307 Speech Flow Block Diagram
10.3.1
Use with Additional External Lines
The PCM serial interface block can route channels 1, 2 and 3 from the Speech Processor to PCM highway which can be used to interface
to external CODECs to provide connection to two external lines.
For this mode PcmIf enable =1 and Slave Mode =0.
PCM Serial Interface can generate a Long frame sync (for LongSync =1) or a Short frame sync (for LongSync=0).
Timing diagrams for short frame sync and long frame sync modes are given in section 9.7.
10.3.2
I/O Ports
For PCMH1_Dis =1, the Speech Interface is reset and PCM highway (pins name: PCM_OUT, PCM_IN, PCM_FSC, PCM_CLK) operate
as standard IO ports, controlled by SpeechIoD, SpeechIoIp and SpeechIoOp registers. An interrupt event will be generated if there is a
change in the value of any one of SpeechIoIp and the corresponding bit of SpeechIoMsk is set.
For PCMH1_Dis=0, the direction of PCM highway is always controlled by the PCM highway function setting. In the PCM master mode,
the PCM_OUT, PCM_FSC and PCM_CLK pins areoutput, the PCM_IN pin is input. In the PCM slave mode, the PCM_OUT pin is
output, the PCM_IN, PCM_FSC and PCM_CLK pins are output.
- 57 -
Publication Release Date: May, 2007
Revision 1.3
W681307
10.3.3
Status of Speech Interface When Reset
When the device is reset then the speech interface I/O pins will all be set as inputs and the associated interrupts will be masked. Resetting
the device will cause the Speech Interface Pins (PCM[0:5] to be (general purpose) I/O ports.
10.4
Internal CODEC Control
The Speech Interface Block provides two control bits to the internal CODEC. The bits are used for TxMute and DisHPF. The signals are
output from the speech interface block and go to the internal CODEC. The values output by the speech interface on the two ports equates
to the value programmed in DisHPF and TxMute, the bits are reset to 0.
10.5
PCM Interface Registers
This section describes the Speech Interface Register.
10.5.1
Speech Control 0
Address
Access Mode
Value At Reset
0x1460
R/W
0x03
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Blocked
(for test modes)
Fsync
Advance
Fsync 16/8bit
Fsync
Long/Short
Blocked
(for test modes)
Slave Mode
Reserved
PCMH1_Dis
According to the configuration of PCMH1_Dis bit, the PCM highway function and GPIO function can be served at four PCM pins at the
same time. On the other hand, four PCM pins can just act for only pure PCM highway function or GPIO function.
B0: PCMH1_Dis
B2: Slave Mode
=1
PCM I/O ports are GPIO function.
=0
PCM I/O ports are serial-parallel converter function.
=1
Effective PCM highway function will operate at slave mode.
=0
Effective PCM highway function will operate at master mode.
B5: Fsync-16/8bit
B4:Fsync
Long/Short
x
0
Short Frame Sync signal is selected. The period of Fsync signal occupies 1 bit clock.
0
1
Long Frame Sync signal is selected. And the period of Fsync signal occupies 8 bits.
1
1
Long Frame Sync signal is selected. And the period of Fsync signal occupies 16 bits.
B6: Fsync advance
10.5.2
=1
The PCM_FSC signal is transmitted in advance of the PCM_CLK by one system clock.
=0
The PCM_FSC signal is transmitted at the rising edge of the PCM_CLK
Specific Register
Address
Access Mode
Value At Reset
0x1461
R/W
0x00
Nominal Value
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Publication Release Date: May, 2007
Revision 1.3
W681307
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
10.5.3
Bit 1
Bit 0
Blocked
Blocked
(for test modes) (for test modes)
Speech IO Direction
Address
Access Mode
Value At Reset
0x1462
R/W
0x0F
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
SpeechIoD[3]
SpeechIoD[2]
SpeechIoD[1]
SpeechIoD[0]
When set PCM interface as General I/O, this register set the I/O direction.
SpeechIoD[0]
=1:
PCM0 pin will be operated as input port.
SpeechIoD[1]
SpeechIoD[2]
SpeechIoD[3]
10.5.4
=0:
PCM0 pin operated as output mode.
=1:
PCM1 pin will be operated as input port.
=0:
PCM1 pin operated as output mode.
=1:
PCM2 pin will be operated as input port.
=0:
PCM2 pin operated as output mode.
=1:
PCM3 pin will be operated as input port.
=0:
PCM3 pin operated as output mode.
Speech IO Input Data
Address
Access Mode
Value At Reset
0x1463
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
SpeechIoI[3]
SpeechIoI[2]
SpeechIoI[1]
SpeechIoI[0]
SpeechIoI
10.5.5
When PCM interface is configured as input port, this register reflects the input data.
Speech IO Output Data
Address
Access Mode
Value At Reset
0x1464
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
SpeechIoO[3]
SpeechIoO[2]
SpeechIoO[1]
SpeechIoO[0]
SpeechIoO
When PCM interface is configured as output port, this register set to output data.
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Publication Release Date: May, 2007
Revision 1.3
W681307
10.5.6
Speech IO Mask
Address
Access Mode
Value At Reset
0x1465
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Reserved
Reserved
Reserved
Reserved
Bit 3
Bit 2
Bit 1
Bit 0
SpeechIOM[3] SpeechIOM[2] SpeechIOM[1] SpeechIOM[0]
When PCM interface configured as input port, this register mask the interrupt when PCM
interface input port is interrupted.
SpeechIOM[3:0]
10.5.7
Nominal Value
Fsync Counter
Address
Access Mode
Value At Reset
0x1466
R
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Reserved
Bit 3
Bit 2
Bit 1
Bit 0
Fsync-Counter
Fsync-Counter
10.6
Nominal Value
Provide the status of the frame sync counter within the speech interface.
The multiplexer to connect 5 PCM channels to 4 processor channels
10.6.1
Multiplexer control register
Address
Access Mode
Value At Reset
0x1467
R/W
0x11
Bit 7
Bit 6
Bit 5
Reserved
Reserved
Reserved
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
PCM channel4 PCM channel3 PCM channel2 PCM channel1 PCM channel0
The function of the multiplexer is to choose 4 channels among the 5 PCM channels to be effective which can be connected to 4 processor
channels by setting the multiplexer control register 0x1467. And the four processor channels labeled by from C0 to C3 will connect to the
effective PCM channels in numerical order of the channel label.The PCM channel4 (B4) have two input source: USB ISO input and
external pcm device. It is controlled by USB_EN bit. Setting USB_EN =1, the USB ISO data pass to pcm channel 4 .
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Publication Release Date: May, 2007
Revision 1.3
W681307
10.7
PCM Highway Interface
10.7.1
The Introduction of PCM Modes
10.7.1.1
Master / Slaver mode
For Master mode, PCM_CLK and PCM_FSC is output port.
For Slaver mode, PCM_CLK and PCM_FSC is input port.
PCM_CLK
.............
Bitclk
Bitclk
.............
PCM_FSC
PCM_IN
.....Rx_DELAY1..... M
8/16 BITS
L .....Rx_DELAY2..... M
8/16 BITS
L .....Rx_DELAY3..... M
8/16 BITS
L .....Rx_DELAY4..... M
8/16 BITS
L
PCM_OUT
.....Tx_DELAY1..... M
8/16 BITS
L ..... Tx_DELAY2..... M
8/16 BITS
L ..... Tx_DELAY3..... M
8/16 BITS
L ..... Tx_DELAY4..... M
8/16 BITS
L
10.7.1.2
Master mode
In master mode, PCM_CLK and PCM_FSC is output port.
PCM_FSC
8K short sync or long sync.
PCM_CLK
1536 KHz
PCM_IN
When sync is coming, it starts to catch MSB in (first sync rising + delay1 bits). LSB is depending 8bits or
16bits for first slot. Data rate is 1x or 1/2 Clk.
PCM_OUT
When sync is coming, it starts to send MSB in (first sync rising + delay1 bits). LSB is depending 8bits or
16bits for first slot. Data rate is 1x or 1/2 Clk.
Master Mode With Data Rate = 1x CLK
PCM_CLK
(Output)
PCM_FSC
Long Sync Mode
(Output)
PCM_FSC
Short Sync Mode
(Output)
PCM_IN
PCM_OUT
HI-Z
MSB
LSB
MSB
LSB
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HI-Z
Publication Release Date: May, 2007
Revision 1.3
W681307
Master Mode With Data Rate = 1/2 CLK
PCM_CLK
(Output)
PCM_FSC
Long Sync Mode
(Output)
PCM_FSC
Short Sync Mode
(Output)
PCM_IN
PCM_OUT
HI-Z
10.7.1.3
MSB
LSB
MSB
LSB
HI-Z
Slave mode
In slave mode, PCM_CLK and PCM_FSC is input port.
PCM_FSC
8K short sync or long sync.
PCM_CLK
768 KHz ~ 2048 KHz
PCM_IN
When sync is coming, it starts to catch MSB in (first sync rising + delay1 bits). LSB is depending 8bits or
16bits for first slot. Data rate is 1x or 1/2 Clk.
PCM_OUT
When sync is coming, it starts to send MSB in (first sync rising + delay1 bits). LSB is depending 8bits or
16bits for first slot. Data rate is 1x or 1/2 Clk.
Slave Mode With Data Rate = 1x CLK
PCM_CLk
(Input)
PCM_FSC
Long Sync Mode
(Input)
PCM_FSC
Short Sync Mode
(Input)
PCM_IN
PCM_OUT
MSB
HI-Z
MSB
LSB
LSB
HI-Z
Slave Mode with Data Rate = 1/2 CLK
PCM_CLK
(Intput)
PCM_FSC
Long Sync Mode
(Intput)
PCM_FSC
Short Sync Mode
(Input)
PCM_IN
PCM_OUT
MSB
HI-Z
MSB
LSB
LSB
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HI-Z
Publication Release Date: May, 2007
Revision 1.3
W681307
10.7.2
10.7.2.1
The Description of PCM Highway Interface Registers
PCM channel format and delay control of 1st group (PCM B1, PCM B2)
Address
Access Mode
Value At Reset
0x1700h
R/W
0x02
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCMB1_dis
Half rate
PCMB2_dis
RESERVED
Hizen
Half/Full
RESERVED
Data
16/8bits
RESERVED
Data 16/8bits
Set the bit to receive/transmit 16 bits; Reset the bit to receive/transmit 8 bits.
Hizen Half/Full
Set the bit to tristate in the end of the bit. Reset the bit to tristate in the falling edge of the end of the
bit.
PCMB2_dis
=1: disabling the B2 channel of the PCM Highway.
=0: enabling the B2 channel of the PCM Highway.
Half rate
Set the bit for one bit per 2 Bitclk (during data length being 16 bits=>0x1700 [1] =1’b1). Reset the bit
for one bit per 1 Bitclk.
PCMB1_dis
=1: disabling the B1 channel of the PCM Highway.
=0: enabling the B1 channel of the PCM Highway.
10.7.2.2
TX delay1
Address
Access Mode
Value At Reset
0x1701h
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TX delay1
Set the values for delaying the transmitted bits of PCM B1 channel after the rising edge of the frame pulse. The resolution is one bitclk in
full date rate and two Bitclk in half data rate.
10.7.2.3
TX delay2
Address
Access Mode
Value At Reset
0x1702h
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TX delay2
Set the values for delaying the transmitted bits of PCM B2 channel after the tail bit of PCM B1 channel. The resolution is one PCM
Bitclk in full date rate and two Bitclk in half data rate.
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Publication Release Date: May, 2007
Revision 1.3
W681307
10.7.2.4
RX delay1
Address
Access Mode
Value At Reset
0x1703h
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RX delay1
Set the values for delaying the received bits of PCM B1 channel after the rising edge of the Fsync. The resolution is one Bitclk in full
date rate and two Bitclk in half data rate.
10.7.2.5
RX delay2
Address
Access Mode
Value At Reset
0x1704h
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RX delay2
Set the values for delaying the received bits of PCM B2 channel after the tail bit of Rx PCM Highway B1 channel. The resolution is one
Bitclk in full date rate and two Bitclk in half data rate.
10.7.2.6
PCM channel format and delay control of 2nd group (PCM B3, PCM B4)
Address
Access Mode
Value At Reset
0x1708h
R/W
0x02
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCMB3_dis
Half rate
PCMB4_dis
RESERVED
Hizen
Half/Full
RESERVED
Data
16/8bits
RESERVED
Data 16/8bits
Set the bit to receive/transmit 16 bits; Reset the bit to receive/transmit 8 bits.
Hizen Half/Full
Set the bit to tristate in the end of the bit. Reset the bit to tristate in the falling edge of the end of the
bit.
PCMB4_dis
=1: disabling the B4 channel of the PCM Highway.
=0: enabling the B4 channel of the PCM Highway.
Half rate
Set the bit for one bit per 2 Bitclk (during data length being 16 bits=>0x1708 [1] =1’b1). Reset the bit
for one bit per 1 Bitclk.
PCMB3_dis
=1: disabling the B3 channel of the PCM Highway.
=0: enabling the B3 channel of the PCM Highway.
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Publication Release Date: May, 2007
Revision 1.3
W681307
10.7.2.7
TX delay3
Address
Access Mode
Value At Reset
0x1709h
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TX delay3
Set the values for delaying the transmitted bits of PCM Highway B3 channel after the tail bit of TX PCM Highway B2 channel. The
resolution is one Bitclk in full date rate and two Bitclk in half data rate.
10.7.2.8
TX delay4
Address
Access Mode
Value At Reset
0x170Ah
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TX delay4
Set the values for delaying the transmitted bits of PCM Highway B4 channel after the tail bit of TX PCM Highway B3 channel. The
resolution is one Bitclk in full date rate and two Bitclk in half data rate.
10.7.2.9
RX delay3
Address
Access Mode
Value At Reset
0x170Bh
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RX delay3
Set the values for delaying the received bits of PCM Highway B3 channel after the tail bit of RX PCM Highway B2 channel. The
resolution is one Bitclk in full date rate and two Bitclk in half data rate.
10.7.2.10
Rx delay4
Address
Access Mode
Value At Reset
0x170Ch
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RX delay4
Set the values for delaying the received bits of PCM Highway B4 channel after the tail bit of RX PCM Highway B3 channel. The
resolution is one Bitclk in full date rate and two Bitclk in half data rate.
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Publication Release Date: May, 2007
Revision 1.3
W681307
10.8
Digital Gain Multiplexer
There are 4 fine-tune on-chip gain stage allocated between multiplexer interface and half acoustic canceller block or behind multiplexer
interface. This gain stage is implemented by a digital multiplexer to provide a range of +12 dB to –12 dB with a resolution of 0.5 dB per
step. Figure 10-3 is shown the location of this digital gain multiplexer. The 4 channels FT Gain Stage support gain adjustment for
linear PCM signal for each PCM channel. Each channel has its independent gain registers for gain setting.
Gain Stage
#146Eh
C0
Half
AEC
CODEC
C1
Multiplexer
C2
#146Fh
#146Ch
#146Dh
#146Ah
#146Bh
# 1468h
C3
# 1469h
Figure 10-3 The location of digital fine-tuning gain stage
10.8.1
Fine-Tuning Gain Stage Registers
10.8.1.1
FTInGain3
Address
Access Mode
Value At Reset
0x1468
R/W
0x00
Nominal Value
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Publication Release Date: May, 2007
Revision 1.3
W681307
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
FTInGain[5]
FTInGain[4]
FTInGain[3]
FTInGain[2]
FTInGain[1]
FTInGain[0]
Refer to Table 10-1 for fine tune input gain. This gain is applied to the input data of processor channel C3.
10.8.1.2
FTOutGain3
Address
Access Mode
Value At Reset
0x1469
R/W
0x00
Bit 7
Bit 6
Bit 5
RESERVED
RESERVED
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
FTOutGain[5] FTOutGain[4] FTIOutGain[3] FTOutGain[2] FTOutGain[1] FTOutGain[0]
Refer to Table 10-1 for fine tune output gain. This gain is applied to the output data of processor channel C3.
10.8.1.3
FTInGain2
Address
Access Mode
Value At Reset
0x146A
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
FTInGain[5]
FTInGain[4]
FTInGain[3]
FTInGain[2]
FTInGain[1]
FTInGain[0]
Refer to Table 10-1 for fine tune input gain. This gain is applied to the input data of processor channel C2.
10.8.1.4
FTOutGain2
Address
Access Mode
Value At Reset
0x146B
R/W
0x00
Bit 7
Bit 6
Bit 5
RESERVED
RESERVED
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
FTOutGain[5] FTOutGain[4] FTIOutGain[3] FTOutGain[2] FTOutGain[1] FTOutGain[0]
Refer to Table 10-1 for fine tune output gain. This gain is applied to the output data of processor channel C2.
10.8.1.5
FTInGain1
Address
Access Mode
Value At Reset
0x146C
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
FTInGain[5]
FTInGain[4]
FTInGain[3]
FTInGain[2]
FTInGain[1]
FTInGain[0]
Refer to Table 10-1 for fine tune input gain. This gain is applied to the input data of processor channel C1.
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Publication Release Date: May, 2007
Revision 1.3
W681307
10.8.1.6
FTOutGain1
Address
Access Mode
Value At Reset
0x146D
R/W
0x00
Bit 7
Bit 6
Bit 5
RESERVED
RESERVED
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
FTOutGain[5] FTOutGain[4] FTIOutGain[3] FTOutGain[2] FTOutGain[1] FTOutGain[0]
Refer to Table 10-1 for fine tune output gain. This gain is applied to the output data of processor channel C1.
10.8.1.7
FTInGain0
Address
Access Mode
Value At Reset
0x146E
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
FTInGain[5]
FTInGain[4]
FTInGain[3]
FTInGain[2]
FTInGain[1]
FTInGain[0]
Refer to Table 10-1 for fine tune input gain. This gain is applied to CODEC PCM output data. This gain can be also adjusted to consider
the power requirement of the half acoustic echo canceller.
10.8.1.8
FTOutGain0
Address
Access Mode
Value At Reset
0x146F
R/W
0x00
Bit 7
Bit 6
RESERVED
RESERVED
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
FTOutGain[5] FTOutGain[4] FTIOutGain[3] FTOutGain[2] FTOutGain[1] FTOutGain[0]
Refer to Table 10-1 for fine tune output gain. This gain is applied to CODEC PCM input data. This gain can be also adjusted to consider
the power requirement of the half acoustic echo canceller.
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Publication Release Date: May, 2007
Revision 1.3
W681307
Table 10-1
mute.
： Fine-tuning input, output gain (decimal index). The 5-bit numbers allow +/- 12 dB adjustment in 0.5 dB steps and hard
FT In/out Gain [4:0]
Gain Value
FT In/out Gain [4:0]
Gain Value
0x00
0 dB
0x19
-0.5 dB
0x01
0.5 dB
0x1A
-1.0 dB
0x02
1.0 dB
0x1B
-1.5 dB
0x03
1.5 dB
0x1C
-2.0 dB
0x04
2.0 dB
0x1D
-2.5 dB
0x05
2.5 dB
0x1E
-3.0 dB
0x06
3.0 dB
0x1F
-3.5 dB
0x07
3.5 dB
0x20
-4.0 dB
0x08
4.0 dB
0x21
-4.5 dB
0x09
4.5 dB
0x22
-5.0 dB
0x0A
5.0 dB
0x23
-5.5 dB
0x0B
5.5 dB
0x24
-6.0 dB
0x0C
6.0 dB
0x25
-6.5 dB
0x0D
6.5 dB
0x26
-7.0 dB
0x0E
7.0 dB
0x27
-7.5 dB
0x0F
7.5 dB
0x28
-8.0 dB
0x10
8.0 dB
0x29
-8.5 dB
0x11
8.5 dB
0x2A
-9.0 dB
0x12
9.0 dB
0x2B
-9.5 dB
0x13
9.5 dB
0x2C
-10.0 dB
0x14
10.0 dB
0x2D
-10.5 dB
0x15
10.5 dB
0x2E
-11.0 dB
0x16
11.0 dB
0x2F
-11.5 dB
0x17
11.5 dB
0x30
-12.0 dB
0x18
12.0 dB
0x3F
Mute
- 69 -
Publication Release Date: May, 2007
Revision 1.3
W681307
11. PROCESSOR INTERFACE
11.1
Overview
The Processor Interface controls reads and writes made by the Processor to the on-chip RAM and on-chip registers.
11.2
Functionality
Figure 11-1 shows the processor interface block diagram.
Figure 11-1 Illustration of the Processor Interface
11.3
Processor Access Sequencer
：
The Processor Access Sequencer has 2 functions
•
•
Internal Register access sequencing
On-Chip RAM access sequencing
External RAM accesses, external ROM accesses and internal register reads are performed directly by the 8032Turbo, the Address
Decoder and Read Multiplexer. No action is required by the Processor Access Sequencer.
The operation of the Processor Access Sequencer for internal register writes is shown in Figure 11-2.
Note that
•
•
：
The sequence of a register write is not affected by the setting of STRECH.
The Internal Register Clock Enable signal SysClock2En is active for 4 cycles to allow internal events to be scheduled after a
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Publication Release Date: May, 2007
Revision 1.3
W681307
•
register writes.
The Internal Address Bus IntAddress is a latched version of the Processor Address bus, updated when an internal accesses is
required. This reduces internal transitions on the chip to save power.
S1
S2
S3
S4
S1
TurboClock
TurboAle
TurboWr
TurboPort2
A 8 - A15
TurboPort0
A 0 - A7
Data Out
System Clock
IntRegSelect
SysClock2En
SysClock2
IntRegClk
Write Enable
Figure 11-2 Timing of Internal Register Writes
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Publication Release Date: May, 2007
Revision 1.3
W681307
：
The operation of the Processor Access Sequencer for access to the On-Chip RAM is shown in Figure 11-3.
Note that
•
•
The On-Chip RAM is a clocked-synchronous RAM.
The data read out of the On-Chip RAM is latched in the Processor Interface.
Figure 11-3 Timing of On-Chip RAM Access
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Publication Release Date: May, 2007
Revision 1.3
W681307
11.4
Read Multiplexer
The Read Multiplexer multiplexes the following data onto the internal 8032Turbo data bus:
•
•
•
•
On-chip registers
On-Chip RAM
Speech Processor Registers
Off-Chip Bus Interface
Each function performs local address decoding for both Reads and Writes. For register reads, each block multiplexes the addressed
register onto a single output bus and asserts a Data Valid signal.
All internal modules present zero on the read data buses when not selected.
In the case of support logic, processor interface, speech interface and interface logic these modules decode a lower part of the address bus,
so may present data out at various points in the memory map.
For other blocks all the decoding is done within the processor interface.
A data inputs are qualified with appropriate Address Decoder outputs. This ensures that only the required sub-module data is presented to
the 8032Turbo.
11.5
Processor Interface Control Registers
11.5.1
AuxOpPort
Address
Access Mode
Value At Reset
0x1470
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
CS1R2
CS1R1
CS1R0
AuxOp
Port1En
AuxOpPort1
AuxOp
Port0En
AuxOpPort0
CS1 and CS2 can be set as general output port, 0x1470 bit1 and bit3 enable this function independently. AuxOpPort0 means CS1 and
AuxOpPort1 means CS2. When you enable the general output function, the CS1/CS2 will be not in address decode mode. Figure 11-4
shows /CS1 & /CS2 output multiplexer.
AuxOpPort0
AuxOpPort0En
AuxOpPort1
The AuxOpPort data bits contain TRUE data.
When set, enable the AuxOpPort 0.
The AuxOpPort data bits contain TRUE data.
AuxOpPort1En
When set, enable the AuxOpPort 1.
The AuxOpPort enables are active high.
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Publication Release Date: May, 2007
Revision 1.3
W681307
A uxO pP ort0
0x1470 [0]
/C S 1
0
3
/W R
P in N a m e
1
2
/R D
A uxO pP ort0E n
0 x1470[1 ]
1
/C S 1
0
0x1 472[1:0 ]
A uxO pP ort1
0x1470 [2]
/C S 2
0
3
/W R
P in N a m e
1
2
/R D
A uxO pP ort1E n
0 x1470[3 ]
1
/C S 2
0
0x1 472[3:2 ]
Figure 11-4
/CS1 & /CS2 output multiplexer
The CS1 range is defined as:
CS1R2
0
0
0
0
1
1
1
1
11.5.2
CS1R1
0
0
1
1
0
0
1
1
CS1R0
0
1
0
1
0
1
0
1
Depth
4KB
8KB
12KB
16KB
20KB
24KB
28KB
32KB
Address Range
0x8000
0x8FFF
0x8000
0x9FFF
0x8000
0xAFFF
0x8000
0xBFFF
0x8000
0xCFFF
0x8000
0xDFFF
0x8000
0xEFFF
0x8000
0xFFFF
DiagSel
Address
Access Mode
Value At Reset
0x1471
R/W
0x00
Nominal Value
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Publication Release Date: May, 2007
Revision 1.3
W681307
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
11.5.3
Diag_CS
Address
Access Mode
Value At Reset
0x1472
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
CS2R2
CS2R1
CS2R0
CS2_Sel[1]
CS2_Sel[0]
CS1_Sel[1]
CS1_Sel[0]
CS1 & CS2 can be selected output for setting the bits
CS1 & CS2 output multiplexer (See Figure 11-4)
CS1[1:0] / CS2[3:2]
00
01
10
11
Output
CS1 / CS2
CS1|RD / CS2|RD
CS1|WD / CS2 |WD
~((CS 1 | RD) & (CS1 | WR)) / ~((CS 2 | RD) & (CS2 | WR))
The CS2 range is defined as:
CS2R2
0
0
0
0
1
1
1
1
CS2R1
0
0
1
1
0
0
1
1
CS2R0
0
1
0
1
0
1
0
1
Depth
4KB
8KB
12KB
16KB
20KB
24KB
28KB
32KB
Address Range
0xF000
0xFFFF
0xE000
0xFFFF
0xD000
0xFFFF
0xC000
0xFFFF
0xB000
0xFFFF
0xA000
0xFFFF
0x9000
0xFFFF
0x8000
0xFFFF
CS1 and CS2 can address 32 K totally. So for example, you set CS2 for addressing 12 KB, then CS1 only address 20KB .
CS1: 0x8000H~ 0xCFFFH ; CS2 : 0xD0000H~0xFFFFH.
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11.5.4
Diag_CS3
Address
Access Mode
Value At Reset
0x1473
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RD_WR_BLK
CS2_WAIT
_EN
CS3_SEL[1]
CS3_SEL[0]
PWR_SAVE[1]
PWR_SAVE[0]
3
/ WR
2
Pin Name
/CS3
/RD
1
/CS3
0
0x 1473[3:2]
Figure 11-5 CS3 Output multiplexer
CS3 output multiplexer is shown in Figure 11-5. Address mapping range of CS3 is 0x2000~0x5FFF
CS3_sel[1:0]
00
01
10
11
Output
CS3
CS3 | RD
CS3 | WD
~((CS 3 | RD) & (CS3 | WR))
CS2_WAIT_EN
This is a wait state enable bit for CS2 controlled device. When set this bit, the WR/RD duration
to CS2 controlled device will last from 4 clock cycles to 8 clock cycles.
RD_WR_BLK
When set this bit, the external RD/WR signal will not active (blocked) when access internal
RAM/register (0x0000 to 0x1FFF and 0x6000 to 0x7FFF), the default is not blocked.
PWR_SAVE [1:0]
You can set PWR_SAVE [1:0] to control AD/ADDR bus output state for I/O power save purpose.
PWR_SAVE[1:0]
00
01
10
11
AD/ADDR bus
No power save feature.
AD/ADDR bus only active when T8032 RD/WR in the Mask ROM mode.
AD/ADDR bus only active when T8032 RD/WR external device
(0x8000~0xFFFF),in the Mask ROM mode.
AD/ADDR bus always inactive.
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11.5.5
Multiplier_Enable
Address
Access Mode
Value At Reset
0x1474
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Mul8x8_en
Mul8x8_en
11.6
This is an enable bit of a fast 8x8 multiplier in T8032.When set this bit, a fast T8032 internal 8x8 multiplier will be
active otherwise the original T8032 add-shift multiplier is the default choice.
In System Programming Mode
In System Programming mode is designed for fast program on board flash. Flash type includes 29, 39 and 49 series. The chip is provided
two ISP entry modes. One is hardware setting and the other is software command mode.
This function comes with the PC software, which transfer the binary code to internal T8032 to program the external ROM flash. ISP
function use internal T8032 UART or USB port to transfer data, the default baud rate of the UART port is 9600bps, which can be set by
remote PC program. There are four baud-rates for selection, 9600bps, 19200bps, 28800bps and 57600bps. The double-speed MCU chip
(2x), you can select optional 115200bps for flash program.
11.6.1
Hardware Setting Usage
In the initial power-up state, the /CS2 pin will replaced as ISP function hardware setting pin. When /CS2 pin set to low and re-power up
the system, the chip will execute the internal ISP code, and wait for PC command and binary data to update the external ROM flash. If the
/CS2 is set to output purpose pin (the pin is default pull-up), this chip will in normal mode. The flash needed an external write signal. The
ISP_WR pin of the chip needs to connect to the /WR pin of the external Flash and which pin only active in ISP operation.
11.6.2
Software Command Usage
This ISP function can provide the system program update from the internal USB or UART ports with software command
and don’t need any hardware modification. Therefore the baseband chip doesn’t need extra circuit to support this function.
Figure 11-6 is shown the function description and specification.
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ISP_EN
ISP hardware module generates
ISP hardware module generates
ISP_RST
ISP Program completes the ISP mode
Program set ISP_EN
Hardware switch to run the
HW_ISP_EN
internal mask ISP ROM code of
Hardware switch to normal
baseband. And the all the
operation to run the external
internal registers of baseband
flash ROM code.
chip will band-switch to P1.7.
MCU
Baseband external Flash
Baseband internal mask ROM ISP code operation to
into
ROM code operation
RST
idle
download program code to external flash from USB or
UART port dependent on the ISP command source
mode
MCU
into
idle
mode
Baseband
RST
external Flash
ROM code
operation
Figure 11-6 The software ISP operation procedure
11.6.3
ISP_CTRL (Hardware & Watchdog Reset Control Register)
Address
Access Mode
Value At Reset
0x1900
RW
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ISP_EN
Reserved
Reserved
Reserved
Reserved
Reserved
USB_ISP
UART_ISP
This ISP control register is provided the In-system-programming function to update the system program code without modification
hardware. This function can be enabled by the bit 7 of ISP_CTRL control register. And the enable command which is come from the
internal UART port or USB interface.
UART_ISP
This bit is reserved for ISP mask rom program recognition which type ISP mode is enabled. When ISP enabled command
is come from internal UART port. Then the normal program will set this bit for recognition in ISP mode period before
enabled ISP_EN bit. And download program data will come from UART port in the ISP programming period.
USB_ISP
The bit function is the same as UART_ISP.
ISP_EN
When set this bit will enable ISP mode to program the external flash ROM via the internal USB interface or UART port.
11.6.4
Specific Register
Address
Access Mode
Value At Reset
0x1901
RW
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Blocked
(for test modes)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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11.7
MASK ROM Mode
Mask ROM Mode is designed to use the internal mask ROM, besides this MCU chip also can disable the internal mask ROM to use
external flash ROM. Although MCU chip provide ISP mode and MASK ROM mode but you cannot use it simultaneously. Each function
is independent function.
11.7.1
Usage
When set EXT_ROM pin to low, the chip will execute the internal mask ROM code. When set EXT_ROM pin to high, the chip will
execute the external flash ROM code.
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12.
SPEECH PROCESSOR
：
The Speech Processor provides a complete implementation, including
•
•
•
•
4 duplex channels
1 channel Echo Canceller
A Mixer Block
Programmable Tone Generators
The Speech Processor supports A-law, µ-law and 16-bits linear PCM formats. Echo canceller channels support 16 bits linear PCM only.
The Speech Processor is implemented by an optimized micro-coded DSP, an external FIR Filter Engine and one digital gain multiplexer.
The architecture of the Speech Processor can be shown in Figure 12-1.
The Microcode DSP Core:
•
•
Performs Tone Generation
Performs PCM Mixing
The FIR Engine:
•
•
•
•
12.1
Performs real-time Echo Estimation
Implements Network Echo Suppression
Calculates the Echo Cancellation filter coefficients
Performs intermediate calculations on the Echo Estimation error
Transcoder DSP
The Transcoder DSP is a low power implementation and has the following features:
•
•
•
•
•
Low power consumption and low gate count
Group delay under 14 µs / channel
DTMF and call progress tones
Sidetone generation and Volume control
Requires only 4.1 MIPS per channel
The Transcoder DSP supports A-law, µ-law and 16-bits linear PCM formats. Format selection is programmable on a by-channel basis.
：
The signal flow (per channel) is shown in Figure 12-1 below
INPUT
GAIN
PCM_IN
+
PCM
FORMAT
MIXER
MATRIX
TONE
GEN
PCM_OUT
SIDE
TONE
+
MIXER
MATRIX
+
OUTPUT
GAIN
Figure 12-1 Transcoder signal flow
There are dual-tone generators for each PCM channel. These can generate DTMF and common signaling tones, as well as user
notification tones. The tones may be added in either direction. A mixer function is enabled by setting 1401[0]. Four full-duplex PCM
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channels can be connected / mixed together in any combination. This function is controlled by programmable registers. Moreover, the
speech logic interface (which is not needed by the CODEC) of four channels must be enabled.
12.2
The Description of the Activation Registers
12.2.1
MIXER_EN
Address
Access Mode
Value At Reset
0x1401
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Blocked
Blocked
Blocked
Blocked
Blocked
Blocked
Blocked
(for test modes) (for test modes) (for test modes) (for test modes) (for test modes) (for test modes) (for test modes)
MIXER_EN
MIXER_EN
Set to enable the mixer block.
12.2.2
SPEECH LOGIC_EN
Address
Access Mode
Value At Reset
0x1420
R/W
0x04
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Blocked
Blocked
Blocked
Blocked
Blocked
Blocked
Blocked
(for test modes) (for test modes) (for test modes) (for test modes) (for test modes) (for test modes) (for test modes)
SPEECH LOGIC_EN
12.3
Bit 0
Bit 0
SPEECH
LOGIC_EN
Set to enable speech logic interface (which is not needed by the CODEC) of four channels.
The Description of Transcoder DSP Registers
The transcoder block is programmed via microprocessor accessible programming registers.
All registers allow read/write access and reset to zero except as noted. All bits not specified below are reserved or blocked and should
only be written with zeros. Unspecified bits read back zero.
The transcoder registers are divided into `Global registers' and `Channel-specific registers'.
：
Global registers
•
Consist of SideTone (0x148D) and Lookback_EN (0x148E) registers.
：
Channel-specific registers
Channel-specific registers appear in four groups at offsets of sixteen bytes.
•
•
•
•
Channel 0 registers appear at addresses 0x1480 -> 0x148C
Channel 1 registers appear at addresses 0x1490 -> 0x149C
Channel 2 registers appear at addresses 0x14A0 -> 0x14AC
Channel 3 registers appear at addresses 0x14B0 -> 0x14BC
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12.3.1
Connect0
Address
Access Mode
Value At Reset
0x1480
R/W
0x01
Bit 7
Bit 6
Bit 5
Bit 4
PCM channel 3 PCM channel 2 PCM channel 1 PCM channel 0
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
Blocked
Blocked
Blocked
* Blocked
(for test modes) (for test modes) (for test modes) (for test modes)
Specify mixing among four PCM channels. This register enables the connections of each PCM channels.
Bits [7:4]
correspond to PCM channels 3:0.
* Blocked (for test modes)
must be set to 1.
When the value of the bit is set to 1, it enables the addition of the corresponding channel in mixing. An additive connection is set up
between the specified channels.
12.3.2
Specified Register
Address
Access Mode
Value At Reset
0x1481
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
12.3.3
Bit 1
Bit 0
Blocked
Blocked
(for test modes) (for test modes)
Specified Register
Address
Access Mode
Value At Reset
0x1482
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Blocked
(for test modes)
12.3.4
Specified Register
Address
Access Mode
Value At Reset
0x1483
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Blocked
(for test modes)
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12.3.5
PCMmode0
Address
Access Mode
Value At Reset
0x1484
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
COMP_FORMAT
PCM_LINEAR
PCM_LINEAR
=1, PCM port 0 operates in 16-bit linear mode.
=0, 8-bit compressed PCM.
COMP_FORMAT
If PCM port 0 is in compressed mode,
=1, A-law,
=0, µ -law
12.3.6
InputGain0
Address
Access Mode
Value At Reset
0x1485
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
RESERVED
InputGain[3]
InputGain[2]
InputGain[1]
InputGain[0]
InputGain[3:0]
PCM input gain table is listed as below Table 12-1. This gain is applied directly to the PCM input value.
12.3.7
OutputGain0
Address
Access Mode
Value At Reset
0x1486
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
RESERVED
RESERVED
RESERVED
RESERVED
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
OutputGain[3] OutputGain[2] OutputGain[1] OutputGain[0]
OutputGain[3:0]
PCM output gain table is listed as below Table 12-2. This gain is applied after the Mixer Matrix and tone generation.
12.3.8
ToneFreqA0
Address
Access Mode
Value At Reset
0x1488
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
ToneFreqA
Frequency of tone A = ToneFreqA * 15.625 (Hz)
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12.3.9
ToneFreqB0
Address
Access Mode
Value At Reset
0x1489
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
ToneFreqB
Frequency of tone B = ToneFreqB * 15.625 (Hz)
12.3.10
ToneVolA0
Address
Access Mode
Value At Reset
0x148A
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
ToneVolA[4]
ToneVolA[3]
ToneVolA[2]
ToneVolA[1]
ToneVolA[0]
Tone level is listed as below Table 12-3 for tone generator A.
12.3.11
ToneVolB0
Address
Access Mode
Value At Reset
0x148B
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
ToneVolB[4]
ToneVolB[3]
ToneVolB[2]
ToneVolB[1]
ToneVolB[0]
Tone level is listed as below Table 12-3 for tone generator B.
12.3.12
ToneEna0
Address
Access Mode
Value At Reset
0x148C
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Tx_tone
Rcv_tone
Rcv_tone
=1, add tone generators to the receiving (PCM_OUT) path. Receive tones are added just before the PCM output gain
stage.
Tx_tone
=1, add tone generators to the transmitting (PCM_IN) path. Transmit tones are added just after the PCM input gain
stage.
WARNING: enabling tones in both directions at the same time causes the output frequencies to double.
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12.3.13
SideTone
Address
Access Mode
Value At Reset
0x148D
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
SideTone[4]
SideTone[3]
SideTone[2]
SideTone[1]
SideTone[0]
SideTone[4:0]
SideTone[4:0]
Side tone gain is listed as below Table 12-4. This is applied to all active PCM channels between the Mixer Matrix and
PCM formatting. Please refer to 0x14AF to enable the active sidetone channel.
=0, to disable side tone.
12.3.14
Loopback_EN
Address
Access Mode
Value At Reset
0x148E
R/W
0x00
Bit 7
Bit 6
* Blocked
RESERVED
(for test modes)
Bit 5
Bit 4
RESERVED
RESERVED
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
Blocked
Blocked
Blocked
Loopback_EN
(for test modes) (for test modes) (for test modes)
Loopback_EN
=1, loopback behind the side tone function in the transmitting (PCM_IN) path.
* Blocked (for test modes) must be set to 1.
12.3.15
Specified Register
Address
Access Mode
Value At Reset
0x148F
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
Blocked (for test modes)
12.3.16
Connect1 ~ ToneEna1
Address
Access Mode
Value At Reset
0x1490 ~ 0x149C
R/W
0x00
Nominal Value
The functions are the same as channel 0.
12.3.17
Connect2 ~ ToneEna2
Address
Access Mode
Value At Reset
0x14A0 ~ 0x14AC
R/W
0x00
Nominal Value
The functions are the same as channel 0.
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12.3.18
SideToneChannel_Ena
Address
Access Mode
Value At Reset
0x14AF
R/W
0x01
Bit 7
Bit 6
Bit 5
Bit 4
RESERVED
RESERVED
RESERVED
RESERVED
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
SideTone_ch3 SideTone_ch2 SideTone_ch1 SideTone_ch0
The register can enable side tone individually for the each active pcm channel.
12.3.19
Connect3 ~ ToneEna3
Address
Access Mode
Value At Reset
0x14B0 ~ 0x14BC
R/W
0x00
Nominal Value
The functions are the same as channel 0.
12.4
PCM Mixer Matrix
The registers Connect0-3 specify channels which should be connected together and enable the corresponding PCM channels. The
connection registers of each specified PCM channels can be set to the same value simultaneously. The result is the same that one of each
registers be set. For example, The PCM0 and PCM1 channels need to be connected. So the 1480 and 1490 can be set to 31. The effect is
the same that only 1480 or 1490 is set.
12.5
Gain Tables
There are four gain functions in this block: PCM I/O gain, side tone gain and tone gain (level).
Table 12-1 The PCM Input gain is provided to allow minor corrections for board-level analogue gain problems. The 4-bit numbers allow
+/- 10 dB adjustments and hard mute.
InputGain (3:0)
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
Nominal gain
0 dB
+1 dB
+2 dB
+3 dB
+4 dB
+6 dB
+8 dB
+10 dB
-∞ (Hard mute)
-10 dB
-8 dB
-6 dB
-4 dB
-3 dB
-2 dB
-1 dB
- 86 -
Actual gain
0 dB
+1.0
+2.0
+2.8
+4.2
+6.0
+8.0
+9.5
-∞
-10.1
-8.5
-6.0
-4.1
-3.2
-1.8
-1.2
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Revision 1.3
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Table 12-2 The PCM Output gain is provided to allow minor corrections for board-level analogue gain problems. The 4-bit numbers
allow +/- 16 dB adjustments and hard mute.
OutputGain(3:0)
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
Nominal gain
0 dB
+1.5 dB
+3 dB
+5 dB
+7 dB
+10 dB
+13 dB
+16 dB
-∞ (Hard mute)
-16 dB
-13 dB
-10 dB
-7 dB
-5 dB
-3 dB
-1.5 dB
Actual gain
0 dB
+1.9
+3.5
+4.9
+7.0
+9.9
+13.5
+15.6
-∞
-18.1
-12.0
-8.5
-6.0
-4.1
-2.5
-1.2
Table 12-3 Tone levels are specified in linear values, referenced to ½ of the max PCM level (+3.17 dBm0). Tone level = -2.85 dBm0 +
20 log10 (TONEVOL / 32). Because there are 32 legal values, the following table contains only example values.
Tone Generator Gain Value
TONEVOLx(4:0)
Actual level
(dBm0)
TONEVOLx(4:0)
Actual level
(dBm0)
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
Disable
-32.9530
-26.9324
-23.4106
-20.9118
-18.9736
-17.3900
-16.0510
-14.8912
-13.8681
-12.9530
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
-12.1251
-11.3694
-10.6741
-10.0304
-9.4312
-8.8706
-8.3440
-7.8475
-7.3779
-6.9324
-6.5086
- 87 -
TONEVOLx(4:0)
Actual level
(dBm0)
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
-6.1045
-5.7184
-5.3488
-4.9942
-4.6535
-4.3257
-4.0098
-3.7050
-3.4106
-3.1258
Publication Release Date: May, 2007
Revision 1.3
W681307
Table 12-4 The side tone gain is adjustable from -32 dB to 0 dB in 1 dB steps. Setting this register to 0 disables side tone.
Side Tone Gain value
Index
Value
Index
Value
0x00
Mute
0x10
-15 dB
0x01
0 dB
0x11
-16 dB
0x02
-1 dB
0x12
-17 dB
0x03
-2 dB
0x13
-18 dB
0x04
-3 dB
0x14
-19 dB
0x05
-4 dB
0x15
-20 dB
0x06
-5 dB
0x16
-21 dB
0x07
-6 dB
0x17
-22 dB
0x08
-7 dB
0x18
-23 dB
0x09
-8 dB
0x19
-24 dB
0x0A
-9 dB
0x1A
-25 dB
0x0B
-10 dB
0x1B
-26 dB
0x0C
-11 dB
0x1C
-28 dB
0x0D
-12 dB
0x1D
-30 dB
0x0E
-13 dB
0x1E
-32 dB
0x0F
-14 dB
0x1F
-36 dB
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Revision 1.3
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13.
13.1
ECHO CANCELLER
Half AEC Block Diagram
The acoustics echo cancellation unit removes the echo signal inserted by the speaker and space.
Figure 13-1 illustrates the block diagram of the Half Acoustics Echo Canceller in the Speech Processor.
Figure 13-1 The signal flow through the Acoustics Echo Canceller in the Speech Processor
13.1.1
Acoustics Suppression
When enabled (and so, switched into the network output data path) the acoustic suppression unit will insert a configurable attenuation
factor into the network output path. The attenuation will switch between a maximum and minimum value depending on the presence or
absence of speech on the network output data path. When speech is present the attenuation will converge towards the minimum value.
When speech is absent the attenuation will converge towards the maximum value. The attenuation factor will not switch abruptly between
these two factors but will exponentially converge from one to the other.
When enabled the network output data path will include the following arithmetic unit
：
Nout ∝ Nout ∗ AS _ ATTENUATIO N
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Revision 1.3
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13.1.2
Network Power Estimation
To detect the double talk condition an estimate of the long term network power is required.
The long term network power is estimated with the following arithmetic unit
(
：
)
 Nin n ∗ 2VD _ LONG _ NETWORK _ ATTACK _ TC −16

Pninn ∝ Pninn−1 +  − Pninn −1 ∗ 2VD _ LONG _ NETWORK _ ATTACK _ TC −16

 + Vd _ Long _ Network _ Threshold ∗ 2VD _ LONG _ NETWORK _ ATTACK _ TC −17

(
(
The short term network power is estimated with the following arithmetic unit
(
)






)
：
)
 Nin n ∗ 2VD _ SHORT _ NETWORK _ ATTACK _ TC −16
PninShort n ∝ PninShort n −1 + 
 − PninShort ∗ 2VD _ SHORT _ NETWORK _ ATTACK _ TC −16
n −1

(
The deviation term network power is estimated with the following arithmetic unit




)
：
PninDevn ∝ Pninn − Cut _ Off _ Network _ Power − PninShortn
13.1.3
Acoustic Power Estimation
This speech will have originated at the near end and does not correspond to a reflected echo signal. Speech is deemed to occur if the long
term acoustic power exceeds a predetermined threshold or if the short term acoustic power exhibits sudden variations. If speech is being
carried over both the network and acoustic interfaces then the double talk condition occurs.
The long term acoustic power is estimated with the following arithmetic unit
(
：
)
 Ain n ∗ 2 DT _ LONG _ ACOUSTIC _ ATTACK _ TC −16
Pain n ∝ Pain n −1 + 
 − Pain ∗ 2 DT _ LONG _ ACOUSTIC _ ATTACK _ TC −16
n −1

(
The short term acoustic power is estimated with the following arithmetic unit
(




)
：
)
 Ain n ∗ 2 DT _ SHORT _ ACOUSTIC _ ATTACK _ TC −16
PainShort n ∝ PainShort n −1 + 
 − PainShort ∗ 2 DT _ SHORT _ ACOUSTIC _ ATTACK _ TC −16
n −1

(
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



)
Publication Release Date: May, 2007
Revision 1.3
W681307
13.1.4
Auto Gain Control
The short term cancelled power is estimated with the following arithmetic unit
：
 ( Hsout ∗ 2 AGC _ ST _ ATTACK _ TC −16 )


+
 − (PgShort ∗ 2 AGC _ ST _ ATTACK _ TC −16 )
n −1


PgShort n ∝ PgShort n −1
：
The AGC module is operated with the following algorithm
( Hsout > PgShort)
If
then PgShort = Hsout
If PgShort < AGC _ NOISE _ THRESHOLD
then Sg = 1
Else Sg =
AGC _ THRESHOLD
PgShort
If Sg > AGC _ MAX _ SG
then Sg = AGC _ MAX _ SG
The long term AGC module gain is estimated with the following arithmetic unit
Sglong n ∝ Sglong n −1
：
 (Sg ∗ 2 AGC _ LG _ ATTACK _ TC −16 )


+ 
AGC _ LG _ ATTACK _ TC −16 
(
)
−
Sglong
∗
2
n
−
1


If Sglong > Sg
then Sglong = Sg
13.2
The Software Interface of Speech Processor
The following registers are used to configure the echo canceller. All registers may be both read and written by software. The width of
each location will be a byte within the memory map. Some locations may have unused bits which will be returned undefined values on a
read cycle. Information in these bit positions will be discarded on write cycles.
：
The registers within the echo cancellation unit may be segmented into two classes Activation Registers and Performance Adjustment
Registers. An overview of each register class and nominal values to program each register is presented.
13.3
Activation Registers
13.3.1
UP_CONFIG
Address
Access Mode
Value At Reset
Nominal Value
0x14C0
R/W
0x00
0x82
Bit 7
Bit 6
AGC
RESERVED
Bit 5
Bit 4
Bit 3
Bit 2
Blocked
Blocked
Blocked
Blocked
(for test modes) (for test modes) (for test modes) (for test modes)
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Bit 1
Bit 0
AS1_ENA
Blocked
(for test modes)
Publication Release Date: May, 2007
Revision 1.3
W681307
AS1_ENA
When set, the acoustic suppression (AS1) function will be enabled.
AGC
When set, enable AGC function.
* The acoustic suppression (AS2) function is always enabled.
13.3.2
UP_RESET
Address
Access Mode
Value At Reset
Nominal Value
0x14C1
R/W
0x08
0x00
Bit 7
Bit 6
Blocked
(for test modes)
Bit 5
RESERVED
RESERVED
Power Down
When set,
AEC_Reset
When set,
13.3.3
Bit 4
AEC_Reset
Bit 3
Bit 2
Power Down
Bit 1
Bit 0
Blocked
Blocked
Blocked
(for test modes) (for test modes) (for test modes)
Power down the AEC unit to save power. Speech signal will bypass AEC
module.
Setting this bit will cause the AEC registers, including the activation registers
and performance adjustment registers, to be reseted to their hardware reset
values.
EC_BELTA
Address
Access Mode
Value At Reset
Nominal Value
0x14C2
R/W
0x03
0xE0
Bit 7
Bit 6
Bit 5
Bit 4
NS_Enable
NetAcIdle
* Blocked
(for test modes)
Absolute
Bit 3
Bit 2
Bit 1
Bit 0
Blocked
(for test modes)
Absolute
When set, the double talk detection algorithm is based on absolute value of Acoustic power.
NetAcIdle
When set, the double sides don’t have any voice; it will mute in Network side.
NS_Enable
If this bit is set "0", noise suppressor is by-passed. If this bit is set "1", then noise suppressor is enabled.
* Blocked (for test modes)
must be set to 1.
13.3.4
Specific Register
Address
Access Mode
Value At Reset
Nominal Value
0x14C3
R/W
0x03
0x03
Bit 7
Bit 6
RESERVED
13.4
Bit 5
RESERVED
RESERVED
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Blocked
(for test modes)
RESERVED
Performance Adjustment Registers
13.4.1
13.4.1.1
Acoustic Suppressor Register
AS_BUILD_UP_TIME
Address
Access Mode
Value At Reset
Nominal Value
0x14C4
R/W
0x07
0x55
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Revision 1.3
W681307
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
AS2_BUILD_UP_TIME
Bit 1
Bit 0
AS1_BUILD_UP_TIME
Control register for acoustic suppression factor convergence towards target.
Raising (lowering) the value of this field will lower (raise) the inertial delay present when the acoustic suppression unit responds to the
presence or absence of speech.
13.4.1.2
AS_MAX_ATTEN
Address
Access Mode
Value At Reset
Nominal Value
0x14C5 - 0x14C6
R/W
0x1CA8
0x0200
Bit 15
Bit 14
Bit 13
Bit 12
C5
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
AS1 & AS2_MAX_ATTEN
Bit 7
Bit 6
Bit 5
Bit 4
C6
Bit 3
AS1 & AS2_MAX_ATTEN
Maximum attenuation value will be utilized by the acoustic suppression algorithm.
The maximum value of this field provides an attenuation factor of 1.
The minimum value provides an attenuation factor of 0.
13.4.1.3
AS_MIN_ATTEN
Address
Access Mode
Value At Reset
Nominal Value
0x14C7 - 0x14C8
R/W
0xFFFF
0xFFFF
Bit 15
Bit 14
Bit 13
C7
Bit 12
Bit 11
AS1 & AS2_MIN_ATTEN
Bit 7
Bit 6
Bit 5
C8
Bit 4
Bit 3
AS1 & AS2_MIN_ATTEN
Minimum attenuation value will be utilized by the acoustic suppression algorithm.
The maximum value of this field provides an attenuation factor of 1.
The minimum value provides an attenuation factor of 0.
13.4.2
13.4.2.1
Acoustic Side Control Registers
DT_LONG_ACOUSTIC_ATTACK_TC
Address
Access Mode
Value At Reset
Nominal Value
0x14C9
R/W
0x09
0x09
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Revision 1.3
W681307
Bit 7
Bit 6
Bit 5
Bit 4
RESERVED
RESERVED
RESERVED
RESERVED
Bit 3
Bit 2
Bit 1
Bit 0
DT_LONG_ACOUSTIC_ATTACK_TC
Acoustic long term power estimation’s attacking time constant.
This field defines the inertial delay utilized for the long term acoustic power estimation. Raising the value of this field reduces the inertia
and will make the estimation more responsive whilst lowering the field will cause the power estimation algorithm to be less responsive to
bursts of energy on the acoustic.
13.4.2.2
DT_SHORT_ACOUSTIC_ATTACK_TC
Address
Access Mode
Value At Reset
Nominal Value
0x14CA
R/W
0x0B
0x0B
Bit 7
Bit 6
Bit 5
Bit 4
RESERVED
RESERVED
RESERVED
RESERVED
Bit 3
Bit 2
Bit 1
Bit 0
DT_SHORT_ACOUSTIC_ATTACK_TC
Acoustic short term power estimation’s attacking time constant
This field defines the inertial delay utilized for the short term acoustic power estimation. Raising the value of this field reduces the inertia
and will make the estimation more responsive whilst lowering the field will cause the power estimation algorithm to be less responsive to
bursts of energy on the acoustic side.
13.4.2.3
DT_ACOUSTIC_HANGOVER_TIME
Address
Access Mode
Value At Reset
Nominal Value
0x14CB - 0x14CC
R/W
0x0020
0x0340
Bit 15
Bit 14
Bit 13
CB
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
DT_ACOUSTIC_HANGOVER_TIME
Bit 7
Bit 6
Bit 5
CC
Bit 4
Bit 3
DT_ACOUSTIC_HANGOVER_TIME
This field defines the inertial delay of the double talk detection algorithm for acoustic side.
Following the detection of the double talk condition there is a programmable inertial delay (in PCM sample periods 125us) following the
disappearance of the double talk condition. For the duration of this delay period the double talk condition is assumed to remain. If double
talk does not reappear during this window then the echo cancellation unit will revert back to acoustic training mode.
13.4.2.4
Address
Access Mode
Value At Reset
Nominal Value
0x14CD - 0x14CE
R/W
0x0666
0x0040
Bit 15
CD
DT_ ACOUSTIC _DEV_THRESHOLD
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
DT_ ACOUSTIC_DEV_THRESHOLD
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Revision 1.3
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Bit 7
Bit 6
Bit 5
CE
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DT_ ACOUSTIC_DEV_THRESHOLD
This field defines the instantaneous acoustic power change that is deemed to correspond to speech and is used to detect short term
changes in voice level on the acoustic interface.Raising (lowering) this field will raise (lower) the change in acoustic power required for
the detection of speech (and hence the double talk condition).
13.4.2.5
DT_SHORT_ACOUSTIC_THRESHOLD
Address
Access Mode
Value At Reset
Nominal Value
0x14CF - 0x14D0
R/W
0x0404
0x0040
Bit 15
Bit 14
Bit 13
CF
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
DT_SHORT_ ACOUSTIC_THRESHOLD
Bit 7
Bit 6
Bit 5
D0
Bit 4
Bit 3
DT_SHORT_ ACOUSTIC_THRESHOLD
This field defines the power threshold that is deemed to correspond to speech. Raising(lowering) this field will raise (lower) the acoustic
power required for the detection of speech (and hence the double talk condition).
13.4.3
13.4.3.1
Network Side Control Registers
VD_LONG_NETWORK_ATTACK_TC
Address
Access Mode
Value At Reset
Nominal Value
0x14D1
R/W
0x09
0x09
Bit 7
Bit 6
Bit 5
Bit 4
RESERVED
RESERVED
RESERVED
RESERVED
Bit 3
Bit 2
Bit 1
Bit 0
VD_LONG_NETWORK_ATTACK_TC
Network long term power estimation’s attacking time constant
This field defines the inertial delay utilized for the long term network power estimation. Raising the value of this field reduces the inertia
and will make the estimation more responsive whilst lowering the field will cause the power estimation algorithm to be less responsive to
bursts of energy on the network side.
13.4.3.2
VD_SHORT_NETWORK_ATTACK_TC
Address
Access Mode
Value At Reset
Nominal Value
0x14D2
R/W
0x0B
0x0B
Bit 7
Bit 6
Bit 5
Bit 4
RESERVED
RESERVED
RESERVED
RESERVED
Bit 3
Bit 2
Bit 1
Bit 0
VD_SHORT_NETWORK_ATTACK_TC
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Publication Release Date: May, 2007
Revision 1.3
W681307
Network short term power estimation’s attacking time constant
This field defines the inertial delay utilized for the short term network power estimation. Raising the value of this field reduces the inertia
and will make the estimation more responsive whilst lowering the field will cause the power estimation algorithm to be less responsive to
bursts of energy on the network side.
13.4.3.3
VD_NETWORK_HANGOVER_TIME
Address
Access Mode
Value At Reset
Nominal Value
0x14D3 - 0x14D4
R/W
0x0009
0x0340
Bit 15
Bit 14
Bit 13
D3
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
VD_NETWORK_HANGOVER_TIME
Bit 7
Bit 6
Bit 5
D4
Bit 4
Bit 3
VD_NETWORK_HANGOVER_TIME
This field defines the inertial delay of the voice detection algorithm for the network side.
Following the detection of the speech on the network interface there is a programmable inertial delay (in PCM sample periods) following
the disappearance of the speech signal. For the duration of this delay period the speech is assumed to remain. If speech does not reappear
during this window then the echo cancellation unit will revert back to channel training mode.
13.4.3.4
VD_NETWORK_DEV_THRESHOLD
Address
Access Mode
Value At Reset
Nominal Value
0x14D5 - 0x14D6
R/W
0x0666
0x01B0
Bit 15
Bit 14
Bit 13
D5
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
VD_NETWORK_DEV_THRESHOLD
Bit 7
D6
Bit 12
Bit 6
Bit 5
Bit 4
Bit 3
VD_NETWORK_DEV_THRESHOLD
This field defines the instantaneous network power change that is deemed to correspond to speech and is used to detect short term
changes in voice level on the network interface.
Raising (lowering) this field will raise (lower) the change in network power required for the detection of speech.
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Revision 1.3
W681307
13.4.3.5
VD_LONG_NETWROK_THRESHOLD
Address
Access Mode
Value At Reset
Nominal Value
0x14D7 - 0x14D8
R/W
0x0666
0x1050
Bit 15
Bit 14
Bit 13
D7
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
VD_LONG_NETWORK_THRESHOLD
Bit 7
Bit 6
Bit 5
D8
Bit 4
Bit 3
VD_LONG_NETWORK_THRESHOLD
Minimum power level constitutes speech over the network interface, as measured by the long term power estimation algorithm.
13.4.3.6
VD_SHORT_NETWROK_THRESHOLD
Address
Access Mode
Value At Reset
Nominal Value
0x14D9 - 0x14DA
R/W
0x040E
0x03C0
Bit 15
Bit 14
Bit 13
D9
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
VD_SHORT_NETWORK_THRESHOLD
Bit 7
Bit 6
Bit 5
DA
Bit 4
Bit 3
VD_SHORT_NETWORK_THRESHOLD
Minimum power level constitutes speech over the network interface, as measured by the short term power estimation algorithm.
13.4.3.7
VD_CUT_OFF_NETWORK_POWER
Address
Access Mode
Value At Reset
Nominal Value
0x14DB - 0x14DC
R/W
0x0666
0x08A0
Bit 15
Bit 14
Bit 13
DB
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
VD_CUT_OFF_NETWORK_POWER
Bit 7
Bit 6
Bit 5
DC
Bit 4
Bit 3
VD_CUT_OFF_NETWORK_POWER
Configurable bias for network power estimation. This field defines the zero reference for the network power estimation algorithm.
13.4.3.8
Specific Register
Address
Access Mode
Value At Reset
0x14DD
R/W
0x00
Nominal Value
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Revision 1.3
W681307
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Blocked
(for test modes)
Bit 1
Bit 0
13.4.4
ACOUSTIC / NETWORK Active Status
Address
Access Mode
Value At Reset
0x14DE
R
0x00
Bit 7
RESERVED
AcousticActive
NetworkActive
13.4.5
Bit 6
Bit 5
RESERVED
Bit 4
Nominal Value
Bit 3
Bit 2
Blocked
Blocked
Blocked
Blocked
AcousticActive NetworkActive
(for test modes) (for test modes) (for test modes) (for test modes)
= 1, reflect the status of acoustic power
= 1, reflect the status of network power.
AGC Control Registers
13.4.5.1
AGC_THRESHOLD
Address
Access Mode
Value At Reset
Nominal Value
0x14DF - 0x14E0
R/W
0x0800
0x1000
Bit 15
Bit 14
Bit 13
DF
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
AGC_THRESHOLD
Bit 7
Bit 6
Bit 5
E0
Bit 4
Bit 3
AGC_THRESHOLD
The AGC threshold is set the maximum output power from AGC module. The purpose is set properly gain to prevent voice signal
clipping.
13.4.5.2
AGC_NOISE_THRESHOLD
Address
Access Mode
Value At Reset
Nominal Value
0x14E1 - 0x14E2
R/W
0x00C8
0x0100
Bit 15
Bit 14
Bit 13
E1
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
AGC_NOISE_THRESHOLD
Bit 7
E2
Bit 12
Bit 6
Bit 5
Bit 4
Bit 3
AGC_NOISE_THRESHOLD
The calculated input power with time constant AGC_ST_ATTACK_TC is less than the AGC_NOISE_THRESHOLD, then AGC gain is
set to unit gain. It is assumed that the input power is background signal.
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Revision 1.3
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13.4.5.3
AGC_MAX_SG
Address
Access Mode
Value At Reset
Nominal Value
0x14E3
R/W
0x02
0x0A
Bit 7
Bit 6
Bit 5
Bit 4
Reserved
Reserved
Reserved
Reserved
Bit 3
Bit 2
Bit 1
Bit 0
AGC_MAX_SG
The AGC module has maximum gain to amplifier the echo cancelled input signal.
13.4.5.4
Specific Register
Address
Access Mode
Value At Reset
Nominal Value
0x14E4
R/W
0x0F
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Reserved
Reserved
Reserved
Reserved
Bit 3
Bit 2
Bit 1
Bit 0
*Blocked for test modes
*Blocked for test modes. Set the 4 bits to 1.
13.4.5.5
AGC_LG_ATTACK_TC
Address
Access Mode
Value At Reset
Nominal Value
0x14E5
R/W
0x0B
0x33
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
AGC_LG_ATTACK_TC_POS
AGC_LG_ATTACK_TC_NEG
AGC_LG_ATTACK_TC_POS
13.4.5.6
Bit 0
AGC_LG_ATTACK_TC_NEG
The field defines the inertial delay utilized for the long term gain estimation when the AGC gain is
increasing. Raising the value of this field reduces the inertial and will make the estimation more
responsive while lowering the field will cause the gain estimation algorithm to be less responsive to
bursts of gain on the AGC.
The field defines the inertial delay utilized for the long term gain estimation when the AGC gain is
decreasing. Raising the value of this field reduces the inertial and will make the estimation more
responsive while lowering the field will cause the gain estimation algorithm to be less responsive to
bursts of gain on the AGC.
AGC_ST_ATTACK_TC
Address
Access Mode
Value At Reset
Nominal Value
0x14E6
R/W
0x09
0x09
Bit 7
Bit 1
Bit 6
Bit 5
Bit 4
Bit 3
RESERVED
Bit 2
Bit 1
Bit 0
AGC_ST_ATTACK_TC
Attack time for short term AGC power estimation. This field defines the inertial delay utilized for the short term AGC power estimation.
Raising the value of this field reduces the inertial and will make the estimation more responsive while lowering the field will cause the
power estimation algorithm to be less responsive to bursts of energy on the AGC.
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Revision 1.3
W681307
13.4.6
Noise Suppressor Registers
13.4.6.1
NS_STTACK_Tcand_GAIN
Address
Access Mode
Value At Reset
Nominal Value
0x14E7
R/W
0x00
0xB5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
ShortTermNSPowerATTACKTC[7:4]
：
Bit 1
Bit 0
Noise_Suppressor_Index[3:0]
Noise_Suppressor_Index This 4-bit field defines the gain of Noise suppressor
Noise_Suppressor_Index[3:0]
0
1
2
3
4
5
6
7
8
：
Noise Suppressor Level (dB)
-1
-2
-3
-4
-5
-6
-7
-8
-9
Noise_Suppressor_Index[3:0]
9
A
B
C
D
E
F
Noise Suppressor Level (dB)
-10
-11
-12
-13
-14
-15
-16
ShortTermNSPowerATTACKTC
The 4-bit field defines the "Time Constant" to calculate the power of voice that enters the noise suppressor module.
So "Noise Suppressor" can determine if current power of voice is larger than "Noise threshold" or not.
The operation is just like "Short term acoustic power time constant.
13.4.6.2
NS_ATTEN_DW_UP_TC
Address
Access Mode
Value At Reset
Nominal Value
0x14E8
R/W
0x00
0x55
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Noise_fall_TC[4:7]
Bit 1
Bit 0
Noise_rise_TC[0:3]
Noise_rise_TC
This 4-bit field defines the time constant of Noise suppressor gain from the gain specified by
"noise_suppressor_index" to "0dB". Larger value, faster speed.
Noise_fall_TC
This 4-bit field defines the time constant of Noise suppressor gain from "0dB" to the gain specified by
"noise_suppressor_index". Larger value, faster speed.
13.4.6.3
NS_Active_Power_MSB
Address
Access Mode
Value At Reset
Nominal Value
0x14E9
R/W
0x00
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NS_Active_Power_MSB
The most significant byte of noise threshold.
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Revision 1.3
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13.4.6.4
NS_Active_Power_LSB
Address
Access Mode
Value At Reset
Nominal Value
0x14EA
R/W
0x00
0x40
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NS_Active_Power_LSB
The most significant byte of noise threshold.
So "noise_threshold" = {NS_Active_Power_MSB,NS_Active_Power_LSB}
13.4.7
AEC Soft Clip
In order to reduce clipping distortion, a soft clipping function has been implemented in GTx1. A second gain (GTx1_SC) and an overload
threshold point (TH_SC) is programmable. Gain GTx1 is changed to GTx1_SC if the input signal level of the GTx1 gain state is greater
than TH_SC. Note that the input signal power level is estimated in the GTx1 gain stage using the following arithmetic unit
：
(
)
PGTx1 = PGTx1 × 1 − 2 GTx1_ TC −16 + AGTx1 × 2 GTx1_ TC −16
If
(
PGTx1 ≥ TH_SC)
GTx1_ Factor ⇐ GTx1_ SC
Else
GTx1_ Factor ⇐ GTx1
GTx1avg ⇐ (1 − 2 ( GT _ TC −16) ) × GTx1avg + GTx1_ Factor × 2 ( GT _ TC −16)
Arin ⇐ AGTx1 × GTx1avg
PGTx1 ： GTx1 input power with time constant GTx1_TC
GTx1avg ： GTx1 average gain with time constant GT_TC
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Revision 1.3
W681307
Output_ Signal
MAX_ LEVEL
GTx1_SC
GTx1*TH_SC
GTx1
Input_ Signal
TH_SC
MAX_ LEVEL
Figure 13-2 Block diagram of the soft clipping function of GTx1
13.4.7.1
Soft Clip Control
Address
Access Mode
Value At Reset
Nominal Value
0x14EB
R/W
0x00
0x03
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
RESERVED
Reserved
Reserved
DTSC_Enable
VDSC_Enable
Soft_clip control register is used to enable the soft clipping function. There are two bits in this register to control two soft clip blocks
independently.
VDSC_Enable
When set, enable soft clip function for network signal before network signal is sent to AEC module.
When reset, disable soft clip function. So network signal is sent to AEC module directly.
DTSC_Enable
When set, enable soft clip function for acoustic signal after acoustic signal is sent out from AEC module.
When reset, disable soft clip function. So acoustic signal is sent to next stage directly.
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Publication Release Date: May, 2007
Revision 1.3
W681307
13.4.7.2
VD Soft Clip Normal Index
Address
Access Mode
Value At Reset
Nominal Value
0x14EC
R/W
0x00
0x12
Bit 7
Bit 6
Bit 5
RESERVED
RESERVED
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VDSC_Normal_Index[5:0]
：
VDSC_Normal_Index[5:0] is used to control the gain of VD Soft_Clip module at normal mode. The gain selection range is the same as
"Digital Gain Multiplexer" and is reproduced below
VDSC_Normal_Index[5:0]
HEX Value
Gain
VDSC_Normal_Index[5:0]
HEX Value
Gain
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0 dB (default)
0.5 dB
1.0 dB
1.5 dB
2.0 dB
2.5 dB
3.0 dB
3.5 dB
4.0 dB
4.5 dB
5.0 dB
5.5 dB
6.0 dB
6.5 dB
7.0 dB
7.5 dB
8.0 dB
8.5 dB
9.0 dB
9.5 dB
10.0 dB
10.5 dB
11.0 dB
11.5 dB
12.0 dB
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x3F
- 0.5 dB
- 1.0 dB
- 1.5 dB
- 2.0 dB
- 2.5 dB
- 3.0 dB
- 3.5 dB
- 4.0 dB
- 4.5 dB
- 5.0 dB
- 5.5 dB
- 6.0 dB
- 6.5 dB
- 7.0 dB
- 7.5 dB
- 8.0 dB
- 8.5 dB
- 9.0 dB
- 9.5 dB
- 10.0 dB
- 10.5 dB
- 11.0 dB
- 11.5 dB
- 12.0 dB
Mute
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Publication Release Date: May, 2007
Revision 1.3
W681307
13.4.7.3
VD Soft Clip Low Index
Address
Access Mode
Value At Reset
Nominal Value
0x14ED
R/W
0x00
0x06
Bit 7
Bit 6
Bit 5
RESERVED
RESERVED
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VDSC_Low_Index[5:0]
VDSC_Low_Index[5:0] is used to control the gain of vd soft_clip module at low mode. The gain selection range is the same as "VD Soft
Clip Normal Index".
13.4.7.4
VD Soft Clip Threshold
Address
Access Mode
Value At Reset
Nominal Value
0x14EE - 0x14EF
R/W
0x0400
0x4000
Bit 15
Bit 14
Bit 13
Bit 12
EE
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
VDSC_Threshold
Bit 7
Bit 6
Bit 5
Bit 4
EF
Bit 3
VDSC_Threshold
VDSC_Threshold is used to determine the selection of Soft Clip gain. When the input network power is larger then VDSC_Threshold,
VDSC_Low_Index gain is used, otherwise VDSC_Normal_Index gain is used.
13.4.7.5
ShortTermPreNetworkPowerAttackTC
Address
Access Mode
Value At Reset
Nominal Value
0x14F0
R/W
0x07
0x0B
Bit 7
Bit 6
Bit 5
Bit 4
RESERVED
RESERVED
RESERVED
RESERVED
Bit 3
Bit 2
Bit 1
Bit 0
ShortTermPreNetworkPowerAttackTC[3:0]
ShortTermPreNetworkPowerAttackTC[3:0] is the time constant which is used to calculate the short term network power for VD Soft Clip.
13.4.7.6
VDSC Attack TC
Address
Access Mode
Value At Reset
Nominal Value
0x14F1
R/W
0x07
0x05
Bit 7
Bit 6
Bit 5
Bit 4
RESERVED
RESERVED
RESERVED
RESERVED
Bit 3
Bit 2
Bit 1
Bit 0
VDSC_AttackTC[3:0]
When soft clip gain is switched between normal and low, an embedded smoothing function is used to smooth the gain change.
VDSC_AttackTC[3:0] is a time constant to control the smoothing speed.
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Publication Release Date: May, 2007
Revision 1.3
W681307
13.4.7.7
DT Soft Clip Normal Index
Address
Access Mode
Value At Reset
Nominal Value
0x14F2
R/W
0x00
0x18
Bit 7
Bit 6
Bit 5
RESERVED
RESERVED
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DTSC_Normal_Index[5:0]
DTSC_Normal_Index[5:0] is used to control the gain of DT Soft Clip module at normal mode. The gain selection range is the same as
"VDSC_Normal_Index".
13.4.7.8
DT Soft Clip Low Index
Address
Access Mode
Value At Reset
Nominal Value
0x14F3
R/W
0x00
0x0C
Bit 7
Bit 6
Bit 5
RESERVED
RESERVED
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DTSC_Low_Index[5:0]
DTSC_Low_Index[5:0] is used to control the gain of DT Soft_Clip module at low mode. The gain selection range is the same as "VDSC_
Normal_Index".
13.4.7.9
DT Soft Clip Threshold
Address
Access Mode
Value At Reset
Nominal Value
0x14F4 - 0x14F5
R/W
0x0400
0x1140
Bit 15
Bit 14
Bit 13
F4
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
DTSC_Threshold
Bit 7
F5
Bit 12
Bit 6
Bit 5
Bit 4
Bit 3
DT_SC_Threshold
DTSC_Threshold is used to determine the selection of Soft Clip gain. When the output acoustic power is larger then DTSC_Threshold,
DTSC_Low_Index gain is used, otherwise DTSC_Normal_Index gain is used.
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Publication Release Date: May, 2007
Revision 1.3
W681307
13.4.7.10
ShortTermPostAcousticPowerAttackTC
Address
Access Mode
Value At Reset
Nominal Value
0x14F6
R/W
0x07
0x0B
Bit 7
Bit 6
Bit 5
Bit 4
RESERVED
RESERVED
RESERVED
RESERVED
Bit 3
Bit 2
Bit 1
Bit 0
ShortTermPostAcousticPowerAttackTC[3:0]
ShortTermPostAcousticPowerAttackTC[3:0] is the time constant which is used to calculate the short term acoustic power for DT Soft Clip.
13.4.7.11
DTSC Attack TC
Address
Access Mode
Value At Reset
Nominal Value
0x14F7
R/W
0x07
0x05
Bit 7
Bit 6
Bit 5
Bit 4
RESERVED
RESERVED
RESERVED
RESERVED
Bit 3
Bit 2
Bit 1
Bit 0
DTSC_AttackTC[3:0]
When soft clip gain is switched between normal and low, an embedded smoothing function is used to smooth the gain change.
DTSC_AttackTC[3:0] is a time constant to control the smoothing speed.
Acoustic Side / Network Side Power Measurement
13.5
13.5.1
ACOUSTIC_SHORT_TERM_POWER
Address
Access Mode
Value At Reset
0x15C0- 0x15C1
R
0x0000
Bit 15
Bit 14
Bit 13
C0
Bit 12
Nominal Value
Bit 11
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 9
Bit 8
ACOUSTIC_SHORT_TERM_POWER
Bit 7
Bit 6
Bit 5
C1
Bit 4
Bit 3
ACOUSTIC__SHORT_TERM_POWER
Short Term Acoustic Power calculated by the double talk detector (DT).
13.5.2
ACOUSTIC_LONG_TERM_POWER
Address
Access Mode
Value At Reset
0x15C2- 0x15C3
R
0x0000
Bit 15
Bit 14
Bit 13
Bit 12
Nominal Value
Bit 11
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Bit 10
Publication Release Date: May, 2007
Revision 1.3
W681307
C2
ACOUSTIC_LONG_TERM_POWER
Bit 7
Bit 6
Bit 5
Bit 4
C3
Bit 3
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 1
Bit 0
ACOUSTIC_LONG_TERM_POWER
Long Term Power on acoustic side estimated by the double talk detector (DT).
13.5.3
ACOUSTIC_POWER_DEVIATION
Address
Access Mode
Value At Reset
0x15C4- 0x15C5
R
0x0000
Bit 15
Bit 14
Bit 13
Bit 12
C4
Nominal Value
Bit 11
ACOUSTIC_POWER_DEVIATION
Bit 7
Bit 6
Bit 5
Bit 4
C5
Bit 3
ACOUSTIC_POWER_DEVIATION
Acoustic Power Deviation estimated by the double talk detector (DT).
13.5.4
Address
Access Mode
Value At Reset
0x15C6
R
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Bit[1]
Bit[0]
= 1, reflect the status of acoustic power.
= 1, reflect the status of network power.
13.5.5
NETWORK_SHORT_TERM_POWER
Address
Access Mode
Value At Reset
0x15C8 - 0x15C9
R
0x0000
Bit 15
C8
ACOUSTIC / NETWORK Active Status
Bit 14
Bit 13
Bit 12
AcousticActive NetworkActive
Nominal Value
Bit 11
Bit 10
Bit 9
Bit 8
NETWORK_SHORT_TERM_POWER
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Publication Release Date: May, 2007
Revision 1.3
W681307
Bit 7
Bit 6
Bit 5
C9
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
Bit 1
Bit 0
NETWORK_SHORT_TERM_POWER
Network Short Term Power calculated by VD modules.
13.5.6
NETWORK_LONG_TERM_POWER
Address
Access Mode
Value At Reset
0x15CA- 0x15CB
R
0x0000
Bit 15
Bit 14
Bit 13
CA
Nominal Value
Bit 12
Bit 11
NETWORK_LONG_TERM_POWER
Bit 7
Bit 6
Bit 5
CB
Bit 4
Bit 3
NETWORK_LONG_TERM_POWER
Network Long Term Power calculated by VD modules.
13.5.7
NETWORK_POWER_DEVIATION
Address
Access Mode
Value At Reset
0x15CC- 0x15CD
R
0x0000
Bit 15
Bit 14
Bit 13
CC
Nominal Value
Bit 12
Bit 11
NETWORK_POWER_DEVIATION
Bit 7
Bit 6
Bit 5
CD
Bit 4
Bit 3
NETWORK_POWER_DEVIATION
Network Power Deviation estimated by the voice detector (VD).
13.5.8
ACOUSTIC / NETWORK Active Status
Address
Access Mode
Value At Reset
0x15CE
R
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Bit[1]
Bit[0]
AcousticActive NetworkActive
= 1, reflect the status of acoustic power.
= 1, reflect the status of network power.
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Publication Release Date: May, 2007
Revision 1.3
W681307
14. SYSTEM FUNCTION
14.1
Power On Reset
The power on reset (POR) block generates a internal reset signal to reset the whole chip after connecting the power supply voltage the
chip. The power on reset circuit responds to the voltage difference applied between AVDD and AGND. Figure 14-1 shows the power
reset circuit.
When AVDD is rising slowly starting from zero to the signal PowerOnResetN will be low until AVDD passed the power-on voltage level
Von. After a delay time (about 37ms for 13.824MHz clock) Reset_out goes high and the actual reset sequence starts. If AVDD does not
pass Von voltage, then the PowerOnResetN stays low, causing the oscillator to run and having most of the digital logic circuits being in
an active reset mode. If AVDD sinks below the power-off voltage level Voff, PowerOnRestN will become low again. The hysteresis
voltage between Von and Voff is need to overcome a “reset oscillation” phenomenon that otherwise might occur if AVDD decrease due
to the activity during the reset sequence.
Figure 144-1 Analog part of the power on Reset function.
14.1.1
CODEC On/Off Scheme
Address
Access Mode
Value At Reset
0x1500
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
RESERVED
RESERVED
RESERVED
RESERVED
Bit 3
Bit 2
PeriodSelection
Bit 1
Bit 0
Codec on/off
CODECOnOff
scheme Enable
CODECOnOff_scheme_Enable
Set “1” to enable hardwired CODEC On/Off scheme.
Set “0” to use independent On/Off control from 0x1509.
CODEC On/Off
Set“1” to turn on CODEC.
Set “0” to turn off CODEC.
PeriodSelection
Set to select the duration length between CODEC_digital_on/off and
CODEC_analog_on/off.
Bit[3:2]
2’b00
2’b01
2’b10
2’b11
Period
2 mS
4 mS
8 mS
16 mS
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Publication Release Date: May, 2007
Revision 1.3
W681307
14.1.2
CODEC Digital Part
Address
Access Mode
Value At Reset
Nominal Value
0x1501
R/W
0x80
90
Bit 7
Bit 6
ABF_MODE
Bit 5
DAC_Dither_Level[1:0]
Bit 4
DAC_Dither
_Enable
Bit 3
Bit 2
ADC_ABF_Length[1:0]
Bit 1
Bit 0
CODEC_FIFO_ CODEC_FIFO_
PTR_Reset
Reset
CODEC_FIFO_Reset
CODEC_FIFO_PTR_Reset
ADC_ABF_Length[1:0]
When set, Clear CODEC FIFO content after each 8K operation.
When set, Reset CODEC FIFO pointer after each 8K operation.
Select the limit cycle length to do adaptive bit flipping (ABF) algorithm.
ABF_L[1:0]
Limit cycle Length
0
4
1
6
2
8
3
10
DAC_Dither_Enable
DAC_Dither_Level[1:0]
When set, enable the dither input in DAC path
Select the dither level in the DAC path.
DA_Dither_Level[1:0]
Dither Level
0
17 bit
1
15 bit
2
16 bit
3
18 bit
ABF_MODE
When set, select adaptive bit flipping algorithm (ABF) mode in the analog CODEC modulator.
14.2
ADC Adaptive Bit Flip Probability
Address
Access Mode
Value At Reset
Nominal Value
0x1502
R/W
0xFF
80
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADC_ABF_PROB
This byte set the adaptive bit flip probability of the ADC path in the CODEC modulator. When set ADC_ABF_PROB to 0xFF will
disable the adaptive bit-flipping algorithm, and set to 0x00 means always enable the adaptive bit-flipping algorithm if the limit cycle
length condition is detected.
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Publication Release Date: May, 2007
Revision 1.3
W681307
14.3
Sounder Signal Selection
Address
Access Mode
Value At Reset
0x1503
R/W
0x00
Bit 7
Bit 6
Bit 5
Blocked
(for test modes)
RESERVED
Rclk_SNDR_SE
L
Bit 4
Nominal Value
Bit 3
RefClkSel
Bit 2
Bit 1
Bit 0
RefClkOn
PDMEN
SNDRSigSel
There are two sounders signal to be selected to connect to SNDR pin. This subsection describes the sounder signal of PDM (Pulse Density
Modulation) format. The selection of different sounder signal and the related control bits are shown in 0x1503[1:0].
PDMEN
When set, the TX path of CODEC will be hardware muted, the over sampled DTMF signal is switched to
sounder signal path. So except to generate sounder signal, this bit should be reset to 0 while CODEC is
active.
SNDRSigSel
When set, the sounder signal comes from the DTMF generator in the speech processor. The DTMF signal
will be over sampled to 1 bit signal, which is called Pulse Density Modulation (PDM) format. The PDM
format signal then connects to pin SNDR while PDMRingEN=1. The control registers of DTMF generator
are allocated from addresses 1488H~148CH
=0, the sounder signal comes from the Ringer Tone Generator with Pulse Width Modulation (PWM) format.
The control registers of Ringer Tone Generator are allocated from addresses 1447H~144AH
RefClkOn
When set, enable Reference Clock Generation circuit.
RefClkSel
Reference clock rate selection.
RefClkSel[4:3]
0
1
2
3
Rclk_SNDR_Sel
Reference Clk Rate
13.824 MHz
6.912 MHz
3.456 MHz
1.728 MHz
Switch the function of pin SNDR. Set “1” to configure the SNDR pin as RefClock output.
Set ”0” to configure the SNDR pin as SNDR output.
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Publication Release Date: May, 2007
Revision 1.3
W681307
CODECAPd
0x1509[6]
ADown
CODEC
Analog
Half
AEC
CODEC
Digital
SWC_in
0
1
0x1485
PCM
Format
0x14C1
Tone
Geneator
Linear
PCM
0x1488-0x148C
DAout
0x1486
0x1484
PDMEN
0x1503[1]
PDM
1
0
SNDR
PWM
SNDRSigSel
0x 1503[0]
Ringer
Tone
Generation
(dd209_rt)
Figure 14-2 Sounder signal selection circuit
SNDR_in
negedge clk control logic
control
RefClkSel[1:0]
RefClkOn
On
system clock
00
Rclk_SNDR_Sel
cnt
0
01
10
11
0
1
Muxed_SNDR
1
counter to 7
2
Figure 14-3 Reference clock frequency rate and function selection circuit.
14.4
Frequency Adjustment of Crystal Oscillator
A 13.824 MHz crystal is connected to pin XTAL1 and XTAL2. But the accuracy of the system clock will affect the performance and
power saving capability of a handset operating in suspend mode. The frequency deviation resulted from the variation of crystal device and
external load capacitances can be adjusted by the on-chip capacitances.
FACO (Frequency Adjustment of Crystal Oscillator) controls the connection of on-chip capacitance Cg and Cd to the crystal oscillator
pins XTAL1 and XTAL2 respectively. The total maximum value is 11.9pF per pin. Therefore this register can control the frequency of
the crystal oscillator at 13.824 MHz. accurately.
FACO
Address
Access Mode
Value At Reset
0x1504
R/W
0x00
Nominal Value
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Publication Release Date: May, 2007
Revision 1.3
W681307
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 1
Bit 0
FACO
FACO[Bit 7]
FACO[Bit 6]
FACO[Bit 5]
FACO[Bit 4]
FACO[Bit 3]
FACO[Bit 2]
FACO[Bit 1]
FACO[Bit 0]
14.5
When set, add an 8 pF to Cg and Cd each.
When set, add an 4 pF to Cg and Cd each.
When set, add an 2 pF to Cg and Cd each.
When set, add an 1 pF to Cg and Cd each.
When set, add an 0.5 pF to Cg and Cd each.
When set, add an 0.25 pF to Cg and Cd each.
When set, add an 0.125 pF to Cg and Cd each.
When set, add an 0.0625 pF to Cg and Cd each.
Specific Register
Address
Access Mode
Value At Reset
0x1505
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
RESERVED
RESERVED
RESERVED
RESERVED
14.6
Nominal Value
Bit 3
Bit 2
Blocked
Blocked
Blocked
Blocked
(for test modes) (for test modes) (for test modes) (for test modes)
VAG Selection
Address
Access Mode
Value At Reset
0x1506
R/W
0x00
Bit 7
Bit 6
Bit 5
Vc_vag [2:0]
Nominal Value
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
VAG default voltage is 1.5V. And the VAG level can be programmed by software with following table.
Vc_vag [2:0]
Default
VAG (V)
Bin
Hex
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
1.50
1.57
1.67
1.80
2.00
2.33
1.50
1.50
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Publication Release Date: May, 2007
Revision 1.3
W681307
14.7
TG Gain Register
Address
Access Mode
Value At Reset
0x1507
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
TG_A Gain[2]
TG_A Gain[1]
TG_A Gain[0]
Reserved
TG_B Gain[2]
TG_B Gain[1]
TG_B Gain[0]
TG Op amp of the Codec is implemented as a two amplifiers cascade to provide the necessary gain for low signal microphone input. The
first stage (TG_A) is designed as a full differential high impendence and low noise amplifier. This amplifier gain can be set as bypass or
maximum gain 18dB for microphone input. The second stage (TG_B) is also full differential amplifier and provides maximum gain 24dB
for the application requirement. It is according this register to set different gain in the Codec, equivalent architecture is shown in Figure
14-4. The TG amplifier gain table is listed as below
：
TG_A Gain[2:0]
Bin
Hex
0000
0
0001
1
0010
2
0011
3
0100
4
0101
5
0110
6
0111
7
Gain [dB]
0 dB
6 dB
12 dB
18 dB
Bypass
Bypass
Bypass
Bypass
TG_B Gain[2:0]
Bin
Hex
0000
0
0001
1
0010
2
0011
3
0100
4
0101
5
0110
6
0111
7
Gain [dB]
0 dB
6 dB
12 dB
18 dB
24 dB
24 dB
24 dB
24 dB
0x1521[0] , 0x1507[6]
0x1521[0]
TI1TI2TI1+
TI2+
15K
0
15K
1
15K
0
15K
1
15K ,30K , 60K,
120K
TI1-
15K
TI2-
15K
15K ,30K , 60K,
120K, 240K
TG+
15K
MUX
1st TG
2nd TG
15K
15K ,30K , 60K,
120K
TI1+
15K
TI2+
15K
TG15K ,30K , 60K,
120K, 240K
Figure 14-4 Equivalent schematics for TG Op amp.
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Publication Release Date: May, 2007
Revision 1.3
W681307
14.8
PO Gain Register
Address
Access Mode
Value At Reset
0x1508
R/W
0x88
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PO2_PD
PO2Gain [2]
PO2Gain [1]
PO2Gain [0]
PO1_PD
PO1Gain [2]
PO1Gain [1]
PO1Gain [0]
The gains of PO1 and PO2 op amp are set according to this register value. The maximum driving capability of PO1 is 120Ω and PO2 is
16Ω. The PO1 and PO2 can be power down by the corresponding control bits of PO Gain register.
Note that the PO op amps can be also power down by the CODEC_CTRL register (0x1509).
The PO amplifier gain table is listed as below.
PO1 Gain [3:0]
Bin
Hex
0000
0
0001
1
0010
2
0011
3
0100
4
0101
5
0110
6
0111
7
1xxx
Gain [dB]
0 dB
2 dB
4 dB
6 dB
8 dB
10 dB
-2 dB
-4 dB
Disable
PO2 Gain [7:4]
Bin
Hex
0000
0
0001
1
0010
2
0011
3
0100
4
0101
5
0110
6
0111
7
1xxx
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Gain [dB]
0 dB
2 dB
4 dB
6 dB
8 dB
10 dB
-2 dB
-4 dB
Disable
Publication Release Date: May, 2007
Revision 1.3
W681307
The equivalent resistance is shown in Figure 14-5.
PO1_PD
0x1508 B[3]
15K
PO1+
PO 1
PO 115K
r
PO2_PD
0x1508 B[7]
15K
PO2+
PO 2
PO215K
r
Unit
Gain RO
Figure 14-5 Equivalent schematics for PO op amp
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Publication Release Date: May, 2007
Revision 1.3
W681307
14.9
14.9.1
The PCM CODEC
Block Diagram
Figure 14-6 shows the block diagram of the speech CODEC-filter.
Figure 14-6 The block diagram of the PCM CODEC-Filter
14.9.2
Analog Interface and Signal Path
The built in linear 14-bit PCM CODEC-filter uses Σ∆ technology. There are two paths in the block, a transmit path and a receive path.
14.9.2.1
Transmit Path in Σ∆ CODEC-Filter
An analog signal input, from a microphone interface, is passed to three terminal operational amplifiers (TI+, TI-, TG) driving a typical 2
KΩ load externally to amplify the input analog signal. The modulator block over samples the analog signal at 1.536 MHz with one bit
resolution. The next anti-aliasing decimation filter reduces the sampling frequency from 1.536 MHz (1 bit) to 32 KHz (15 bit). Digital biquad filters perform the decimation from 32K to 8 KHz and CCITT low-pass filtering at 3400 Hz. The digital HPF block performs the
high-pass filtering at 300 Hz. In the final step, the 14 bit A/D conversed data is sent by the transmit path to the DSP engine for further
signal processing.
14.9.2.2
Receive Path in Σ∆ CODEC-Filter
A 14-bit linear digital signal from the DSP engine is first passed to the digital anti-aliasing interpolation filter block. The interpolation
block performs the reverse operation of the decimation filter (described above in the transmit path) and the sampling rate will be increased
from 8 KHz (14 bits) to 1.536 MHz (14 bits). The digital demodulator will then reduce the 14-bit samples (1.024 MHz) to 1 bit (1.536
MHz). The digital output signal will be passed to a 3400 Hz switched capacitor low-pass filter with sin(x)/x correction and an analog
smoothing filter to reduce the spectral components of the switched capacitor filter. Finally, the analog output signal is sent to the unit gain
power amplifier RO, which is capable of driving a 2 KΩ load connected to the VAG pin.
The last stage of the received path is a pair of power driver PO1- (PO2-) and PO1+ (PO2+) which is connected in a push-pull (differential)
configuration. The PO driver can accommodate large gain ranges by adjusting two external resistors for applications such as driving a
handset receiver (or a speaker). This differential circuit is capable of driving a 120 Ω (16Ω) load.
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Publication Release Date: May, 2007
Revision 1.3
W681307
14.9.3
Control Register: CODEC_CTRL
The functional description and read/write status of each bit are illustrated in this section. The read or write status of each bit is indicated
by the symbol R or W described in Table 14-1.
SYMBOL
R/W
TYPE
Read/Write
MEANING
Data may be read or written by micro-processor.
Table 14-1: Read/Write status description in control register
Address
Access Mode
Value At Reset
0x1509
R/W
0xC0
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CODEC
DigDis
CODECAPd
Reserved
Reserved
Analog
Loopback
Reserved
Reserved
Reserved
CODECDigDis [Bit7]:
CODECAPd [Bit6]:
Analog Loopback [Bit 3]:
=1,
Disable the CODEC digital part,
=0,
Enable the CODEC digital part.
=1,
To disabled the CODEC analog part to save power. Especially when using the PDM
mode sounder signal, only the CODEC digital filter is necessary.
=0,
CODEC analog part enabled.
Setting this bit causes an analog loopback from the receive path to the transmit path.
Internally the RO output in the receive path is routed to the transmit gain control in the
transmit path; the op-amp TG is bypassed. This feature is useful for self-testing to neglect
the external connecting circuit, shown in Figure 14-7.
.
=1,
Figure 14-7 The signal flow of Analog Lookback
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Publication Release Date: May, 2007
Revision 1.3
W681307
14.9.4
Specific Register
Address
Access Mode
Value At Reset
0x150A
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
Blocked (for test modes)
14.9.5
Specific Register
Address
Access Mode
Value At Reset
0x150B
R/W
0x00
Bit 7
Bit 6
Blocked
(for test modes)
14.10
Bit 5
RESERVED
Nominal Value
Bit 4
RESERVED
RESERVED
Bit 3
Bit 2
Bit 1
Bit 0
Blocked
Blocked
Blocked
Blocked
(for test modes) (for test modes) (for test modes) (for test modes)
RECEIVE_DIAG
Address
Access Mode
Value At Reset
0x150C
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
P3.5_A1
_Sel
P3.4_A0
_Sel
CS3_Enable
P1.4_WaitState_Sel
P1.5_Sel
P1.6_Sel[1]
P1.6_Sel[0]
B[1:0]
B[2]
B[3]
B[4]
B[5]
B[6]
P1.6_Sel[1:0]=
P1.5_Sel=
P1.4_waitstate_sel=
CS3_Enable=
P3.4_A0_Sel=
P3.5_A1_Sel=
0,
Pin 44= P1.6
Port 1 Bit 6 of embedded T8032.
1,
Pin 44= X
Undefined. signal.
2,
Pin 44= X
Undefined. signal.
3,
Pin 44= P1.6
Port 1 Bit 6 of embedded T8032.
0
Pin 45= P1.5 or /CS3
Port 1 Bit 5 of embedded T8032 or External chip select.
1
Pin 45= X
Undefined. signal
0,
Pin 46= P1.4
Port 1 Bit 4 of embedded T8032.
1,
Pin 46= wait state input
The input pin with pull-high can receive wait signal from
external device.
0
Pin 45= P1.5
Port 1 Bit 5 of embedded T8032.
1
Pin 45= /CS3
External chip select.
0,
Pin37= P3.4
Port 3 Bit 4 of embedded T8032.
1,
Pin37= A0
A0 address of embedded T8032.
0,
Pin36= P3.5
Port 3 Bit 5 of embedded T8032.
1,
Pin36= A1
A1 address of embedded T8032.
※ If KR is used as GPIO function besides setting SPI_Enable 0x1720 [7] = 0 (disable SPI), 0x150C [7] must be set “0”.
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Publication Release Date: May, 2007
Revision 1.3
W681307
The usages of pin44 and pin45 are illustrated in Figure 14-8.
P1.5_ Sel [B2]
( 0x150C [B2] )
CS3_Enable [B4]
( 0x150C [B4] )
/CS3
SPI_ ENB
X
1
0
1
0
3
X
2
X
1
P1.6
0
1
SDI
(DF_SPI)
P1.6_ Sel [1:0]
( 0x150C [1:0] )
P1.6
P1.5/ MOSI / SDI / /CS3
MOSI
( SPI Master Output ;
Slave Input)
0
P1.5
SPI_ ENB
DF_ ENB
0
0
MISO
( SPI Master Input ;
Slave Output )
Figure 14-8
1
SDO
(DF_SPI)
1
P1.6/MISO / SDO
The Multiplexers of pin44 and pin45
The usages of pin36 and pin37 are illustrated in Figure 14-9.
P3.4_A0_Sel
150C[5]
P3.4
A0
0
1
X
UART_RXD1
SIM_CLK
P3.5_A1_Sel
150C[6]
P3.5
UART_EN &
SIM_EN
1554[7-6]
00
01
10
11
P3.4/ A0/
RXD1/SIM_CLK
UART_EN
1554[7]
0
0
A1
1
P3.5/ A1/ TXD1
UART_TXD1
1
Figure 14-9 The Multiplexers of pin36 and pin37
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Publication Release Date: May, 2007
Revision 1.3
W681307
14.11
Specific Register
Address
Access Mode
Value At Reset
0x150D
R/W
0x19
Bit 7
Bit 6
RESERVED
RESERVED
14.12
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
Blocked
Blocked
Blocked
Blocked
Blocked
Blocked
(for test modes) (for test modes) (for test modes) (for test modes) (for test modes) (for test modes)
EnAllClock
Address
Access Mode
Value At Reset
0x150E
R/W
0x00
Bit 7
Bit 6
SpeedUp32K
Bit 5
RESERVED
EnAllClock
Read Mask ROM Enable
8032 clk output selection
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
Dump mask
Rom
8032 clk output
selection
Read MASK
ROM Enable
EnAllClock
when set, most of the clocks will be enabled.
when set, enable read_access for MASK ROM
when set, P1.4 will output system clock used by on chip TB8032. If chip is configured as double system
clock speed, it output the x2 system clock.
when set, enable MASK ROM test mode.
when set, 32k clock will replace with 13.824 system clock for speed up testing.
Dump mask Rom
SpeedUp32K
14.13
RESERVED
Nominal Value
CODEC_Test_Sel
Address
Access Mode
Value At Reset
0x150F
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
codec_test
_sel[7]
codec_test
_sel[6]
codec_test
_sel[5]
codec_test
_sel[4]
codec_test
_sel[3]
codec_test
_sel[2]
codec_test
_sel[1]
codec_test
_sel[0]
Codec_test-sel[3:0]
=0001, loopback DA output.
=0010, loopback AD output.
=0011, assign DA output to “0”.
=0100, loopback DA input.
=0101, test ALU function.
=0110, set value to internal register D2.
=0111, calculate checksum of code ROM.
=1000, calculate checksum of coefficient ROM.
=1001, route external input (pDR) to AD input.
=1010, output code ROM content.
=1011, output coefficient ROM content.
Codec_test-sel[7:4]
=0001, 1-bit AD input.
=0010, ADC FIFO pointer.
=0011, ADC 1st -stage SINC filter output.
=0100, ADC 2nd –stage SINC filter output.
=0101, ADC LPF output.
=0110, ADC HPF output.
=0111, ADC output.
=1000, DAC input.
=1001, DAC 1st –stage SINC filter output.
=1010, DAC LPF output
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Revision 1.3
W681307
=1011, DAC 2nd –stage SINC filter output.
=1100, 1-bit DA output.
=1101, DAC FIFO pointer.
14.14
Test_SYSCLKOUT
Address
Access Mode
Value At Reset
0x1510
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 0
Test_SYSCLKO
Blocked
UT
(for test modes)
When set, the SYSCLKOUT signal switches to pin RESET_OUT.
Test_SYSCLKOUT
14.15
Bit 1
BGP_LPF_EN
Address
Access Mode
Value At Reset
0x1511
R/W
0x00
Bit 7
Bit 6
BGP_LPF_EN
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Blocked
Blocked
Blocked
Blocked
(for test modes) (for test modes) (for test modes) (for test modes)
Blocked (for test modes)
BGP_LPF_EN
Nominal Value
When set, the switch is open and bandgap low pass filter is enabled.
When reset, the switch is close and bandgap low pass filter is disabled.
Reset: SW Close
Set: SW Open
Supply Power: VBAT
BGAP
BGP_LPF_EN
Bandgap
Generator
500K ohm
14.16
CODEC Status Indicator
Address
Access Mode
Value At Reset
0x1512
R
0x00
Bit 7
RESERVED
Nominal Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
ADC_FIFO
_Overflow
ADC_FIFO
_Underflow
DAC_FIFO
_Overflow
DAC_FIFO
_Underflow
ADC_SINC
_Overflow
ADC_SINC
_Underflow
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Publication Release Date: May, 2007
Revision 1.3
W681307
ADC_FIFO_OverflowFIFO pointer overflow in the ADC path.
ADC_FIFO_underflowFIFO pointer underflow in the ADC path.
DAC_FIFO_OverflowFIFO pointer overflow in the DAC path.
DAC_FIFO_underflowFIFO pointer underflow in the DAC path.
ADC_SINC_OverflowOverflow indication for ADC SINC filter.
ADC_SINC_UnderflowUnderflow indication for ADC SINC filter.
14.17
BandGap Voltage Adjustment
Address
Access Mode
Value At Reset
0x1513
R/W
0x00
Bit 7
Bit 6
Bit 5
Reserved
Reserved
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
Vbgp_trimming[5:0]
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80mV
40mV
20mV
10mV
5mV
±
Bandgap voltage is default 1V. You can fine tune bandgap voltage follow below formula.
When set Vbgp_trimming[5] = 1, BandGap Voltage = 1V 5mV * Vbgp_trimming[4:0]
When set Vbgp_trimming[5] = 0, BandGap Voltage = 1V 5mV * Vbgp_trimming[4:0]
Where Vbgp_trimming [4:0] is a decimal value and ranges from 0 to 31
－
＋
14.18
Specific Register
Address
Access Mode
Value At Reset
0x1514
R/W
0x00
Bit 7
Bit 6
Blocked
(for test modes)
14.19
Bit 5
Nominal Value
Bit 4
Bit 3
Bit 2
Blocked
(for test modes)
Blocked (for test modes)
Bit 1
Bit 0
Blocked (for test modes)
Linear Regulator Voltage Controller Register
Address
Access Mode
Value At Reset
0x1515
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
RESERVED RESERVED RESERVED RESERVED
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
REG_LV[1]
REG_LV[0]
RESERVED
RESERVED
The output voltage of the embedded linear regulator (REG) is correlated to the internal bandgap voltage. Any tolerance and deviation of
the bandgap voltage will cause a deviation of the output voltage of the embedded linear regulator. In order to ease the usage, the
adjustment possibilities of output voltage of the linear regulator have been built in to compensate the bandgap variation in process.
REG_LV[1:0]
REG_LV [1:0]
00
01
10
11
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REG Output Voltage
3.0V
3.1V
3.2V
3.3V
Publication Release Date: May, 2007
Revision 1.3
W681307
14.20
Core PWR_Det
Address
Access Mode
Value At Reset
0x1518
R
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RESERVED
RESERVED
RESERVED
CPWR_Det
RESERVED
RESERVED
CPWR_Det
14.21
Bit 1
Bit 0
Blocked
Blocked
(for test modes) (for test modes)
This bit is for core power voltage monitor purpose and read only. When the core power voltage is below 1.7V, this bit
will set to low. If the core power voltage is above 1.8V, this bit will set to high. Normally, the core power voltage is
1.9V. This core power voltage monitor function can generate the interrupt and locate at 0x144D[5] register.
DA High Pass Filter Selection
Address
Access Mode
Value At Reset
0x151A
R/W
0x00
Bit 7
Bit 6
Disable HPF DA_dither_select
Disable HPF
DA_ditehr_select
Nominal Value
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
when set, disable the High Pass filter D to A directory
when set, change D to A dither function is add level (no sign)
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Publication Release Date: May, 2007
Revision 1.3
W681307
14.22
TI Path Selection
There is a multiplexer at the input stage to choose which the receiving signal comes from
Address
Access Mode
Value At Reset
0x1521
R/W
0x00
Bit 7
RESERVED
Path_SEL
TI2_Buffer_SEL
TI2NtoPO1
TI2NtoPO2
Bit 6
RESERVED
Bit 5
TI2NtoPO2
Bit 4
TI2NtoPO1
Nominal Value
Bit 3
RESERVED
Bit 2
Bit 1
Bit 0
TI2_Buffer_SEL
Blocked
(for test modes)
Path_SEL
When set, the signal is come from TI1- and TI1+ terminal to internal TG OP Amp
When reset, the signal is come from TI2- and TI2+ terminal to internal TG OP Amp
When set this bit, the TI2 input will provide high input impedance to meet application requirement.
When set, the signal TI2N will be connected to internal PO1 Amp.
When reset, the signal TI2N will be disconnected to internal PO1 Amp.
When set, the signal TI2N will be connected to internal PO2 Amp.
When reset, the signal TI2N will be disconnected to internal PO2 Amp.
The multiplexers of the TI Path Selection are shown in Figure 14-10.
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Revision 1.3
W681307
Figure 14-10 The multiplexers of the TI Path Selection
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Revision 1.3
W681307
15. SERIAL PERIPHERAL INTERFACE
15.1
Serial Peripheral Interface – SPI signals
•
•
•
•
SCK: Input pin in slave mode; output pin in master mode. Serial Clock from Master. Max clock rate is TBD MHz
(depends on how fast the CPU to read a word of received data).
/SPI_CS: Input pin in slave mode; output pin in master mode. Low active Chip Select signal from Master.
MISO: Output pin in slave mode; input pin in master mode. Slave data out to the input of Master.
MOSI: Input pin in slave mode; output pin in master mode. Master data out to the input of Slave.
If the phase of the clock is zero, i.e. CPHA = 0, data is latched at the rising edge of the clock with CPOL = 0, and at the falling edge of
the clock with CPOL = 1. If CPHA = 1, the polarities are reversed. CPOL = 0 means falling edge, CPOL = 1 rising edge. The
transmission clock edges are the reversed of sampling edges, shown in Figure 15-1. Timing diagram of CPHA = 0 and CPHA = 1 is
shown in Figure 15-2 and Figure 15-3.
Figure 15-1 Sampling edges of different modes
Figure 15-2 Timing diagram of CPHA = 0 ( SS is the pin /SPI_CS)
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Revision 1.3
W681307
Figure 15-3
15.1.1
Timing Diagram of CPHA = 1 ( SS is the pin /SPI_CS)
SPI_Control 0
Address
Access Mode
Value At Reset
0x1720
R/W
00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPI_Enable
SPI_Master_Mo
de
Reserved
Reserved
DumpComp
Reserved
CPHA
CPOL
SPI_Enable
Spi_master_mode
CPOL
CPHA
DumBcomp
15.1.2
SPI interface enable. If SPI_ENB=0, the SPI is disabled and pins defined as original functions. Default to 0.
set to 1 in master mode. Default to slave mode
Clock polarity, if CPOL=0, clock is active high; if CPOL=1, clock is active low. Default to 0.
Clock Phase, determined the sampling clock edge of SCLK. Default to 0.
When this bit is on and the received byte is the same as Dumpbyte (0x1724), then no write to RX fifo.
SPI mode 0 = 0x80; SPI mode 1 = 0x82; SPI mode 2 = 0x81; SPI mode 3 = 0x83;
Note: 0x1720[1:0] = ‘10’ is mode 1 in figure 1; 0x1720[1:0] = ‘01’ is mode 2 in figure 1.
SPI_Control 1
Address
Access Mode
Value At Reset
0x1721
R/W
00
Bit 7
Bit 6
SPI_Clock
Bit 5
Bit 4
Reserved
Reserved
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
RxDepth_intr[3:0]
Set master spi clock speed. (Master mode only)
00
1.152MHz
01
576KHz
10
256KHz
11
64KHz
The SPI in slave mode support maximum clock speed is 576K.
SPI_Clock
Rxdepth_intr
An RxINT interrupt event 1723[bit 4] is generated when received byte count reaches Rxdepth_intr[bit 3:0] +1 bytes.
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Revision 1.3
W681307
15.1.3
SPI Status
Address
Access Mode
Value At Reset
0x1722
R
00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
RxFIFOgeThres
hold
TxEmpty
RxEmpty
TxOverflow
RxOverflow
RxOverflow
TxOverflow
RxEmpty
TxEmpty
RxFIFOgeThreshold
15.1.4
When SPI keeps on receiving data and Rx-FIFO is full, the RxOverflow will be set to 1.
When 8032 writing data is fast than SPI transmitting rate, the Tx-FIFO will overflow indicated by TxOverflow bit.
Indicate the Tx-FIFO is currently empty.
Indicate the Tx-FIFO is currently empty.
When RX-FIFO reach to RxDepth_intr (0x1721[3:0]), the RxFIFOgeThreshold will set to 1.
SPI Interrupt Enable
Address
Access Mode
Value At Reset
0x1723
R/W
00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
RxInt
TxEmpty
Reserved
TxOverflow
RxOverflow
According to 0x1722, these interrupts will occur if the corresponding interrupts enable.
RxOverflow
TxOverflow
TxEmpty
RxInt
Rx overflow interrupt enable.
Tx overflow interrupt enable.
Tx empty interrupt enable. (Recommended this bit served in low data rate interface application.)
Rx interrupt enable. RX interrupt occurs upon the number of rx data reaches Rxdepth_intr[3:0].
15.1.5
DumpByte
Address
Access Mode
Value At Reset
0x1724
R
00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
DumpByte[7:0]
If 1720[3] DumpCmp is set to "1", the received byte will be filtered out (No Write to RX-FIFO) when DumpByte is equal to Received
Byte.
15.1.6
Write TX FIFO
Address
Access Mode
Value At Reset
0x1725
W
00
Nominal Value
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Publication Release Date: May, 2007
Revision 1.3
W681307
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
TxFIFO[7:0]
Store data in SPI TX-FIFO when micro controller writes data to this register.
15.1.7
Read RX FIFO
Address
Access Mode
Value At Reset
0x1726
R
00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
RxFIFO[7:0]
Read data from SPI RX-FIFO when micro controller read data from this register.
15.1.8
SPI_Transfer_Size
Address
Access Mode
Value At Reset
0x1727
R/W
00
Bit 7
Bit 6
Bit 5
Bit 4
Reserved
Reserved
Reserved
Reserved
SPI_Transfer_Size
15.1.9
Nominal Value
Bit 3
Transfer Size [3:0]
perform (transfer size+1) bytes of Tx/Rx when start_rtx is set. (master mode only)
SPI_Start_rtx
Address
Access Mode
Value At Reset
0x1728
R/W
00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Start_rtx
Start_rtx
Set to 1 to start Tx/Rx for (transfer size+1) bytes; cleared by hardware automatically when it is done.
(master mode only)
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Publication Release Date: May, 2007
Revision 1.3
W681307
16.
16.1
SPI FOR SERIAL DATA FLASH
Introduction to SPI of Serial Data Flash
Winbond W681307 chip embed a SPI of serial data flash (DF_SPI) port which is a 4-pin (SCK, /DF_CS, SDI, SDO) SPI Interface. This
SPI interface makes W681307 chip easy to control 4-pin Serial Peripheral Interface (SPI) Data Flash memories. It has various clock speed
and data format configurations by setting control register. The SPI interface can be operated at clock rates of up to CPU CLK frequency /
2.
16.2
Block Diagram
Figure 16-1 The SPI of the Serial Data Flash block diagram
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Revision 1.3
W681307
16.3
Data Format
The packet/page data format is separated to 2 fields. First one is the Command field, and the second one is Data field. Command field (1
~ 5 bytes) is used to send the control instruction/code and access address. The Data field (0 ~ 256 bytes) is used to send/store the
write/read data of serial data flash. All of Command and Data bytes are sand MSB first.
◆ Example 1: Single Byte Command Only
◆Example 2: Multiple Bytes Command only
◆Example 3: Single Byte Command with Single Byte Write Data
◆Example 4: Single Byte Command with Single Byte Read Data
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◆Example 5: Single Byte Command with Multiple Bytes Write Data
◆Example 6: Single Byte Command with Multiple Bytes Read Data
◆Example 7: Multiple Bytes Command with Multiple Bytes Write Data
◆Example 8: Multiple Bytes Command with Multiple Bytes Read Data
Both command and data field length can be program with write the CMD_LEN (REG 0x1731[2:0]) and DATA_LEN (REG 0x1732[7:0]).
The MAX command field length is 5 bytes. The MAX data field length is 256 bytes.
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16.4
FSM
There have 3 states in the DF_SPI module : IDLE, CMD and DATA.
Step1. While power on reset, the FSM initial is in the IDLE state.
Step2. After enable the DF_SPI function (write REG 0x1730[7]=1), the FSM start to wait the CPU control to change to CMD state (write
REG 0x1731), then force control logic to shift out the command bytes sequentially to serial data flash.
Step3. After finished shift out the command bytes, the FSM will change to DATA state if the Data_enb (REG 0x1731[4]) is true, or run
back to IDLE state if the Data_enb is false.
Step4. When FSM goes into Data state, the control logic will start to shift out the write out data to serial data flash if DF_RD (REG
0x1731[3]) is false, or shift in the read back data from serial data flash if DF_RD (REG 0x1731[3]) if true.
Step5. After finished shift out/in the data bytes, the FSM will go back to IDLE state, and wait for next transition.
16.5
FIFO/RAM
：
The DF_SPI module takes 5 bytes register to write the control command and takes the 256x8 bytes RAM to do the Read/Write access
FIFO. It supports 2 kinds of memory access method
Type1. FIFO like method:
The CPU always read/write the same address, then the hardware control the memory read/write address, and increase the
read/write point automatically after each read/write. The current write/read point can be read back at REG 0x173E/0x173F.
Type2. Direct access method:
The CPU can read/write any byte of the memory with write the read (REG 0x173F)/write (REG 0x173E) point first.
16.6
Interrupt
The DF_SPI module supports two kinds of interrupt source. One is the TX/RX finish interrupt, occur while TX/RX byte counts (REG
0x173D) is equal to DATA_LEN, the other is middle flag interrupt, occur while TX/RX byte counts (REG 0x173D) is equal to the 16 *
INTR_CNT (REG 0x1733[7:4]). Any other concept, please reference to the description of the registers.
16.7
DF_SPI Register Group
16.7.1
DF_CLK
Address
Access Mode
Value At Reset
0x1730
R/W
00
Bit 7
DF_ENB
CLK_REG
Bit 6
Bit 5
Nominal Value
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CLK_REG [6:0]
Clock Divider Base to decide the DF_clk clock frequency.
DF_CLK freq. = CPU CLK freq. / (CLK_REG + 1)
EX:
CLK_REG [6:0] = 0x01→ DF_CLK freq. = CPU CLK freq. / 2
CLK_REG [6:0] = 0x03 → DF_CLK freq. = CPU CLK freq. / 4
Note: CLK_REG [6:0] must
1 while DF_CLK active.
≧
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DF_ENB
16.7.2
When set, enable DF_SPI module.
When reset, disable DF_SPI module.
Note: The FIFO/RAM only can be access while this bit is set enable.
DF_CMD_LEN
Address
Access Mode
Value At Reset
0x1731
R/W
00
Bit 7
Bit 6
Bit 5
Nominal Value
Bit 4
Bit 3
DATA_ENB
DF_RD
Bit 2
Bit 1
Bit 0
CMD_LEN [2:0]
≦
CMD_LEN
Command Field Length. (unit: byte,CMD_LEN
4)
Command Field Length = CMD_LEN + 1
EX: CMD_LEN = 0x03 → Command Field Length = 4 bytes.
DF_RD
Read/Write Flag. (1: Read,0: Write)
DATA_ENB
Enable Data Field. (1: Enable, 0: Disable)
Note: While DF_ENB = 1, write this byte will force DF module start to TX/RX
16.7.3
DF_DATA_LEN
Address
Access Mode
Value At Reset
0x1732
R/W
00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
DATA_LEN [7:0]
DATA_LEN
16.7.4
Data Field Length.(unit: byte)
Data Field Length = DATA_LEN + 1
EX: DATA_LEN = 0x0F → Data Field Length = 16 bytes.
DF_INTR_REG
Address
Access Mode
Value At Reset
0x1733
R/W
00
Bit 7
Bit 6
Bit 5
INTR_CNT [3:0]
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
RD_FLAG
RX_OK
TX_OK
INTR_ENB
INTR_ENB
When set, enable DF module interrupt.
When reset, disable DF module interrupt.
This module support 2 kind of interrupt source. One is the TX/RX Finished interrupt
(occurred while TX/RX bytes = DATA_LEN), the other is internal pre-interrupt (occurred
while TX/RX bytes = INTR_CNT * 16).
TX_OK
TX Finish Interrupt.( Read Only)
This bit will be clear automatically while next TX/RX
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RX_OK
RX Finish Interrupt.( Read Only)
This bit will be clear automatically while next TX/RX
RD_FLAG
The same with DF_RD. ( Read Only)
INTR_CNT
Internal Pre Interrupt.
Internal interrupt @ TX/RX byte count = (INTR_CNT * 16).
If want to disable the internal pre-interrupt, please set INTR_CNT = 0
While internal pre-interrupt occurred, the interrupt status TX_OK/RX_OK will be both
zero. The RD_FLAG will indicate the pre-interrupt is TX or RX.
EX:INTR_CNT [3:0] = 0x01 → internal interrupt @ TX/RX = byte 16.
16.7.5
DF_CMD_B1 ~ DF_CMD B5
Address
Access Mode
Value At Reset
0x1734
R/W
00
Address
Access Mode
Value At Reset
0x1735
R/W
00
Address
Access Mode
Value At Reset
0x1736
R/W
00
Address
Access Mode
Value At Reset
0x1737
R/W
00
Address
Access Mode
Value At Reset
0x1738
R/W
00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Nominal Value
Nominal Value
Nominal Value
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
CMD_B1 [7:0]
CMD_B2 [7:0]
CMD_B3 [7:0]
CMD_B4 [7:0]
CMD_B5 [7:0]
CMD_B1
Command Byte 1.(0x1734)
CMD_B2
Command Byte 2.(0x1735)
CMD_B3
Command Byte 3.(0x1736)
CMD_B4
Command Byte 4.(0x1737)
CMD_B5
Command Byte 5.(0x1738)
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16.7.6
DF_CLK_FORMAT
Address
Access Mode
Value At Reset
0x173B
R/W
00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
CSN_MORE
CK_MORE
CP
CI
There have 4 control bits (CSN_MORE, CK_MORE, CP and CI) to decide the DF_SPI data format.
CSN_MORE
When set, DF_CSN toggling only while DF_CLK stable.
CK_MORE
Extend one more clock before/after signal DF_CSN active.
CP
DF_CLK transition position setting.
When CP = 1, DF_CLK start toggling in the middle of transfer.
When CP = 0, DF_CLK start toggling at the beginning of transfer.
CI
DF_CLK level while DF_CSN is non active.
When CI = 1, DF_CLK is high while DF_CSN is non active.
When CI = 0, DF_CLK is low while DF_CSN is non active.
CSN_MORE
When set, DF_CSN toggling only while DF_CLK stable.
CK_MORE
Extend one more clock before/after signal DF_CSN active.
CP
DF_CLK transition position setting.
-- When CP = 1, DF_CLK start toggling in the middle of transfer.
-- When CP = 0, DF_CLK start toggling at the beginning of transfer.
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CI
DF_CLK level while DF_CSN is non active
-- When CI = 1, DF_CLK is high while DF_CSN is non active.
-- When CI = 0, DF_CLK is low while DF_CSN is non active.
Note: For W25X and W25P serial SPI-Flash, these control bits are all zeros.
16.7.7
DF_FIFO_DATA
Address
Access Mode
Value At Reset
0x173C
R/W
00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
FIFO_DATA [7:0]
FIFO_DATA
16.7.8
TX/RX FIFO Read/Write data.
When write this byte, i.e. put transmit data into FIFO.
When read this byte, i.e. read back the current data in FIFO.
After Read/Write this byte, the CPU read/write point will increase one automatically.
DF_CNT
Address
Access Mode
Value At Reset
0x173D
R
00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
DF_CNT [7:0]
DF_CNT
Current TX/RX byte count point.
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16.7.9
DF_WR_CNT
Address
Access Mode
Value At Reset
0x173E
R/W
00
Bit 7
Bit 6
Bit 5
Nominal Value
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DF_WR_CNT [7:0]
DF_WR_CNT
16.7.10
CPU current write-point. (unit: byte)
Write this byte will force CPU write point set to the DF_WR_CNT value.
DF_RD_CNT
Address
Access Mode
Value At Reset
0x173F
R/W
00
Bit 7
Bit 6
Bit 5
Nominal Value
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DF_RD_CNT [7:0]
DF_RD_CNT
16.8
CPU current read-point. (unit: byte)
Write this byte will force CPU read point set to the DF_RD_CNT value.
Example of W25X20/40/80 Serial Flash
1.
Write Enable(0x1734 = 06) / Write Disable(0x1734 = 04) / Chip Erase(0x1734 = C7) / Power-down(0x1734 = B9)
0x1730 = 0x81// Set DF_enb, CLK = CPU clock / 2
0x1734 = 0x06// Set CMD Byte1 0x06 / 0x04 / 0xC7 / 0xB9 (code)
0x1731 = 0x00// Force 1 byte TX (CMD)
2.
Read Status Register(0x1734 = 05)
0x1730 = 0x87// Set DF_enb, CLK = CPU clock / 8
0x1732 = 0x00// Set CMD Data Field Length = 1 byte
0x1734 = 0x05// Set Byte1 0x05 (code)
0x1731 = 0x18// Force 1 byte TX (CMD), and 1 byte RX
3.
Write Status Register(0x1734 = 01)
0x1730 = 0x8A// Set DF_enb, CLK = CPU clock / 11
0x1734 = 0x01// Set CMD Byte1 0x01 (code)
0x1735 = 0x04// Set CMD Byte2 0x04 (S7-S0)
0x1731 = 0x01// Force 2 bytes TX (CMD)
4.
Block Erase(0x1734 = D8) / Sector Erase(0x1734 = 20)
0x1730 = 0x8A// Set DF_enb, CLK = CPU clock / 11
0x1734 = 0xD8// Set CMD Byte1 0xD8 / 0x20 (code)
0x1735 = 0x34// Set CMD Byte2 0x34 (A23-A16)
0x1736 = 0x35// Set CMD Byte3 0x35 (A15-A8)
0x1737 = 0x36// Set CMD Byte4 0x36 (A7-A0)
0x1731 = 0x03// Force 4 bytes TX (CMD)
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5.
Read Data (0x1734 = 03)
0x1730 = 0x8B// Set DF_enb, CLK = CPU clock / 12
0x1732 = 0x0F// Set Data Field Length = 16 bytes
0x1733 = 0x01// Enable Interrupt
0x1734 = 0x03// Set CMD Byte1 0x03 (code)
0x1735 = 0x04// Set CMD Byte2 0x04 (A23-A16)
0x1736 = 0x05// Set CMD Byte3 0x05 (A15-A8)
0x1737 = 0x06// Set CMD Byte4 0x06 (A7-A0)
0x1731 = 0x1B// Force 4 bytes TX (CMD), and 16 bytes RX (DATA)
6.
Page Program (0x1734 = 02)
0x1730 = 0x83// Set DF_enb, CLK = CPU clock / 4
0x1732 = 0x0F// Set Data Field Length = 16 bytes
0x1734 = 0x02// Set CMD Byte1 0x02 (code)
0x1735 = 0x52// Set CMD Byte2 0x54 (A23-A16)
0x1736 = 0x51// Set CMD Byte3 0x55 (A15-A8)
0x1737 = 0x50// Set CMD Byte4 0x56 (A7-A0)
0x173E = 0x00// Reset CPU write point to 0x00
0x173C = 0xD0// Write Data Byte 1 (first data byte)
0x173C = 0xDF// Write Data Byte 16 (last data byte)
0x1731 = 0x13// Force 4 bytes TX (CMD), and 16 bytes TX (DATA)
7.
Release Power-down and Device ID (0x1734 = AB)
0x1730 = 0x84// Set DF_enb, CLK = CPU clock / 5
0x1732 = 0x00// Set Data Field Length = 1 bytes
0x1734 = 0xAB// Set CMD Byte1 0xAB (code)
0x1735 = 0x00// Set CMD Byte2 0x00 (dummy)
0x1736 = 0x00// Set CMD Byte3 0x00 (dummy)
0x1737 = 0x00// Set CMD Byte4 0x00 (dummy)
0x1731 = 0x1B// Force 4 bytes TX (CMD), and 1 byte RX (DATA)
8.
Manufacturer-Device ID(0x1734 = 90)
0x1730 = 0x85// Set DF_enb, CLK = CPU clock / 6
0x1732 = 0x01// Set Data Field Length = 2 bytes
0x1734 = 0x90// Set CMD Byte1 0x90 (code)
0x1735 = 0x00// Set CMD Byte2 0x00 (dummy)
0x1736 = 0x00// Set CMD Byte3 0x00 (dummy)
0x1737 = 0x00// Set CMD Byte4 0x00 (00h)
0x1731 = 0x1B// Force 4 bytes TX (CMD), and 2 bytes RX (DATA)
9.
JEDECID(0x1734 = 9F)
0x1730 = 0x85// Set DF_enb, CLK = CPU clock / 6
0x1732 = 0x02// Set Data Field Length = 3 bytes
0x1734 = 0x9F// Set CMD Byte1 0x9F (code)
0x1731 = 0x18// Force 1 bytes TX (CMD), and 3 bytes RX (DATA)
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17. WINBOND 2-WIRE SERIAL BUS
17.1
Introduction to Winbond 2-Wire Serial bus
Winbond 2-wire serial bus (W2S) is a simple bi-directional 2-wire bus for efficient inter-IC control. This design is for W2S master use
only, and governed by micro controller, typically an 8032. The W2S used in the chip is used to both read/write from/to EEPROM and
control melody device. The W2S master controller equips 35 bytes FIFO performing W2S formatting and de-formatting. The micro
controller can simply fill up the FIFO contents which consists of target device ID, high/low address (depend on the device format); for
reading, just set read enable , for writing, keep writing data to FIFO then set write enable to launch transmission. The W2S master
controller supports up to 3 kinds of page writing, i.e. 8, 16, 32 bytes. The W2S master controller designed to support maximum 32 bytes
per page, and the FIFO depth is calculated as 3 header bytes (one device ID, two address) plus 32 bytes for data. It has various bus speed
configurations to support wide range of EEPROM bus speed.
17.2
The Description of W2S Register
17.2.1
W2S_Enable
Address
Access Mode
Value At Reset
0x1740
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W2S_ENA
W2S_Port_Sel
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
W2S_HW
_Protection
W2S_ENA: Set this bit will activate W2S bus controller.
W2S_Port_Sel: Pin selection for hardware W2S bus function.
W2S_Port_Sel
Pin name
0
P1.2 : SDA0
P1.3 : SCL0
1
P1.3 : SDA1
P1.4 : SCL1
If W2S_HW_Protection is set to 1, the couple of pins set by bit W2S_Port_Sel become tri-state as core power below the operation
voltage (see following table).
※
※
Micro-C must set W2S_ENA bit before setup Force_Activity (0x1745) register, and the content of W2S Status (0x1746) is valid only
if W2S_ENA bits is set to 1.
W2S_HW_Protection: Set this bit will force W2S bus pins into tri-state output mode, when the CPWR_Det is low activity. Which pins
will be forced to tri-state output is dependent on the W2S_ENA and W2S_Port_Sel bits setting. The forced pins are listed as below when
the bit CPWR_Det is low. That means the core power voltage is below 1.7V. And the hardware W2S bus will into protection mode to
avoid the E2PROM data corruption.
Table 17-1
CPWR_Det
0
1
(Read only)
W2S_HW_Protection
0
1
Don’t care
X
W2S_ENA
Don’t care
Don’t care
X
W2S_Port_Sel
0
1
Don’t care
X
V
X
X
P1.2
X
V
V
X
P1.3
X
X
X
P1.4
V
PS V means this pin is forced to tri-state output mode.
X means this pin state no any change.
：
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17.2.2
EEPROM_Config
Address
Access Mode
Value At Reset
0x1741
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Bit 1
EEPROM_Format
Bit 0
HEADER
This register is used for W2S bus read cycle.
EEPROM_Format is used for different Page Mode:
EEPROM_format
Page Mode
0 0
8-byte
0 1
16-byte
1 0
32-byte
1 1
RESERVED
HEADER bit is used to support different page size of EEPROM.
“0” is for C16, “1” is for C32/64/128/256
17.2.3
Prescale_Lo
Address
Access Mode
Value At Reset
0x1742
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
Bit 1
Bit 0
Prescale_Lo
This register is used to control W2S bus speed, companion with Prescale_Hi register.
For 100KHz W2S bus operation, set Prescale_Lo to 22H, and Prescale_Hi to 00H.
17.2.4
Prescale_Hi
Address
Access Mode
Value At Reset
0x1743
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Prescale_Hi
This register is used to control W2S bus speed, companion with Prescale_Lo register.
For 100KHz W2S bus operation, set Prescale_Lo to 22H, and Prescale_Hi to 00H.
Prescale Reg. Value
W2S Bus Clock
0x0068
33 KHz
0x0034
66 KHz
0x0022
100 KHz
0x0019
133 KHz
0x0014
166 KHz
0x0006
500 KHz
System Clock: 13.824 MHz
W2S Bus Clock =
System Clock
4 × (Prescale + 1)
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W681307
17.2.5
RdWrFIFO
Address
Access Mode
Value At Reset
0x1744
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
8-bit data from/to FIFO
This register can be used for W2S both read and write W2S-bus compatible device.
Writing data (including target device ID, high address, low address, and repeat ID, Data) to this register will be automatically stored in
W2S controller FIFO. When micro-C receives interrupt from W2S, micro-C need to check W2SStatus (0x1746) register to confirm the
transmission is OK. If there is no error during W2S read process, micro-C can start reading FIFO content by reading RdWrFIFO register.
Micro-C must set RDActive bit (0x1745[5]) before start reading RdWrFIFO (0x1744) W2S FIFO content.
※
17.2.6
Force_Activity
Address
Access Mode
Value At Reset
0x1745
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RDActive
RESERVED
Rst_Rd_Ptr
Rst_Wr_Ptr
RDWRn
RDWR_en
RDActive: Set RDActive bit will enable the read capability of RdWrFIFO (0x1744).
To achieve STOP pattern on W2S bus at power on initial, it can send “acknowledge polling” pattern.
How to send “acknowledge polling” pattern:
After bit W2S_ENA (of register 1470) set 1, writes 0x00H or 0xA0H to FIFO (0x1744H). Finally, sets Force_Activity (0x1745) to 0x01H.
After these operations, W2C controller can start reading from or writing to EEPROM. This mechanism used for once when power on is
an option to enhance EEPROM stability.
Set Rst_Rd_Ptr bit will rest W2S controller internal FIFO read pointer.
Set Rst_Wr_Ptr bit will rest W2S controller internal FIFO write pointer.
RDWRn: For Read operation, reset RDWRn to 0, for Write operation, set RDWRn to 1.
Set RDWR_en bit will enable read or write operation depend on RDWRn.
Micro-C must set W2S_ENA bit before setup Force_Activity.
Write 0xFF to 0x1746 to reset all W2S_Status bits and reset W2S-FIFO both read and write pointer (0x1745[3] and 0x1745[2] set to 1)
and then clear (0x1745[3] and 0x1745[2] reset to 0) before enable read or write operation.
※
※
17.2.7
W2S_Status
Address
Access Mode
Value At Reset
0x1746
R
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
FIFO_empty
FIFO_full
ACK_Fail
FIFO_empty bit will generate W2S interrupt during write operation.
FIFO_full bit will generate W2S interrupt during read operation.
ACK_Fail bit indicates that there is no response for target device during ACK period Rread or Write process, this bit will generate W2S
interrupt.
W2S_Status register content is valid only if W2S_ENA bit has been set.
※
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17.2.8
FIFORdPtr
Address
Access Mode
Value At Reset
0x1747
R
0x00
Bit 7
Bit 6
Bit 5
RESERVED
RESERVED
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
Bit 1
Bit 0
Bit 1
Bit 0
FIFORdPtr
This register is used to monitor W2S FIFO read pointer.
17.2.9
FIFOWrPtr
Address
Access Mode
Value At Reset
0x1748
R
0x00
Bit 7
Bit 6
Bit 5
RESERVED
RESERVED
Bit 4
Nominal Value
Bit 3
Bit 2
FIFOWrPtr
This register is used to monitor W2S FIFO write pointer.
17.2.10
ForceAckFail
Address
Access Mode
Value At Reset
0x1749
R/W
0x00
Bit 7
Bit 6
Bit 5
AckFailEna
RESERVED
Bit 4
Nominal Value
Bit 3
Bit 2
AckFailPtr
AckFailEna: Enable Ack Fail Event
AckFailPtr: During write data to EEPROM or Melody devices, the Ack Fail event will occur at the AckFailPtr-th data of W2S FIFO
content.
17.2.11
W2S_Misc
Address
Access Mode
Value At Reset
0x174A
R
0x00
Bit 7
Bit 6
Bit 5
Bit 4
RESERVED
RESERVED
RESERVED
SCL_in
Nominal Value
Bit 3
Bit 2
C_STATE
Bit 1
Bit 0
W2SIntrpt
This register only monitor several status.
SCL_in: 0: current SCL_in is pull low, 1: current SCL_in pull high.
C_STATE: current finite state machine state.
W2SIntrpt: current interrupt signal indication.
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W681307
18.
18.1
USB DEVICE CONTROLLER AND TRANSCEIVER
Overview
W9681307 is built in a fully functional USB 1.1 controller to be an USB device. It supports most functions of USB 1.1 standard
specification and some required functions of USB audio class and HID class profiles for driver free on Microsoft OS in Skype or VOIP
wireless applications. In ISP mode application, users also can download program code between PC and external ROM flash memory via
USB now. The USB core embeds one 512x8 byte rom to store default descriptors. In the setting, the USB core includes four interfaces
and seven endpoints to handle above applications.
18.2
Functionality
Figure 18-1 The USB block diagram
The USB block diagram is shown in Figure 18-1. The USB module supports all transfer types (Control Endpoint 0, Bulk In, Bulk Out,
Interrupt In, Isochronous In, and Isochronous Out) in. USB 1.1 spec and W681307 USB embeds seven Endpoints include Control
Endpoint 0. The default descriptors are stored in the 512x8 Bytes ROM. The SIE module is for handle USB series-interface-engine
functions. UCOM module is a bridge to communicate SIE and all transfer type modules. Register Control module is for handle CPU
read/write and data signals of W681307 USB registers. Gain Stage is required for adjust gain of pcm data in audio volume control
application. USB Test module connects many internal signals to test pins for help monitor them from outside.
The feature of the USB module is as follows
USB Specification version 1.1 compliant
Full-Speed (12MHz)
Audio Class Interface and Command support (Volume Control, Mute Control)
HID Class Interface and Command support (Set Report)
USB ISP mode support
Vendor Command support
Programmable to connect/disconnect 1.5Kohm pull-up resistance on D+ bus
Support five interfaces and seven endpoints (Control, Bulk In, Bulk Out, Interrupt In, Isochronous In, and Isochronous Out)
Ping-Pong FIFO control for Bulk In/Bulk Out transfer to get better performance
Provide one of three bytes isochronous in endpoint to synchronize isochronous out endpoint for let PC trim the speed of data
stream to improve voice quality.
：
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Revision 1.3
W681307
18.2.1
Mass Storage Class Command support (GER_MAX_LUN)
Endpoints
The definitions of embedded Endpoints are in Table 18-1.
Address
Type
Direction
Maximum Packet Size (Bytes)
Memory Type
0
Control
IN/OUT
8
Registers
1
ISO
IN
16
2
ISO
OUT
18
64x16
(Shared – double buffer)
3
Bulk
IN
64
128 x 8 (double buffer)
4
Bulk
OUT
64
128 x 8 (double buffer)
5
Interrupt
IN
8
Registers
6
ISO
IN
3
Registers
Table 18-1 W681307 USB Endpoint Definitions
18.2.2
Descriptor Rom
The default descriptors are stored in the 512x8 Bytes ROM. The address mapping and bank definition of this ROM are shown in Figure
18-2. The logical topology from these descriptors is shown in Figure 18-3.
0x000H ~ 0x011H
Device Descriptor
18 Bytes
Configuration Descriptor +
Interface Descriptor +
Endpoint Descriptor +
0x012H ~ 0x17FH
Audio Class Descriptor +
366 Bytes
HID Descriptor +
Report Descriptor
0x180H ~ 0x183H
String Descriptor Index 0
4 Bytes
0x184H ~ 0x1BFH
String Descriptor Index 1
60 Bytes
0x1C0H ~ 0x1DFH
String Descriptor Index 2
32 Bytes
0x1E0H ~ 0x1FFH
String Descriptor Index 3
32 Bytes
Figure 18-2 Descriptor ROM Definitions
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Revision 1.3
W681307
Figure 18-3 The Local Topology of Embedded Descriptors
18.2.3
Configurations and Interfaces
：
The configuration and interface settings in W681307 USB are shown in Figure 18-3.
The descriptions are as follows
Configuration 0 : The default configuration for all usb devices
Interface 0 : The default interface for all usb devices
Configuration 1
Interface 0 : Audio Class Interface
Interface 1 : Audio Class Interface for record mode
Alternate 0 : record off
Alternate 1 : record on
Interface 2 : Audio Class Interface for play mode
Alternate 0 : play off
Alternate 1 : play on
Interface 3 : HID Class Interface for commands/status communications
Interface 4 : Non-Class Interface for USB ISP mode or mass data transfer
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18.2.4
Audio Class
W681307 USB provides Audio Class interfaces so it does not need extra driver to be an USB audio device in Microsoft O/S (Windows
2000/XP). Figure 18-4 is shown an USB audio class device topology from embedded descriptors.
Audio Function
ID1
MIC
ID3
ID2
IT
OT
USB Streaming
(USB OUT)
ID4
ID6
ISO IN
(EP1)
ID5
IT
ISO OUT
(EP2)
USB Streaming
(USB IN)
OT
Speaker
ISO IN
(EP6)
Interface 1 (alternate 1)
Interface 2 (alternate 1)
Figure 18-4 USB Audio Class Device Topology
W681307 USB implements Volume Control and Mute Control in Play and Record modes.
18.2.4.1
Play Mode
We define the play mode as the traffic flows from the host to the USB device and to the baseband. The Host can turn on/off the play mode
by setting the alternative value from SET INTERFACE 2 command.
18.2.4.2
Record Mode
Define the record mode as the traffic flows from the baseband to the USB host. The Host can turn on/off the record mode by setting the
alternative value from SET INTERFACE 1 command.
18.2.4.3
Mute Control
The host can issue SET_CUR command with wValue equals to 0x100 to change the Mute function of the USB device. The host can turn
on/off the Mute as requests by the users. If the host selects Feature Unit number 1 (ID is 3), the Mute of audio stream from Mic to USB is
changed; if the host selects Feature Unit number 2 (ID is 6), the Mute of audio stream from USB to speaker is updated. The host also can
issue GET_CUR command to read back current Mute status.
Play Mode
Record Mode
Play Data to Baseband
Record Data to Host
ON
ON
If Play Mute is On, send 16’h0000;
otherwise same as data from host
If Play Mute is On, send 16’h0000;
otherwise same as data from host
If Record Mute is On, send 16’h0000; otherwise
same as data from Baseband
ON
OFF
OFF
ON
16’h0000
OFF
OFF
16’h0000
No data to host
If Record Mute is On, send 16’h0000; otherwise
same as data from Baseband
No data to host
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Revision 1.3
W681307
18.2.4.4
Play Mute On/Off means SET_CUR for Mute Control and Feature Unit ID 6 then received data = 1/0
Record Mute On/Off means SET_CUR for Mute Control and Feature Unit ID 3 then received data = 1/0
Volume Control
The host can issue SET_CUR commands with wValue equals to 0x0200 to change the Volumes of the USB device. If the host selects
Feature Unit number 1 (ID is 3), the Volume of audio stream from Mic to USB (means Record Volume) is changed; if the host selects
Feature Unit number 2 (ID is 6), the Volume of audio stream from USB to speaker (means Play Volume) is updated. The host also can
issue GET_CUR command to read back current volume gain value.
Data Settings & Gain Mapping
Play Data to BASEBAND
Record Data to Host
0x7FFF
+24 dB
If host sends SET_CUR for volume control If host sends SET_CUR for volume
in Play path, device will adjust gain of
control in Record path, device will adjust
…
+24 dB
pcm_tx[15:0] via the command then enter gain of pcm_rx[15:0] via the command
0x18xx
+24 dB
BASEBAND after leave ISO out FIFO
then enter ISO IN FIFO
0x17xx
+23 dB
…
…
0x01xx
+1 dB
0x00xx
0 dB
0xFFxx
-1 dB
0xFExx
-2 dB
…
…
0xE2xx
-29 dB
0xE1xx
-30 dB
…
-30 dB
0x8000
-30 dB
The default value of GET_CUR for Volume Control is 0x0000 (0 dB)
GET_MIN is 0xE100 (-30dB), GET_MAX is 0x1800 (+24 dB) and GET_RES is 0x0100 (+1 dB)
18.2.4.5
Synchronization for Data Transfer
To better synchronization, an endpoint (endpoint 6) is dedicated to provide rate adjustment information to host. The descriptor can set a
time interval, so the host will request the rate information (3 bytes) from that endpoint by using that frequency.
18.2.4.6
Audio Data Format
The data format is 16 bits linear PCM in Audio path and the sample frequency is 8 KHz.
18.2.5
HID Class
Interface 3 is a HID Class interface and it has one Interrupt In endpoint. The device can receive commands from host via SET REPORT
and report hardware’s status to host via Interrupt In transfer in Skype application.
18.2.5.1
Set (Feature) Report
In default descriptors, define 8 bytes feature report descriptors in Report Descriptor. Host can send Set Report command to device then
the device can do the action after receive and analyze these 8 bytes data. We use the way to deliver Skype or Winbond commands from
host to device.
18.2.5.2
Interrupt In
We use the interrupt in transfer to report the device status to host. The maximum packet size is 8 bytes and the time of polling interval is
about 64 ms.
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Revision 1.3
W681307
18.2.6
USB ISP mode
Interface 4 does not belong to any class. It has one Bulk In and Bulk Out endpoints. Both maximum packet sizes are 64 bytes. For gain
better performance, we implement ping-pong FIFO control in Bulk In/Out transfer.
USB ISP mode uses interface 4. It can download code from PC to external flash by Bulk Out or read the code of external flash on PC by
Bulk In via USB bus after install the driver.
18.2.7
Vendor Command
The Vendor command is supported. The bits [6:5] = 2 means Vendor command and bit 7 means data transfer direction in byte 0 of
SETUP data in USB 1.1 spec. Based on the rules, users can define individual vendor commands and use them to communicate host and
device.
18.3
USB Registers
18.3.1
USB Enable Register
Address
Access Mode
Value At Reset
0x1800
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
SE0_Dis
R_PullUp
TRX_EN
PLL_EN
Suspend_EN
USB_Reset
USB_Rese
Suspend_EN
PLL_EN
TRX_EN
R_PullUp
SE0_Dis
Active High. Reset USB digital part. And when S/W receive RESET Interrupt (from host), could use this bit to reset USB.
Active High. Active High and disable the bias current of Transceiver.
Active High. Enable charge pump and VCO.
Active High. Enable Transceiver.
Active High. Enable a pull-up resister (1.5K ohm) to D+.
Active High, disable SE0. Default is Low, and set D+ and D- to “0”.
When USB device need to enable a pull-up resister to D+, it also need to disable SE0 state.
18.3.2
USB Interrupt Register A
18.3.2.1
Enable
Address
Access Mode
Value At Reset
0x1801
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SET_HID
_Intrpt
RESERVED
CDI_Intrpt
CDO_Intrpt
IRQI_Intrpt
BKO_Intrpt
BKI_Intrpt
VENDER
_Intrpt
18.3.2.2
Status
Address
Access Mode
Value At Reset
0x1802
R
0x00
Nominal Value
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Revision 1.3
W681307
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SET_HID
_Intrpt
RESERVED
CDI_Intrpt
CDO_Intrpt
IRQI_Intrpt
BKO_Intrpt
BKI_Intrpt
VENDER
_Intrpt
18.3.2.3
Clear
Address
Access Mode
Value At Reset
0x1803
W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SET_HID
_Intrpt
RESERVED
CDI_Intrpt
CDO_Intrpt
IRQI_Intrpt
BKO_Intrpt
BKI_Intrpt
VENDER
_Intrpt
VENDER_Intrpt
BKI_Intrpt
BKO_Intrpt
IRQI_Intrpt
CDO_Intrpt
CDI_Intrpt
SET_HID_Intrpt
18.3.3
Detection of Vender request
Detection of Bulk In(EP3) request
Detection of Bulk Out(EP4) request
Detection of Interrupt In(EP5) request
Detection of Control Out (EP0) request
Detection of Control In(EP0) request
Detection of Set HID report request
USB Interrupt Register B
18.3.3.1
Enable
Address
Access Mode
Value At Reset
0x1804
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
PlayOn
_Intrpt
RecordOn
_Intrpt
RESERVED
CONNECT
_Intrpt
18.3.3.2
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
USB_ERROR_I Host_RESUME_I Host_SUSPEND
ntrpt
ntrpt
_Intrpt
Host_RESET
_Intrpt
Status
Address
Access Mode
Value At Reset
0x1805
R
0x00
Bit 7
Bit 6
Bit 5
Bit 4
PlayOn
_Intrpt
RecordOn
_Intrpt
RESERVED
CONNECT
_Intrpt
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
USB_ERROR_I Host_RESUME_I Host_SUSPEND_I
ntrpt
ntrpt
ntrpt
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Host_RESET
_Intrpt
Publication Release Date: May, 2007
Revision 1.3
W681307
18.3.3.3
Clear
Address
Access Mode
Value At Reset
0x1806
W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
PlayOn
_Intrpt
RecordOn
_Intrpt
RESERVED
CONNECT
_Intrpt
Host_RESET_Intrpt
Host_SUSPEND_Intrpt
Host_RESUME_Intrpt
USB_ERROR_Intrpt
CONNECT_Intrpt
RecordOn_Intrpt
PlayOn_Intrpt
18.3.4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
USB_ERROR Host_RESUME_I Host_SUSPEND
ntrpt
_Intrpt
_Intrpt
Host_RESET
_Intrpt
Detection of Reset request.
Detection of Suspend request
Detection of Resume request
Detection of Error request (ex: CRC)
Detection of connect
Detection of Record On
Detection of Play On
EndPoint 0 – Control In/Out Registers
18.3.4.1
Control Register
Address
Access Mode
Value At Reset
0x1810
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
HID_FIFO
_Empty
SDO_RD
CTL_IN_RDY
CTL_IN_RDY
SDO_RD
HID_FIFO_Empty
18.3.4.2
Active High. Control In(EP0) Data is ready. S/W needs to set this bit when they finished writing the Control In
Data (Max: 8 bytes)
Setup or Data out packet is reading for control transfer.
While S/W complete to read the control HID Out Data (0x1820 ~0x1827), set “HID_FIFO_Empty” to High. USB
device will send NAK before “HID_FIFO_Empty” setting to High.
Control In Data
Address
Access Mode
Value At Reset
0x1811
W/R
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
CTLI_D [7:0]
CTLI_D
Control in Data. Internal FIFO has 8 bytes.
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Revision 1.3
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18.3.4.3
Control HID Out Data
Address
Access Mode
Value At Reset
0x1820 ~ 0x1827
R
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
Bit 1
Bit 0
CTLO_HID0 [7:0] ~ CTLO_HID7 [7:0]
18.3.4.4
Control Out Data
Address
Access Mode
Value At Reset
0x1828 ~ 0x182F
R
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
CTLO_D0 [7:0] ~ CTLO_D7 [7:0]
18.3.5
EndPoint 1 and 2 – ISO In/Out Registers
18.3.5.1
Control Register
Address
Access Mode
Value At Reset
0x1830
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
ISO_EN
ISO_RST
Bit 2
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
ISO_RST
ISO_EN
Active High reset ISO In/Out function
Active High, enables ISO In/Out function.
18.3.5.2
ISO SYNC Speed Register
Address
Access Mode
Value At Reset
0x1838~0x1839
R/W
0xFFC0
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
ISO_SYNC_SPEED_0[15:8]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
ISO_SYNC_SPEED_0[7:0]
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Revision 1.3
W681307
Address
Access Mode
Value At Reset
0x183A~0x183B
R/W
0xFFE0
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
ISO_SYNC_SPEED_1[15:8]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
ISO_SYNC_SPEED_1[7:0]
Address
Access Mode
Value At Reset
0x183C~0x183D
R/W
0xFFF0
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
ISO_SYNC_SPEED_2[15:8]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
ISO_SYNC_SPEED_2[7:0]
Address
Access Mode
Value At Reset
0x183E~0x183F
R/W
0xFFFE
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
ISO_SYNC_SPEED_3[15:8]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
ISO_SYNC_SPEED_3[7:0]
Address
Access Mode
Value At Reset
0x1840~0x1841
R/W
0x0002
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
ISO_SYNC_SPEED_4[15:8]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
ISO_SYNC_SPEED_4[7:0]
Address
Access Mode
Value At Reset
0x1842~0x1843
R/W
0x0010
Nominal Value
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Revision 1.3
W681307
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
ISO_SYNC_SPEED_5[15:8]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
ISO_SYNC_SPEED_5[7:0]
Address
Access Mode
Value At Reset
0x1844~0x1845
R/W
0x0020
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
ISO_SYNC_SPEED_6[15:8]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
ISO_SYNC_SPEED_6[7:0]
Address
Access Mode
Value At Reset
0x1846~0x1847
R/W
0x0040
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
ISO_SYNC_SPEED_7[15:8]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
ISO_SYNC_SPEED_7[7:0]
18.3.6
EndPoint 3 – Bulk In Registers
18.3.6.1
Control Register
Address
Access Mode
Value At Reset
0x1848
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
BKI_EN
BKI_RST
BKI_RST
BKI_EN:
Active High, reset Bulk In function
Active High, enable Bulk In function.
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Revision 1.3
W681307
18.3.6.2
Bulk In Data
Address
Access Mode
Value At Reset
0x1849
W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
Bit 1
Bit 0
BKI_DATA[7:0]
BKI_DATA
Bulk_In Data except final data.
18.3.6.3
Bulk In Final Data
Address
Access Mode
Value At Reset
0x184A
W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
BKI_EOP_DATA[7:0]
BKI_EOP_DATA
Bulk_In end of packet data.
18.3.6.4
Bulk In FIFO Empty Flag
Address
Access Mode
0x184B
R
Value At Reset
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
BKI_FIFO
_Empty
BKI_FIFO_Empty
18.3.7
FIFO 0 or FIFO 1 empty flag. S/W needs to check this bit to decide if there still had empty FIFO to write.
EndPoint 4 – Bulk Out Registers
18.3.7.1
Control Register
Address
Access Mode
Value At Reset
0x1850
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
BKO_EN
BKO_RST
BKO_RST
BKO_EN
Active High, reset Bulk Out function
Active High, enable Bulk Out function
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Revision 1.3
W681307
18.3.7.2
Bulk Out FIFO Length
Address
Access Mode
Value At Reset
0x1851
R
0x00
Bit 7
Bit 6
Bit 5
Bit 4
RESERVED
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
Bit 1
Bit 0
BKO_FIFO_LEN[6:0]
BKO_FIFO_LEN [6:0]
18.3.7.3
It will show the present FIFO length.
Bulk Out Data
Address
Access Mode
Value At Reset
0x1852
R
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
BKO_D [ 7:0 ]
BKO_D
Bulk Out Data.
18.3.8
EndPoint 5 – Interrupt In Registers
18.3.8.1
Control Register
Address
Access Mode
Value At Reset
0x1858
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
IRQI_EN
IRQI_RST
Bit 1
Bit 0
IRQI_RST
IRQI_EN
Active High, reset IRQI (EP5) function
Active High, enable IRQI (EP5) function
18.3.8.2
USB Interrupt Data Length
Address
Access Mode
Value At Reset
0x1859
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
RESERVED
RESERVED
RESERVED
IRQI_Start
IRQI_LEN [3:0]
IRQI_Start
Nominal Value
Bit 3
Bit 2
IRQI_LEN [3:0]
Interrupt In (EP5) data length.
Active High, Interrupt In (EP5) active.
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Revision 1.3
W681307
18.3.8.3
Interrupt In Data
Address
Access Mode
Value At Reset
0x1860 ~0x186F
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Bit 1
Bit 0
Bit 1
Bit 0
Bit 1
Bit 0
IRQI_D0 [7:0] ~ IRQI_D15 [7:0]
Total 16 bytes Interrupt In Data.
18.3.9
Specific Register
Address
Access Mode
Value At Reset
0x1870 -1873
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Nominal Value
Bit 3
Bit 2
Blocked (for test modes)
18.3.10
Specific Register
Address
Access Mode
Value At Reset
0x1874
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
18.3.11
Bit 2
Blocked
Blocked
Blocked
(for test modes) (for test modes) (for test modes)
Specific Register
Address
Access Mode
Value At Reset
0x1875
R/W
0x00
Nominal Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Blocked
(for test modes)
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Publication Release Date: May, 2007
Revision 1.3
W681307
19.
PACKAGE DIMENSIONS
100pin LQFP (14x14x1.4 mm footprint 2.0mm)
HD
D
7
5
A
A2
51
7
6
50
100
26
A1
HE E
L
1
25
e
L1
c
b
θ
Y
Controlling Dimension : Millimeters
Symbol
Dimension in inch
Min Nom
Max
A
A1
A
2b
c
0.063
0.002
0.053
0.007
0.004
0.008
0.10
0.556
0.556
13.90
13.90
14.00
14.10
14.00
14.10
0.638
0.638
0.030
15.80
0.50
16.00
0.547
0.547
0.551
0.551
e
HD
0.622
0.630
0.622
0.018
0.630
0.024
0.057
0.011
0.17
0.020
L1
y
15.80
0.45
0.039
7
- 159 -
16.00
0.60
1.00
0.27
0.20
16.20
16.20
0.75
0.10
0.004
0
1.45
1.40
0.22
0.15
E
θ
0.05
1.35
0.055
0.009
0.006
D
HE
L
Dimension in mm
Min Nom
Max
1.60
0
7
Publication Release Date: May, 2007
Revision 1.3
W681307
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in
systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, or for other applications intended to support or sustain life. Further more, Winbond
products are not intended for applications wherein failure of Winbond products could result or lead to a
situation wherein personal injury, death or severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their own risk
and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
- 160 -
Publication Release Date: May, 2007
Revision 1.3