ADVANCED W682510/W682310 DUAL-CHANNEL VOICEBAND CODECS -1- Publication Release Date: April 2005 Revision A10 W682510/W682310 1. GENERAL DESCRIPTION The W682510 and W682310 are general-purpose dual channel PCM CODECs with pin-selectable μLaw or A-Law companding. The device is compliant with the ITU G.712 specification. It operates from a single power supply (+5V for the W682510, +3V for the W682310) and is available in 20-pin PDIP (W682510 only), SSOP, and 24-pin SOP package options. Functions performed include digitization and reconstruction of voice signals, and band limiting and smoothing filters required for PCM systems. The filters are compliant with ITU G.712 specification. The W682510 and W682310 performance is specified over the industrial temperature range of –40°C to +85°C. The W682510 includes an on-chip precision voltage reference and receive output buffer amplifiers, capable of driving 600Ω loads (line transformers.) The analog section is fully differential, reducing noise and improving the power supply rejection ratio. The data transfer protocol supports either parallel or serial synchronous communications for PCM applications. The W682510 and W682310 have a build in PLL that eliminates the need for a master clock and automatically determines the division ratio for the required internal clock. For fast evaluation and prototyping purposes, the W682510DK & W682310DK development kits are available. 2. FEATURES APPLICATIONS • • Digital Telephone Systems • Central Office Equipment Switches, Routers) • PBX Systems (Gateways, Switches) • PABX/SOHO Systems Single power supply o 4.5V to 5.5V (W682510) o 2.7V to 3.8V (W682310) • Typical power dissipation of 35 mW, power-down mode of 5 μW • Fully-differential analog circuit design • Hands free system • On-chip precision reference- • Speakerphone devices o W682510: 1.73V for a 0.8 dBm 0TLP at 600 Ω • VoIP Terminals • Enterprise Phones o W682310: 1.41V reference for a 0TLP of –3.8 dBm into 1200 Ω • ISDN Terminals • Analog line cards • Pin-selectable μ-Law and A-Law companding (compliant with ITU G.711) • CODEC A/D and D/A filtering compliant with ITU G.712 • Industrial temperature range (–40°C to +85°C) • Three packages: 20-pin SSOP, 20-pin PDIP, and 24-pin SOP -2- (Gateways, W682510/W682310 3. BLOCK DIAGRAM DATA T1 μ/A-Law CODEC Filter 1 PCMT1 FST BCLK FSR PCMMS PCMR1 PCM Interface PCMT2 PC M Int erf ac DATA R1 RO1 AO1 AI1 μ /A-Law DATA T2 PCMR2 DATA R2 PLL μ/A-Law CODEC Filter 2 RO2 AO2 AI2 Voltage reference VREF V SSA -3- V SSD V DD PUI Power Conditioning Publication Release Date: April 2005 Revision A10 W682510/W682310 4. TABLE OF CONTENTS 1. GENERAL DESCRIPTION ................................................................................................................. 2 1. GENERAL DESCRIPTION ................................................................................................................. 2 2. FEATURES ......................................................................................................................................... 2 3. BLOCK DIAGRAM ............................................................................................................................. 3 4. TABLE OF CONTENTS...................................................................................................................... 4 5. PIN CONFIGURATION ....................................................................................................................... 6 6. PIN DESCRIPTION ............................................................................................................................. 7 7. FUNCTIONAL DESCRIPTION ........................................................................................................... 8 7.1. Transmit Path............................................................................................................................. 8 7.1.1. AI1, AI2, AO1-, AO2-.............................................................................................................. 9 7.1.2. PCMT1 ................................................................................................................................... 9 7.1.3. PCMT2 ................................................................................................................................. 10 7.2. Receive Path ............................................................................................................................ 10 7.2.1. RO1, RO2 ............................................................................................................................ 10 7.2.2. PCMR1................................................................................................................................. 11 7.2.3. PCMR2................................................................................................................................. 11 7.3. Power Signals .......................................................................................................................... 11 7.3.1. VDD ........................................................................................................................................ 11 7.3.2. VSSA ...................................................................................................................................... 11 7.3.3. VSSD ...................................................................................................................................... 11 7.3.4. VREF ...................................................................................................................................... 12 7.3.5. PUI ....................................................................................................................................... 12 7.4. PCM Interface .......................................................................................................................... 12 7.4.1. μ/A-Law ................................................................................................................................ 12 7.4.2. BCLK .................................................................................................................................... 13 7.4.3. FSR ...................................................................................................................................... 13 7.4.4. FST....................................................................................................................................... 13 7.4.5. PCMMS ................................................................................................................................ 13 7.5. Power State Modes................................................................................................................. 13 7.5.1. Power Save Mode................................................................................................................ 13 7.5.2. Power Down Mode............................................................................................................... 14 7.5.3. Power Save/Down Output pin state ..................................................................................... 14 8. TIMING DIAGRAMS ......................................................................................................................... 15 9. ABSOLUTE MAXIMUM RATINGS................................................................................................... 19 -4- W682510/W682310 10. ELECTRICAL CHARACTERISTICS .............................................................................................. 20 10.1. General Parameters W682510 4.5V – 5.5V ............................................................... 20 10.2. General Parameters W682310 2.7V – 3.8V ............................................................... 20 10.3. Analog Signal Level and Gain Parameters ....................................................................... 22 10.4. Analog Distortion and Noise Parameters .......................................................................... 24 10.5. Analog Input and Output Amplifier Parameters ................................................................ 25 10.6. Digital I/O ................................................................................................................................ 26 11. TYPICAL APPLICATION CIRCUIT................................................................................................ 29 12. PACKAGE DRAWING AND DIMENSIONS................................................................................... 31 12.1. 20L (PDIP) Plastic Dual Inline Package Dimensions (W682510 only) ......................... 31 12.2. 20L SSOP – 209 mil Shrink Small Outline Package Dimensions ................................. 32 12.3. 24 SOP – 300 mil .................................................................................................................. 33 13. ORDERING INFORMATION .......................................................................................................... 34 14. VERSION HISTORY ....................................................................................................................... 35 -5- Publication Release Date: April 2005 Revision A10 W682510/W682310 5. PIN CONFIGURATION VREF RO2 NC RO1 PUI PCMMS NC VDD VSSD FSR PCMR2 PCMR1 1 24 2 23 3 22 4 5 6 7 8 W682510/ W682310 DUAL CHANNEL CODEC 21 20 19 18 17 9 10 16 15 11 12 14 13 AI2 AO2 AO1 AI1 NC μ/ A-Law VSSA NC BCLK FST PCMT2 PCMT1 SOP VREF RO2 RO1 PUI PCMMS VDD VSSD FSR PCMR2 PCMR1 1 20 2 19 3 18 4 5 6 7 8 W682510/ W682310 DUAL CHANNEL CODEC 17 16 15 14 13 12 11 9 10 PDIP (W682510 only), SSOP -6- AI2 AO2 AO1 AI1 μ/A- Law VSSA BCLK FST PCMT2 PCMT1 W682510/W682310 6. PIN DESCRIPTION Pin # Pin # Functionality SSOP PDIP SOP (CH1 = Channel 1, CH2 = Channel 2) VREF 1 1 This pin is used to bypass the signal ground. It needs to be decoupled to VSS through a 0.1 μF ceramic decoupling capacitor. No external loads should be tied to this pin. RO2 2 2 CH2 Non-Inverting output of the receive smoothing filter. This pin can typically drive a 600 Ω load (W682510) or 1200 Ω load (W682310). RO1 3 4 CH1 Non-Inverting output of the receive smoothing filter. This pin can typically drive a 600 Ω load (W682510) or 1200 Ω load (W682310).. PUI 4 5 Power up input signal. When this pin is HIGH (tied to VDD) the part is powered up. When LOW (tied to VSS) the part is powered down. PCMMS 5 6 PCM mode select input (serial or parallel data interface) HIGH = Parallel, LOW = Serial VDD 6 8 Power supply. This pin should be decoupled to VSS with a 0.1μF ceramic capacitor. VSSD 7 9 This is the digital supply ground. This pin should be connected to 0V. FSR 8 10 8 kHz Frame Sync input for the PCM receive section. It can also be connected to the FST pin when transmit and receive are synchronous operations. PCMR2 9 11 CH2 PCM input data receive pin. The data needs to be synchronous with the FSR and BCLK pins. PCMR1 10 12 CH1 PCM input data receive pin. The data needs to be synchronous with the FSR and BCLK pins. PCMT1 11 13 CH1 PCM output data transmit pin. The output data is synchronous with the FST and BCLK pins. PCMT2 12 14 CH2 PCM output data transmit pin. The output data is synchronous with the FST and BCLK pins. FST 13 15 8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes. BCLK 14 16 PCM transmit and receive bit clock input pin for CH1 and CH2 transmit. VSSA 15 18 This is the analog supply ground. This pin should be connected to 0V. μ/A-Law 16 19 Compander mode select pin. μ-Law companding is selected when this pin is LOW (tied to VSS.) A-Law companding is selected when pin is HIGH (tied to VDD.) AI1 17 21 CH1 Non-Inverting input of the first gain stage in the transmit path. AO1- 18 22 CH1 Inverting analog output of the first gain stage in the transmit path. AO2- 19 23 CH2 Inverting analog output of the first gain stage in the transmit path AI2 20 24 CH2 Non-Inverting input of the first gain stage in the transmit path. Pin Name -7- Publication Release Date: April 2005 Revision A10 W682510/W682310 7. FUNCTIONAL DESCRIPTION W682510/W682310 is a single-rail, dual channel PCM CODEC for voiceband applications. The CODEC complies with the specifications of the ITU-T G.712 recommendation. The CODEC includes two complete μ-Law and A-Law companders. The μ-Law and A-Law companders are designed to comply with the specifications of the ITU-T G.711 recommendation. The block diagram in section 3 shows the main components of the W682510/W682310. The chip consists of a PCM interface, which can process the data in parallel or serial formats. The PLL of the chip provides the internal clock signals and synchronizes the CODEC sample rate with the external frame sync frequency. The power-conditioning block provides the internal power supply for the digital and the analog section, while the voltage reference block provides a precision analog ground voltage for the analog signal processing. 8 DATA R1 8 bit μ/A - Law DAC RO1 fC = 3400 Hz Smoothing Filter 1a μ/AControl 8 8 bit μ/A - Law DAC DATA R2 DATA T1 8 bit μ/A - Law ADC μ/AControl 8 DATA T1 T2 8 bit μ/A - Law ADC μ/AControl Smoothing Filter 1b Buffer1 Av=1 RO2 fC = 3400 Hz Smoothing Filter 2a μ/AControl 8 + + Smoothing Filter 2b Buffer2 Av=1 AO1 - fC = 200 Hz High Pass Filter fC = 3400 Hz Aliasing Anti-Aliasin AntiFilter 1a fC = 200 Hz High Pass Filter fC = 3400 Hz Anti-Aliasin Anti-Aliasing AntiFilter 2a AI1 + Aliasing Anti-Aliasin AntiFilter 1b AO2 - AI2 + Anti-Aliasin AntiAliasing Filter 2b FIGURE 7.1: THE W682510 AND W682310 SIGNAL PATH 7.1. TRANSMIT PATH The A-to-D path of the CODEC contains an analog input amplifier with externally configurable gain setting (see application examples in section 11). The transmit amplifier output is the input to the encoder section. The output of the input amplifier is fed through a low-pass filter to prevent aliasing at the switched capacitor 3.4 kHz low pass filter. The 3.4 kHz switched capacitor low pass filter prevents aliasing of input signals above 4 kHz, due to the sampling at 8 kHz. The output of the 3.4 kHz low pass filter is filtered by a high pass filter with a 200 Hz cut-off frequency. The filters are designed according to the recommendations in the G.712 ITU-T specification. From the output of the high pass filter the signal is digitized. The signal is converted into a compressed 8-bit digital representation with either μ-Law or A- -8- W682510/W682310 Law format. The μ-Law or A-Law format is pin-selectable through the μ/A-Law pin. The compression format can be selected according to Table 7.1. TABLE 7.1: PIN-SELECTABLE COMPRESSION FORMAT μ/A-Law Pin Format VDD (HIGH) A-Law VSSA (LOW) μ-Law The digital 8-bit μ-Law or A-Law samples are fed to the PCM interface for serial or parallel transmission at the sample rate supplied by the external frame sync FST. 7.1.1. AI1, AI2, AO1-, AO2AI1 and AI2 are the transmit analog inputs for channels 1 and 2. AO1- and AO2- are the transmit level feedback for channels 1 and 2. AI1 and AI2 are inverting inputs for the Op-Amps. AO1- and AO2- are connected to the outputs of the Op-Amps and are used to set the level, as illustrated below. When AI1 and AI2 are not used, connect AI1 to AO1- and AI2 to AO2-. During power saving mode and power down mode, the AO1- and AO2- outputs are tied weakly to VSSA on the W682510 or are high impedance on the W682310 (See table on page 14). R2 C1 R1 AO1AI1 CH1 Analog Input Gain=R2/R1 ≤ 10 R2 > 20 k Ohm + R4 C2 CH2 Analog Input AO2- Gain=R4/R3 ≤ 10 R4 > 20 k Ohm R3 AI2 + 7.1.2. PCMT1 The PCM signal output of channel 1 when the parallel mode is selected. The PCM output signal is sent from PCMT1 in a sequential order, synchronizing with the rising edge of the BCLK signal. The MSB may be output at the rising edge of the FST signal, based on the timing between BCLK and FST. This output pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power-saving state or power-down. When serial operation is selected, this pin is configured to be the output of the serial multiplexed two channel PCM signal. A pull-up resistor must -9- Publication Release Date: April 2005 Revision A10 W682510/W682310 be connected to this pin , as it is an open drain output. This device is compatible with the ITU-T coding law and output coding format recommendation. TABLE 7.15: PCM CODES FOR ZERO AND FULL SCALE Level μ-Law A-Law Sign bit Chord bits Step bits Sign Bit Chord Bits Step Bits + Full Scale 1 000 0000 1 010 1010 + Zero 1 111 1111 1 101 0101 - Zero 0 111 1111 0 101 0101 - Full Scale 0 000 0000 0 010 1010 7.1.3. PCMT2 The PCM signal output for channel 2 when the parallel mode is selected. The PCM output signal is sent from PCMT2 in a sequential order, synchronized with the rising edge of the BCLK signal. The MSB may be output at the rising edge of the FST signal, based on the timing between BCLK and FST. This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance state during power-saving state or power-down. When the serial operation is selected, this pin is left open. A pull-up resistor must be connected to this pin , as it is an open drain output. This device is compatible with the ITU-T coding law and output coding format recommendation. 7.2. RECEIVE PATH The 8-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed through the pin-selectable μ-Law or A-Law expander and converted to analog samples. The mode of expansion is selected by the μ/A-Law pin as shown in Table 7.2. The analog samples are filtered by a low-pass smoothing filter with a 3.4 kHz cut-off frequency, according to the ITU-T G.712 specification. A sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is buffered to provide the receive output signal RO. 7.2.1. RO1, RO2 RO1 and RO2 are the receive analog outputs for channel 1 and channel 2. The output signal of the W682510 has an amplitude of 3.46 Vpp (2.03 Vpp for W682310) around the signal ground voltage (VREF). When the digital PCM signal of +3 dBm0 is presented to PCMR1 or PCMR2, it can drive a load of 600 Ohms or more at 5 V supply voltage for the W682510 and 1200 Ohms at 3V supply for the W682310. During power saving mode, these outputs are at the voltage level of VREF with a high impedance. These outputs have a feature that reduces audio “pop” noises when switching between active and inactive states and back. - 10 - W682510/W682310 7.2.2. PCMR1 The PCM signal input for channel 1 when in the parallel mode. D/A conversion is performed on the serial PCM signal input to this pin. The FSR signal, synchronous with the serial PCM signal, and the BCLK signal, processes the code. Then the analog output is output from the RO1 pin. The data rate of the PCM signal is equal to the frequency of the BCLK signal. The PCM signal is shifted in on the falling edge of the BCLK signal. It is latched into the internal 8-bit register. The start of the PCM data (MSB) is synchronized with the rising edge of FSR. In the serial mode, this pin is not used and should be connected to GND (0V). 7.2.3. PCMR2 PCM signal input for channel 2 when the parallel mode is selected. D/A conversion is performed with the serial PCM signal input to this pin, the FSR signal, synchronous with the serial PCM signal, and the BCLK signal, and then the analog output is output from the RO2 pin. The data rate of the PCM signal is equal to the frequency of the BCLK signal. The PCM signal is shifted at the falling edge of the BCLK signal and latched into the internal register when shifted by eight bits. The start of the PCM data (MSB) is identified at the rising edge of FSR. In the serial mode this pin is used for the two channel multiplexed PCM signal input. 7.3. POWER SIGNALS 7.3.1. VDD The power supply for the analog and digital parts of the W682510 must be 5V +/- 10% and 2.7V to 3.8V for the W682310. This supply voltage is connected to the VDD pin. The VDD pin needs to be decoupled to ground through a 0.1 μF ceramic capacitor. A power supply for an analog circuit in the system to which the device is applied should be used. A bypass capacitor of 0.1 µF to 1 µF with good high-frequency characteristics (Low ESR) and a capacitor of 10 µF to 20 µF should be connected between this pin and the VSSA pin if needed. 7.3.2. VSSA Ground for the analog signal circuits. This ground is separate from the digital signal ground. The VSSA pin must be connected to the VSSD pin on the printed circuit board to make a common ground. However, it’s advised to connect the PCB traces of these pins at the main supply hookup of the PCB and run the VSSA and VSSD traces separately to the device. 7.3.3. VSSD Ground for the digital signal circuits. This ground is separate from the analog signal ground. The VSSD pin must be connected to the VSSA pin on the printed circuit board to make a common ground. However, it’s advised to connect the PCB traces of these pins at the main supply hookup of the PCB and run the VSSA and VSSD traces separately to the device - 11 - Publication Release Date: April 2005 Revision A10 W682510/W682310 7.3.4. VREF This pin carries the signal ground voltage level and requires a bypass capacitor. A 0.1μF ceramic (with low ESR for good high frequency response) capacitor needs to be connected between the VSSA pin and the VREF pin. 7.3.5. PUI Power up input signal. When the PUI pin is set to logic “0” level, the CODEC will go into power down mode. 7.4. PCM INTERFACE The PCM interface is controlled by pins PCMMS, BCLK, FSR & FST. The input data is received through the PCMR pin and the output data is transmitted through the PCMT pin. The modes of operation of the interface are shown in Table 7.2. TABLE 7.2: PCM INTERFACE MODE SELECTIONS PCMMS VDD [HIGH] VSS PCM Mode Data Available Parallel Mode CH1 data on PCMT1 & PCMR1 Serial Mode CH1 data followed by CH2 receive data on PCMR2 (total 16 bits) [LOW] CH2 data on PCMT2 and PCMR2 (same timing as CH1) CH1 data followed by CH2 transmit data on PCMT1 (total 16 bits) 7.4.1. μ/A-Law This pin selects the desired companding law. The CODEC will operate in the μ-law when this pin is at a logic “0” level and in the A-law when at a logic “1” level. The CODEC operates μ-law if the pin is left open, since this pin is internally pulled down. TABLE 7.25: PIN-SELECTABLE COMPRESSION FORMAT μ/A-Law pin Format HIGH (VDD ) A-Law LOW (VSS), Floating μ-Law - 12 - W682510/W682310 7.4.2. BCLK This is the shift clock signal input for the PCMR1, PCMR2, PCMT1, and PCMT2 signals. The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048 or 200 kHz. Setting this signal to a steady logic “1” or “0” sets both transmit and receive circuits to the power saving state. 7.4.3. FSR This is the receive synchronizing signal input. The required eight-bits of PCM data are selected from the PCM data signal to the PCMR1 and PCMR2 pins by the receive synchronizing signal. All timing signals in the receive section are synchronized by this synchronizing signal. This signal must be in phase with the BCLK. The frequency should be 8 kHz ± 50 ppm to guarantee the AC characteristics. This device can operate in the range of 6 kHz to 9 kHz, but the electrical characteristics specified in the data sheet are not guaranteed. 7.4.4. FST The transmit synchronizing signal input. The PCM output signal from PCMT1 and PCMT2 is sent in synchronization with this transmit synchronizing signal. This FST signal triggers the PLL and synchronizes all timing signals of the transmit section. The synchronizing signal must be in phase with BCLK. The frequency should be 8 kHz ± 50 ppm to guarantee the AC characteristics. This device can operate in the range of 6 kHz to 9 kHz sample rates, but the electrical characteristics are not guaranteed. Setting this signal to logic HIGH or LOW drives both transmit and receive circuits to power saving state. 7.4.5. PCMMS The control signal for mode selection of the PCM input and output. When this signal is HIGH, the PCM input and output are in the parallel mode. The PCM data of CH1 and CH2 is input to PCMR1 and PCMR2, and output from PCMT1 and PCMT2, with the same timing. When this signal is at a LOW level, the PCM input and output are in the serial mode. The PCM data of CH1 and CH2 is input to PCMR2 and output from PCMT1 as two serial 8-bit bytes. 7.5. POWER STATE MODES 7.5.1. Power Save Mode In the power save mode, all internal analog circuits except the internal reference are powered down. The CODEC automatically enters the power save mode when the FST or BCLK signal is set to digital “1” or digital “0”; Upon power up with FST and BCLK signals present, it will take 2 to 10 milliseconds for the internal PLL to lock. In addition to the PLL lock-in time, the analog outputs will be set to the internal signal ground for 1 millisecond. This will avoid power up glitches at the outputs. The digital open drain outputs will remain at high impedance during this power up delay. - 13 - Publication Release Date: April 2005 Revision A10 W682510/W682310 7.5.2. Power Down Mode When the power up indicator pin, PUI, is set LOW all internal circuits will go into the power down state. It will take 2 to 10 milliseconds for the PLL to lock when operation is resumed with the FST and BCLK signals applied and PUI set HIGH. An additional 1-millisecond delay is used to set the analog outputs to the signal ground reference in order to avoid power up glitches. The digital open drain outputs will remain at high impedance during this power up delay. 7.5.3. Power Save/Down Output pin state The following table shows the states of the output pins in the power save or power down mode. TABLE 7.5: OUTPUT PIN STATES Product Name Output Pin AO1-, A02- RO1, RO2 W682510 VSSA Signal Ground W682310 High Z Signal Ground - 14 - W682510/W682310 8. TIMING DIAGRAMS BCLK FST PCMT1 MSB D6 D5 D4 D3 D2 D1 D0 MSB D6 Channel 1 Transmit PCM Data D5 D4 D3 D2 D1 D0 Channel 2 Transmit PCM Data Figure 8-1a. Transmit Side Serial Mode Timing (PCMMS=0) BCLK FSR PCMR2 MSB D6 D5 D4 D3 D2 D1 D0 MSB D6 Channel 1 Receive PCM Data D5 D4 D3 D2 D1 D0 Channel 2 Receive PCM Data Figure 8-1b. Receive Side Serial Mode Timing (PCMMS=0) FIGURE 8.1: SERIAL MODE PCM TIMING BCLK FST PCMT1 PCMT2 MSB D6 D5 D4 D3 D2 D1 D0 Figure 8-2a. Transmit Side Parallel Mode Timing (PCMMS=1) BCLK FSR PCMR1 PCMR2 MSB D6 D5 D4 D3 D2 D1 D0 Figure 8-2b. Receive Side Parallel Mode Timing (PCMMS=1) FIGURE 8.2: PARALLEL MODE PCM TIMING - 15 - Publication Release Date: April 2005 Revision A10 W682510/W682310 BCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FST FSR PCMT1 PCMR2 MSB D6 D5 D4 D3 D2 D1 D0 MSB D6 D5 D4 Channel 1 PCM Data D3 D2 D1 D0 Channel 2 PCM Data Figure 8-3a. Burst Mode with Serial Timing (PCMMS=0) BCLK 1 2 3 4 5 6 7 8 9 FST FSR PCMTx PCMRx MSB D6 D5 D4 D3 D2 D1 D0 Figure 8-3b. Burst Mode with Parallel Timing (PCMMS=1) FIGURE 8.3: BURST MODE PCM TIMING - 16 - 17 W682510/W682310 TABLE 8.1: PCM SYNCHRONIZATION PARAMETERS SYMBOL DESCRIPTION MIN TYP MAX UNIT fFS FST, FSR frequency --- 8 --- KHz tWS FST, FSR Pulse Width 1 --- 7 TBCLK tj FST, FSR allowable jitter 0 --- 500 nsec fBCLK BCLK frequency 64, 128, 256, 512, 1024, 2048, 96, 192, 384, 768, 1536, 1544, 200 kHz DC BCLK Duty Cycle 40 50 60 % tIr FSR, FST, BCLK, PCMR1, PCMR2, PUI, PCMMS input rise time --- --- 50 nsec tIf FSR, FST, BCLK, PCMR1, PCMR2, PUI, PCMMS input fall time --- --- 50 nsec tIr BCLK FSR FST 1 2 3 TBCLK=1/fBCLK DC 4 6 5 tIf 7 8 TFS=1/fFS tWS tj FIGURE 8.4: PCM SYNCHRONIZATION PARAMETERS - 17 - Publication Release Date: April 2005 Revision A10 W682510/W682310 TABLE 8.2: PCM TIMING PARAMETERS SYMBOL DESCRIPTION MIN TYP MAX UNIT tWS FST, FSR Pulse Width TBCLK --- 100 µ sec tXS BCLK low to FST high setup time 100 --- --- nsec tSX FST high to BCLK low hold time 100 --- --- nsec tSD PCMT1, PCMT2 output delay; Cl = 100 pF 20 --- 200 nsec tXD1 PCMT1, PCMT2 output delay; Cl = 100 pF 20 --- 200 nsec tXD2 PCMT1, PCMT2 output delay; Cl = 100 pF 20 --- 200 nsec tXD3 PCMT1, PCMT2 output delay; Cl = 100 pF 20 --- 200 nsec tRS BCLK low to FSR high setup time 100 --- --- nsec tSR FSR high to BCLK low hold time 100 --- --- nsec tDS PCMR1, PCMR2 Data in setup time 100 --- --- nsec tDH PCMR1, PCMR2 Data in hold time 100 --- --- nsec RTL PCMT1, PCMT2 Pull-up resistor 500 --- --- Ohm CTL PCMT1, PCMT2 Load capacitance --- --- 100 pF tXS BCLK 1 2 3 4 tSX FST PCMT1 PCMT2 5 6 7 8 9 tXD2 10 11 10 11 tXD3 tWS tSD MSB tXD1 D6 D5 D4 D3 D2 D1 D0 Figure 8-5a. Transmit Timing tRS BCLK 1 2 3 4 5 6 7 8 tSR FSR tWS tDS PCMR1 PCMR2 MSB D6 tDH D5 D4 D3 D2 D1 D0 Figure 8-5b. Receive Timing FIGURE 8.5 PCM TIMING PARAMETERS - 18 - 9 W682510/W682310 9. ABSOLUTE MAXIMUM RATINGS TABLE 9.1: ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS) Condition Value 0 Junction temperature 150 C Storage temperature range -650C to +1500C Voltage Applied to any pin (VSS - 0.3V) to (VDD + 0.3V) Voltage applied to any pin (Input current limited to +/-20 mA) (VSS – 1.0V) to (VDD + 1.0V) Lead temperature (soldering 3000C – 10 seconds) VDD - VSS -0.5V to +6V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Functional operation is not implied at these conditions. TABLE 9.2: OPERATING CONDITIONS (PACKAGED PARTS) Condition Value 0 Industrial operating temperature 0 -40 C to +85 C Supply voltage (VDD) W682510 5V +4.5V to +5.5V Supply voltage (VDD) W682310 3V +2.7V to +3.8V Ground voltage (VSS) 0V - 19 - Publication Release Date: April 2005 Revision A10 W682510/W682310 10. ELECTRICAL CHARACTERISTICS 10.1. GENERAL PARAMETERS W682510 4.5V – 5.5V Max (2) Units 0.0 0.8 V 2.2 VDD V 0.2 0.4 V 7 14 mA 800 1300 μA 1 10 μA VSS<VIN<VDD 0.5 μA Input High Leakage Current VSS<VIN<VDD 2 μA PCMT1, PCMT2 Leakage Current VSS<PCMT<VDD +/-10 μA 10 pF 15 pF Symbol Parameters Conditions VIL Input Low Voltage VIH Input High Voltage VOL PCMT1, PCMT2 Low Voltage IDD VDD Current (Operating) ADC + DAC No Load, No Signal ISB VDD Current (Standby) FST or BCLK =OFF; PUI=VDD IPD VDD Current (Power Down) PUI= Vss IIL Input Low Leakage Current IIH IOL Output Output Digital Input Capacitance COUT PCMT1, PCMT2 Capacitance 2. 0.0 Typ (1) High Z State CIN 1. Rpullup>500 Ω Min (2) Output 5 PCMT1, PCMT2 = High Z Typical values: TA = 25°C, VDD = 5.0 V All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100 percent tested. 10.2. GENERAL PARAMETERS W682310 2.7V – 3.8V Max (2) Units 0.0 0.16xVDD V 0.45xVDD VDD V 0.2 0.4 V No Load, No Signal 7.4 14 mA VDD Current (Standby) FST or BCLK =OFF; PUI=VDD 700 2000 μA IPD VDD Current (Power Down) PUI= Vss 1 10 μA IIL Input Low Leakage Current VSS<VIN<VDD 0.5 μA Symbol Parameters Conditions VIL Input Low Voltage VIH Input High Voltage VOL PCMT1, PCMT2 Low Voltage IDD VDD Current (Operating) ADC + DAC ISB Output Rpullup>500 Ω Min (2) 0.0 - 20 - Typ (1) W682510/W682310 Symbol Parameters Conditions IIH Input High Leakage Current VSS<VIN<VDD IOL PCMT1, PCMT2 Leakage Current VSS<PCMT<VDD Output Digital Input Capacitance COUT PCMT1, PCMT2 Capacitance 2. Typ (3) Max (4) Units 2 μA +/-10 μA 10 pF 15 pF High Z State CIN 1. Min (4) Output 5 PCMT1, PCMT2 = High Z Typical values: TA = 25°C, VDD = 3.0 V All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100 percent tested. - 21 - Publication Release Date: April 2005 Revision A10 W682510/W682310 10.3. ANALOG SIGNAL LEVEL AND GAIN PARAMETERS W682510: VDD=5V ±10%; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VREF; W682310: VDD=2.7V to 3.8V; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VREF; PARAMETER SYM. CONDITION TYP. TRANSMIT (A/D) MIN. Reference Level Out MAX. RECEIVE (D/A) MIN. UNIT MAX. LABS 0 dBm0 = +0.8 dBm @ 600Ω load 1020 Hz 0.850 --- --- --- --- VRMS T0TLP 1020 Hz 0.850 --- --- --- --- VRMS LABS 0 dBm0 = -3.8 dBm @ 1200Ω load 1020 Hz 0.500 --- --- --- --- VRMS T0TLP 1020 Hz 0.350 --- --- --- --- VRMS Max. Transmit Level In W682510 5V TXMAX 3.17 dBm0 for μ-Law 1.732 --- --- --- --- VPK 3.14 dBm0 for A-Law 1.726 --- --- --- --- VPK Max. Transmit Level In W682310 3V TXMAX 3.17 dBm0 for μ-Law 0.712 --- --- --- --- VPK 3.14 dBm0 for A-Law 0.708 --- --- --- --- VPK Absolute Gain (0 dBm0 @ 1020 Hz; TA=+25°C) GABS 0 dBm0 @ 1020 Hz; TA=+25°C 0 -0.2 +0.2 -0.2 +0.2 dB Absolute Gain variation with Temperature GABST TA=0°C to TA=+70°C 0 -0.08 +0.08 -0.08 +0.08 dB -0.1 +0.1 -0.1 +0.1 Frequency Response, GRTV W682510 5V Reference Level In W682510 5V Reference Level Out W682310 3V Reference Level Out W682310 3V Relative to 0dBm0 @ 1020 Hz TA=-40°C to TA=+85°C 15 Hz --- --- -40 -0.5 0 50 Hz --- --- -30 -0.5 0 60 Hz --- --- -20 -0.5 0 200 Hz --- -1.5 -0.4 -0.5 0 300 to 3000 Hz --- -0.20 +0.20 -0.20 +0.20 3300 Hz --- -0.50 +0.20 -0.50 +0.20 3400 Hz --- -0.8 0 -0.8 0 3600 Hz --- --- 0 --- 0 4000 Hz --- --- -14 --- -14 4600 Hz to 100 kHz --- --- -32 --- -30 - 22 - dB W682510/W682310 Gain Variation vs. Level Tone (1020 Hz relative to –10 dBm0) GLT +3 to –40 dBm0 --- -0.3 +0.3 -0.3 +0.3 -40 to –50 dBm0 --- -0.5 +0.5 -0.5 +0.5 -50 to –55 dBm0 --- -1.2 +1.2 -1.2 +1.2 - 23 - DB Publication Release Date: April 2005 Revision A10 W682510/W682310 10.4. ANALOG DISTORTION AND NOISE PARAMETERS W682510: VDD=5V ±10%; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VREF; W682310: VDD=2.7V to 3.8V; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VREF; PARAMETER Total Distortion vs. Level Tone (1020 Hz, μ-Law, C-Message Weighted) Total Distortion vs. Level Tone (1020 Hz, A-Law, Psophometric Weighted) SYM. DLTμ CONDITION TRANSMIT (A/D) MIN. TYP. MAX. 36 --- --- 36 --- -40 dBm0 29 -45 dBm0 TYP. MAX. 34 --- --- --- 36 --- --- --- --- 30 --- --- 25 --- --- 25 --- --- +3 dBm0 36 --- --- 34 --- --- 36 --- --- 36 --- --- -40 dBm0 29 --- --- 30 --- --- -45 dBm0 25 --- --- 25 --- --- 4600 Hz to 7600 Hz --- --- --- --- --- -30 7600 Hz to 8400 Hz --- --- --- --- --- -40 8400 Hz to 100000 Hz --- --- --- --- --- -30 +3 dBm0 0 dBm0 to -30 dBm0 DLTA RECEIVE (D/A) 0 dBm0 to -30 dBm0 MIN. UNIT dBC dBp Spurious Out-Of-Band at RO- (300 Hz to 3400 Hz @ 0dBm0) DSPO Spurious In-Band (700 Hz to 1100 Hz @ 0dBm0) DSPI 300 to 3000 Hz --- --- -47 --- --- -47 dB Intermodulation Distortion (300 Hz to 3400 Hz –4 to –21 dBm0 DIM Two tones --- --- -41 --- --- -41 dB Crosstalk (1020 Hz @ 0dBm0) DXT --- --- -75 --- --- -75 dBm0 Channel to Channel Crosstalk (1020 Hz @ 0dBm0) DXTCH --- --- -75 --- --- -75 dBm0 Absolute Group Delay τABS 1600 Hz --- --- 360 --- --- 240 μsec Group Delay Distortion (relative to group delay @ 1200 Hz) τD 500 Hz --- --- 750 --- --- 750 μsec 600 Hz --- --- 380 --- --- 370 1000 Hz --- --- 130 --- --- 120 2600 Hz --- --- 130 --- --- 120 2800 Hz --- --- 750 --- --- 750 μ-Law; C-message --- --- 5 --- --- 13 dBrnc A-Law; Psophometric --- --- -69 --- --- -79 dBm0p Idle Channel Noise NIDL - 24 - dB W682510/W682310 10.5. ANALOG INPUT AND OUTPUT AMPLIFIER PARAMETERS W682510: VDD=5V ±10%; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VREF; W682310: VDD=2.7V to 3.8V; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VREF; PARAMETER SYM. CONDITION MIN. TYP. MAX. UNIT. AI1, AI2 Input Offset Voltage VOFF,AI Unity Gain --- --- ±20 mV AI1, AI2 Input Resistance RIN,AI AI1, AI2 to VREF 10 --- --- MΩ AO1-, AO2- Output Amplitude VAD W682510 0 --- 3.4 Vpp W682310 AO1-, AO2- Load Resistance RLOAD AO1-, AO2- Load Capacitance CLOAD RO1, RO2 Load Resistance RLOAD RO1, RO2 Load Capacitance CLOAD RO1, RO2 Output Amplitude VORO 1.4 20 --- --- kΩ AO1-, AO2- --- --- 30 pF W682510 0.6 --- --- kΩ W682310 1.2 RO1, RO2 --- --- 50 pF W682510 --- --- 3.4 Vpp W682310 RO1, RO2 Output Offset Voltage VOFF,RO Signal Ground Voltage to VSSA VREF Power Supply Rejection Ratio (0 to 100 kHz to VDD, C-message) PSRR 2.0 --- --- ±100 mV VDD/2 – 0.1 VDD/2 VDD/2+ 0.1 V Transmit; 50 mVpp -- 40 --- dBC Receive; 50 mVpp -- 40 --- RO to VREF - 25 - Publication Release Date: April 2005 Revision A10 W682510/W682310 10.6. DIGITAL I/O TABLE 10.61: μ-LAW ENCODE DECODE CHARACTERISTICS Normalized Encode Decision Levels 8159 7903 Normalized Digital Code D7 D6 D5 D4 D3 D2 D1 D0 Sign Chord Chord Chord Step Step Step Step 1 0 0 0 0 0 0 0 4063 1 0 0 0 1 1 1 1 2015 1 0 0 1 1 1 1 1 991 1 0 1 0 1 1 1 1 479 1 0 1 1 1 1 1 1 223 1 1 0 0 1 1 1 1 95 1 1 0 1 1 1 1 1 31 1 1 1 0 1 1 1 1 1 0 33 : : 3 99 : : 35 231 : : 103 495 : : 239 1023 : : 511 2079 : : 1055 4191 : : 2143 8031 : : 4319 Decode Levels 1 1 1 1 1 1 1 0 2 1 1 1 1 1 1 1 1 0 Notes: Sign bit = 0 for negative values, sign bit = 1 for positive values - 26 - W682510/W682310 TABLE 10.62: A-LAW ENCODE DECODE CHARACTERISTICS Normalized Encode Decision Levels 4096 3968 Digital Code Normalized D7 D6 D5 D4 D3 D2 D1 D0 Sign Chord Chord Chord Step Step Step Step 1 0 1 0 1 0 1 0 2048 1 0 1 0 0 1 0 1 1024 1 0 1 1 0 1 0 1 512 1 0 0 0 0 1 0 1 256 1 0 0 1 0 1 0 1 128 1 1 1 0 0 1 0 1 64 1 1 1 0 0 1 0 1 0 66 : : 2 132 : : 68 264 : : 136 528 : : 272 1056 : : 544 2112 : : 1088 4032 : : 2048 Decode Levels 1 1 0 1 0 1 0 1 1 Notes: 1. Sign bit = 0 for negative values, sign bit = 1 for positive values 2. Digital code includes inversion of all even number bits - 27 - Publication Release Date: April 2005 Revision A10 W682510/W682310 TABLE 10.63: PCM CODES FOR ZERO AND FULL SCALE μ-Law Level A-Law Sign bit Chord bits Step bits Sign bit Chord bits Step bits (D7) (D6,D5,D4) (D3,D2,D1,D0) (D7) (D6,D5,D4) (D3,D2,D1,D0) + Full Scale 1 000 0000 1 010 1010 + Zero 1 111 1111 1 101 0101 - Zero 0 111 1111 0 101 0101 - Full Scale 0 000 0000 0 010 1010 TABLE 10.64: PCM CODES FOR 0DBM0 OUTPUT μ-Law Sample A-Law Sign bit Chord bits Step bits Sign bit Chord bits Step bits (D7) (D6,D5,D4) (D3,D2,D1,D0) (D7) (D6,D5,D4) (D3,D2,D1,D0) 1 0 001 1110 0 011 0100 2 0 000 1011 0 010 0001 3 0 000 1011 0 010 0001 4 0 001 1110 0 011 0100 5 1 001 1110 1 011 0100 6 1 000 1011 1 010 0001 7 1 000 1011 1 010 0001 8 1 001 1110 1 011 0100 - 28 - W682510/W682310 11. TYPICAL APPLICATION CIRCUIT VDD 0.1μF Power Up Input 1 VREF Channel 2 Analog Output AI2 24 2 RO2 AO2- 23 3 NC AO1- 22 4 RO1 1μF 5 PUI NC 20 6 PCMMS A/μ 19 VSSA 18 8 VDD NC 17 9 VSSD BCLK 16 10 FSR PCM 2 Ch Serial Input Frame Sync Input Channe Analog Input AI1 21 7 NC Channel 1 Analog Output Channe Analog Input W682510/W2310 Bit Clock Input FST 15 11 PCMR2 PCMT2 14 12 PCMR1 PCMT1 13 SOP PCM 2 Ch. Serial Output Ω 1k VDD FIGURE 11.1: APPLICATION CIRCUIT FOR SERIAL MODE OPERATION - 29 - Publication Release Date: April 2005 Revision A10 W682510/W682310 V DD 0.1 μF Power Up Input W682510/W682310 1 VREF AI2 24 2 RO2 AO2 - 23 Channel 2 Analog Output 3 NC AO1 - 22 Channel 1 Analog Output 4 RO1 AI1 21 5 PUI NC 20 6 PCMMS A/ μ 19 VSSA 18 7 NC 1 μF PCM Ch2 Serial Input PCM Ch1 Serial Input Frame Sync Input Channel 1 Analog Input 8 V DD NC 17 9 V SSD BCLK 16 10 FSR FST 15 11 PCMR2 PCMT2 14 12 PCMR1 PCMT1 13 Bit Clock Input PCM Ch2 Serial Output PCM Ch1 Serial Output SOP Ω Ω 1k 1k V DD FIGURE 11.2: APPLICATION CIRCUIT FOR PARALLEL MODE OPERATION - 30 - W682510/W682310 12. PACKAGE DRAWING AND DIMENSIONS 12.1. 20L (PDIP) PLASTIC DUAL INLINE PACKAGE DIMENSIONS (W682510 ONLY) D 2 1 1 E 1 1 E S c 1 2 AA A Base Seating L B e1 eA á B1 DIMENSION (MM) DIMENSION (INCH) SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. A - - 4.45 - - 0.175 A1 0.25 - - 0.010 - - A2 3918 3.30 3.43 0.125 0.130 0.135 B 0.41 0.46 0.56 0.016 0.018 0.022 B1 1.47 1.52 1.63 0.058 0.060 0.064 c 0.20 0.25 0.36 0.008 0.010 0.014 D - 20.06 26.42 - 1.026 1.046 E 7.37 7.62 7.87 0.290 0.300 0.310 E1 6.22 6.35 6.48 0.245 0.250 0.255 e1 2.29 2.54 2.79 0.090 0.100 0.110 L 3.05 3.30 3.56 0.120 0.130 0.140 á 0º - 15º 0º - 15º eA 8.51 9.02 9.53 0.335 0.355 0.375 S - - 1.91 - - 0.075 - 31 - Publication Release Date: April 2005 Revision A10 W682510/W682310 12.2. 20L SSOP – 209 MIL SHRINK SMALL OUTLINE PACKAGE DIMENSIONS D 1 2 DTEAIL A HE E 1 1 b A A SEATING SEATING θ Y e L L b A DETAIL A DIMENSION (MM) DIMENSION (INCH) SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. A - - 2.00 - - 0.079 A1 0.05 - - 0.002 - - A2 1.65 1.75 1.85 0.065 0.069 - b 0.22 - 0.38 0.009 - 0.015 c 0.09 - 0.25 0.004 - 0.010 D 6.90 7.20 7.50 0.272 0.283 0.295 E 5.00 5.30 5.60 0.197 0.209 0.220 HE 7.40 7.80 8.20 0.291 0.307 0.323 e - 0.65 - - 0.0256 - L 0.55 0.75 0.95 0.021 0.030 0.037 L1 - 1.25 - - 0.050 - Y - - 0.10 - - 0.004 0 0º - 8º 0 - 8º - 32 - W682510/W682310 12.3. 24 SOP – 300 MIL 13 24 c E HE L 1 12 D 0.25 O A Y SEATING PLANE e GAUGE PLANE A1 b DIMENSION (MM) DIMENSION (INCH) SYMBOL MIN. MAX. MIN. MAX. A 2.35 2.65 0.093 0.104 A1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 E 7.40 7.60 0.291 0.299 D 15.20 15.60 0.598 0.614 e HE 1.27 BSC 10.00 Y 0.050 BSC 10.65 0.394 0.10 0.419 0.004 L 0.10 1.27 0.016 0.050 0 0º 8º 0 8º - 33 - Publication Release Date: April 2005 Revision A10 W682510/W682310 13. ORDERING INFORMATION Product Number Descriptor Key W682510 _ Package Type: Product Family W682510 Product E = 20-Lead Plastic Dual Inline Package (PDIP) S = 24-Lead Plastic Small Outline Package (SOP) R = 20-Lead Plastic Small Outline Package (SSOP) When ordering W682510 series devices, please refer to the following part numbers. Part Number W682510E W682510S W682510R W682310 _ Product Family W682310 Product Package Type: S = 24-Lead Plastic Small Outline Package (SOP) R = 20-Lead Plastic Small Outline Package (SSOP) When ordering W682310 series devices, please refer to the following part numbers. Part Number W682310S W682310R For the latest product information, access Winbond’s worldwide website at HTTP://WWW.WINBOND-USA.COM - 34 - W682510/W682310 14. VERSION HISTORY VERSION DATE PAGE 0.31 Mar 2003 All 0.34 Apr. 2003 Updates 0.35 May 2003 Frequency response updated A10 April 2005 35 DESCRIPTION Preliminary Specifications Add Important Notice Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 35 - Publication Release Date: April 2005 Revision A10