W78E516B Data Sheet 8-BIT MICROCONTROLLER Table of Contents1. GENERAL DESCRIPTION ......................................................................................................... 3 2. FEATURES ................................................................................................................................. 3 3. PIN CONFIGURATIONS ............................................................................................................ 4 4. PIN DESCRIPTION..................................................................................................................... 5 5. FUNCTIONAL DESCRIPTION ................................................................................................... 6 6. 7. 8. 5.1 RAM ................................................................................................................................ 6 5.2 Timers 0, 1 and 2 ............................................................................................................ 6 5.3 Clock ............................................................................................................................... 7 5.4 Crystal Oscillator............................................................................................................. 7 5.5 External Clock................................................................................................................. 7 5.6 Power Management........................................................................................................ 7 5.7 Reduce EMI Emission .................................................................................................... 7 5.8 Reset............................................................................................................................... 7 5.9 Port 4 .............................................................................................................................. 9 5.10 INT2 / INT3 ...................................................................................................................... 9 5.11 Port 4 Base Address Registers .................................................................................... 12 5.12 In-System Programming (ISP) Mode............................................................................ 14 5.13 In-System Programming Control Register (CHPCON)................................................. 16 SECURITY ................................................................................................................................ 20 6.1 Lock Bit ......................................................................................................................... 20 6.2 MOVC Inhibit................................................................................................................. 20 6.3 Encryption ..................................................................................................................... 21 6.4 Oscillator Control .......................................................................................................... 21 ELECTRICAL CHARACTERISTICS......................................................................................... 22 7.1 Absolute Maximum Ratings .......................................................................................... 22 7.2 D.C. Characteristics...................................................................................................... 22 7.3 A.C. Characteristics ...................................................................................................... 24 TIMING WAVEFORMS ............................................................................................................. 26 8.1 Program Fetch Cycle .................................................................................................... 26 8.2 Data Read Cycle........................................................................................................... 26 8.3 Data Write Cycle ........................................................................................................... 27 -1- Publication Release Date: December 4, 2006 Revision A11 W78E516B 8.4 9. 10. 11. TYPICAL APPLICATION CIRCUITS ........................................................................................ 28 9.1 External Program Memory and Crystal ........................................................................ 28 9.2 Expanded External Data Memory and Oscillator ......................................................... 29 PACKAGE DIMENSIONS ......................................................................................................... 30 10.1 40-pin DIP ..................................................................................................................... 30 10.2 44-pin PLCC ................................................................................................................. 30 10.3 44-pin PQFP ................................................................................................................. 31 APPLICATION NOTE ............................................................................................................... 32 11.1 12. Port Access Cycle......................................................................................................... 27 In-system Programming Software Examples ............................................................... 32 REVISION HISTORY ................................................................................................................ 37 -2- W78E516B 1. GENERAL DESCRIPTION The W78E516B is an 8-bit microcontroller which has an in-system programmable Flash EPROM for firmware updating. The instruction set of the W78E516B is fully compatible with the standard 8052. The W78E516B contains a 64K bytes of main Flash EPROM and a 4K bytes of auxiliary Flash EPROM which allows the contents of the 64KB main Flash EPROM to be updated by the loader program located at the 4KB auxiliary Flash EPROM ROM; 512 bytes of on-chip RAM; four 8-bit bidirectional and bit-addressable I/O ports; an additional 4-bit port P4; three 16-bit timer/counters; a serial port. These peripherals are supported by a eight sources two-level interrupt capability. To facilitate programming and verification, the Flash EPROM inside the W78E516B allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security. The W78E516B microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. The idle mode turns off the processor clock but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption. The external clock can be stopped at any time and in any state without affecting the processor. 2. FEATURES • Fully static design 8-bit CMOS microcontroller up to 40 MHz. • 64K bytes of in-system programmable Flash EPROM for Application Program (APROM). • 4K bytes of auxiliary Flash EPROM for Loader Program (LDROM). • 512 bytes of on-chip RAM. (including 256 bytes of AUX-RAM, software selectable) • 64K bytes program memory address space and 64K bytes data memory address space. • Four 8-bit bi-directional ports. • One 4-bit multipurpose programmable port. • Three 16-bit timer/counters • One full duplex serial port • Six-sources, two-level interrupt capability • Built-in power management • Code protection • Packaged in − Lead Free (ROHS) DIP 40: W78E516B40DL − Lead Free (ROHS) PLCC 44: W78E516B40PL − Lead Free (ROHS) PQFP 44: W78E516B40FL -3- Publication Release Date: December 4, 2006 Revision A11 W78E516B 3. PIN CONFIGURATIONS 40-Pin DIP T2, P1.0 T2EX, P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RXD, P3.0 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 WR, P3.6 RD, P3.7 XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P 1 . 4 P1.5 P1.6 P1.7 RST RXD, P3.0 INT2, P4.3 TXD, P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 P 1 . 3 P 1 . 2 T 2 , P 1 . 0 / I N T 3 , P 4 V . D 2 D A D 0 , P 0 . 0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 P 3 . 7 , / R D X T A L 2 X T A L 1 EA ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 P2.4, A12 P2.3, A11 P2.2, A10 P2.1, A9 P2.0, A8 A D 3 , P 0 . 3 6 5 4 3 2 1 44 43 42 41 40 7 39 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 18 19 20 21 22 23 24 25 26 27 28 P 3 . 6 , / W R P0.0, AD0 P0.1, AD1 P0.2, AD2 P0.3, AD3 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 44-Pin QFP 44-Pin PLCC T 2 E X , P 1 . 1 VDD V S S P 4 . 0 P 2 . 0 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 1 . 4 P1.5 P1.6 P1.7 RST RXD, P3.0 INT2, P4.3 TXD, P3.1 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE INT0, P3.2 PSEN P2.7, A15 P2.6, A14 P2.5, A13 INT1, P3.3 T0, P3.4 T1, P3.5 -4- P 1 . 2 T 2 , P 1 . 0 / I N T 3 , P 4 V . D 2 D A D 0 , P 0 . 0 A D 1 , P 0 . 1 A D 2 , P 0 . 2 A D 3 , P 0 . 3 44 43 42 41 40 39 38 37 36 35 34 33 32 31 3 30 4 29 5 28 6 27 7 26 8 9 25 10 24 23 11 12 13 14 15 16 17 18 19 20 21 22 1 2 P 3 . 6 , / W R P 2 . 4 , A 1 2 P 1 . 3 T 2 E X , P 1 . 1 P 3 . 7 , / R D X T A L 2 X V T S A S L 1 P 4 . 0 P 2 . 0 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 W78E516B 4. PIN DESCRIPTION SYMBOL TYPE DESCRIPTIONS EA I EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the external ROM. The ROM address and data will not be presented on the bus if the EA pin is high. PSEN O H PROGRAM STORE ENABLE: PSEN enables the external ROM data in the Port 0 address/data bus. When internal ROM access is performed, no PSEN strobe signal outputs originate from this pin. ALE O H ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. RST I L RESET: A high on this pin for two machine cycles while the oscillator is running resets the device. XTAL1 I CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an external clock. XTAL2 O CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1. VSS I GROUND: ground potential. VDD I POWER SUPPLY: Supply voltage for operation. P0.0 − P0.7 I/O D PORT 0: Function is the same as that of standard 8052. P1.0 − P1.7 I/O H PORT 1: Function is the same as that of standard 8052. P2.0 − P2.7 I/O H P3.0 − P3.7 I/O H PORT 3: Function is the same as that of the standard 8052. P4.0 − P4.3 I/O H PORT 4: A bi-directional I/O. See details below. PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper address bits for accesses to external memory. * Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain PORT4 Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port address is located at 0D8H with the same function as that of port P1. Example: P4 REG 0D8H MOV P4, #0AH ; Output data "A" through P4.0 − P4.3. MOV A, P4 ; Read P4 status to Accumulator. ORL P4, #00000001B ANL P4, #11111110B -5- Publication Release Date: December 4, 2006 Revision A11 W78E516B 5. FUNCTIONAL DESCRIPTION The W78E516B architecture consists of a core controller surrounded by various registers, four general purpose I/O ports, one special purpose programmable 4-bits I/O port, 512 bytes of RAM, three timer/counters, a serial port and an internal 74373 latch and 74244 buffer which can be switched to port2. The processor supports 111 different opcodes and references both a 64K program address space and a 64K data storage space. 5.1 RAM The internal data RAM in the W78E516B is 512 bytes. It is divided into two banks: 256 bytes of scratchpad RAM and 256 bytes of AUX-RAM. These RAMs are addressed by different ways. • RAM 0H − 7FH can be addressed directly and indirectly as the same as in 8051. Address pointers are R0 and R1 of the selected register bank. • RAM 80H − FFH can only be addressed indirectly as the same as in 8051. Address pointers are R0, R1 of the selected registers bank. • AUX-RAM 0H − FFH is addressed indirectly as the same way to access external data memory with the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and DPTR register. An access to external data memory locations higher than FFH will be performed with the MOVX instruction in the same way as in the 8051. The AUX-RAM is disable after a reset. Setting the bit 4 in CHPCON register will enable the access to AUX-RAM. When AUX-RAM is enabled the instructions of "MOVX @Ri" will always access to on-chip AUX-RAM. When executing from internal program memory, an access to AUX-RAM will not affect the Ports P0, P2, WR and RD . Example, CHPENR CHPCON MOV MOV ORL MOV MOV MOV MOVX REG F6H REG BFH CHPENR, #87H CHPENR, #59H CHPCON, #00010000B CHPENR, #00H R0, #12H A, #34H @R0, A ; enable AUX-RAM ; Write 34h data to 12h address. 5.2 Timers 0, 1 and 2 Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1. -6- W78E516B 5.3 Clock The W78E516B is designed with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used by default. This makes the W78E516B relatively insensitive to duty cycle variations in the clock. 5.4 Crystal Oscillator The W78E516B incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias when the crystal frequency is above 24 MHz. 5.5 External Clock An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock signal should have an input one level of greater than 3.5 volts. 5.6 Power Management Idle Mode Setting the IDL bit in the PCON register enters the idle mode. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs. Power-down Mode When the PD bit in the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a hardware reset or external interrupts INT0 to INT1 when enabled and set to level triggered. 5.7 Reduce EMI Emission The W78E516B allows user to diminish the gain of on-chip oscillator amplifier by using programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the external crystal operating improperly at high frequency above 24 MHz. The value of R and C1, C2 may need some adjustment while running at lower gain. 5.8 Reset The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the W78E516B is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset. -7- Publication Release Date: December 4, 2006 Revision A11 W78E516B W78E516B Special Function Registers (SFRs) and Reset Values F8 FF +B 00000000 F0 CHPENR 00000000 F7 E8 EF +ACC 00000000 +P4 xxxx1111 +PSW 00000000 +T2CON 00000000 XICON 00000000 E0 D8 D0 C8 C0 E7 DF D7 RCAP2L 00000000 RCAP2H 00000000 P4CONA 00000000 P4CONB 00000000 TL2 00000000 SFRAL 00000000 TH2 00000000 SFRAH 00000000 +IP 00000000 +P3 00000000 P43AL 00000000 P43AH 00000000 A8 +IE 00000000 P42AL 00000000 P42AH 00000000 A0 +P2 11111111 98 +SCON 00000000 90 +P1 11111111 88 +TCON 00000000 TMOD 00000000 TL0 00000000 80 +P0 11111111 SP 00000111 DPL 00000000 B8 B0 CF SFRFD 00000000 SFRCN 00000000 CHPCON 0xx00000 C7 BF B7 P2ECON 0000XX00 AF A7 SBUF xxxxxxxx P2EAL 00000000 P2EAH 00000000 9F P41AL 00000000 P41AH 00000000 97 TL1 00000000 TH0 00000000 TH1 00000000 8F DPH 00000000 P40AL 00000000 P40AH 00000000 Notes: 1. The SFRs marked with a plus sign(+) are both byte- and bit-addressable. 2. The text of SFR with bold type characters are extension function registers. -8- PCON 00110000 87 W78E516B 5.9 Port 4 Port 4, address D8H, is a 4-bit multipurpose programmable I/O port. Each bit can be configured individually by software. The Port 4 has four different operation modes. Mode 0: P4.0 − P4.3 is a bi-directional I/O port which is same as port 1. P4.2 and P4.3 also serve as external interrupt INT3 and INT2 if enabled. Mode 1: P4.0 − P4.3 are read strobe signals that are synchronized with RD signal at specified addresses. These signals can be used as chip-select signals for external peripherals. Mode 2: P4.0 − P4.3 are write strobe signals that are synchronized with WR signal at specified addresses. These signals can be used as chip-select signals for external peripherals. Mode 3: P4.0 − P4.3 are read/write strobe signals that are synchronized with RD or WR signal at specified addresses. These signals can be used as chip-select signals for external peripherals. When Port 4 is configured with the feature of chip-select signals, the chip-select signal address range depends on the contents of the SFR P4xAH, P4xAL, P4CONA and P4CONB. The registers P4xAH and P4xAL contain the 16-bit base address of P4.x. The registers P4CONA and P4CONB contain the control bits to configure the Port 4 operation mode. 5.10 INT2 / INT3 Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To set/clear bits in the XICON register, one can use the "SETB ( CLR ) bit" instruction. For example, "SETB 0C2H" sets the EX2 bit of XICON. -9- Publication Release Date: December 4, 2006 Revision A11 W78E516B XICON - external interrupt control (C0H) PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2 PX3: External interrupt 3 priority high if set EX3: External interrupt 3 enable if set IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software PX2: External interrupt 2 priority high if set EX2: External interrupt 2 enable if set IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software Eight-source interrupt information VECTOR ADDRESS POLLING SEQUENCE WITHIN PRIORITY LEVEL ENABLE REQUIRED SETTINGS INTERRUPT TYPE EDGE/LEVEL External Interrupt 0 03H 0 (highest) IE.0 TCON.0 Timer/Counter 0 0BH 1 IE.1 - External Interrupt 1 13H 2 IE.2 TCON.2 Timer/Counter 1 1BH 3 IE.3 - Serial Port 23H 4 IE.4 - Timer/Counter 2 2BH 5 IE.5 - External Interrupt 2 33H 6 XICON.2 XICON.0 External Interrupt 3 3BH 7 (lowest) XICON.6 XICON.3 INTERRUPT SOURCE - 10 - W78E516B P4CONB (C3H) BIT NAME FUNCTION 00: Mode 0. P4.3 is a general purpose I/O port which is the same as Port1. 01: Mode 1. P4.3 is a Read Strobe signal for chip select purpose. The address range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0. 7, 6 P43FUN1 P43FUN0 10: Mode 2. P4.3 is a Write Strobe signal for chip select purpose. The address range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0. 11: Mode 3. P4.3 is a Read/Write Strobe signal for chip select purpose. The address range depends on the SFR P43AH, P43AL, P43CMP1, and P43CMP0. Chip-select signals address comparison: 00: Compare the full address (16 bits length) with the base address register P43AH, P43AL. 5, 4 P43CMP1 01: Compare the 15 high bits (A15 − A1) of address bus with the base address register P43AH, P43AL. P43CMP0 10: Compare the 14 high bits (A15 − A2) of address bus with the base address register P43AH, P43AL. 11: Compare the 8 high bits (A15 − A8) of address bus with the base address register P43AH, P43AL. 3, 2 P42FUN1 P42FUN0 1, 0 P42CMP1 The P4.2 address comparator length control bits which are the similar P42CMP0 definition as P43CMP1, P43CMP0. The P4.2 function control bits which are the similar definition as P43FUN1, P43FUN0. P4CONA (C2H) BIT NAME FUNCTION 7, 6 P41FUN1 The P4.1 function control bits which are the similar definition as P43FUN1, P41FUN0 P43FUN0. 5, 4 P41CMP1 The P4.1 address comparator length control bits which are the similar P41CMP0 definition as P43CMP1, P43CMP0. 3, 2 P40FUN1 The P4.0 function control bits which are the similar definition as P43FUN1, P40FUN0 P43FUN0. 1, 0 P40CMP1 The P4.0 address comparator length control bits which are the similar P40CMP0 definition as P43CMP1, P43CMP0. - 11 - Publication Release Date: December 4, 2006 Revision A11 W78E516B P2ECON (AEH) BIT NAME FUNCTION 7 The active polarity of P4.3 when pin P4.3 is defined as read and/or write strobe signal. = 1: P4.3 is active high when pin P4.3 is defined as read and/or write strobe P43CSINV signal. = 0: P4.3 is active low when pin P4.3 is defined as read and/or write strobe signal. 6 P42CSINV The similarity definition as P43SINV. 5 P41CSINV The similarity definition as P43SINV. 5 P41CSINV The similarity definition as P43SINV. 4 P40CSINV The similarity definition as P43SINV. 3 - Reserve 2 - Reserve 1 - 0 0 - 0 5.11 Port 4 Base Address Registers P40AH, P40AL: The Base address register for comparator of P4.0. P40AH contains the high-order byte of address, P40AL contains the low-order byte of address. P41AH, P41AL: The Base address register for comparator of P4.1. P41AH contains the high-order byte of address, P41AL contains the low-order byte of address. P42AH, P42AL: The Base address register for comparator of P4.2. P42AH contains the high-order byte of address, P42AL contains the low-order byte of address. P43AH, P43AL: The Base address register for comparator of P4.3. P43AH contains the high-order byte of address, P43AL contains the low-order byte of address. - 12 - W78E516B P4 (D8H) BIT NAME FUNCTION 7 - Reserve 6 - Reserve 5 - Reserve 4 - Reserve 3 P43 Port 4 Data bit which outputs to pin P4.3 at mode 0. 2 P42 Port 4 Data bit which outputs to pin P4.2 at mode 0. 1 P41 Port 4 Data bit which outputs to pin P4.1at mode 0. 0 P40 Port 4 Data bit which outputs to pin P4.0 at mode 0. Here is an example to program the P4.0 as a write strobe signal at the I/O port address 1234H − 1237H and positive polarity, and P4.1 − P4.3 are used as general I/O ports. MOV P40AH, #12H MOV P40AL, #34H ; Base I/O address 1234H for P4.0 MOV P4CONA, #00001010B ; P4.0 a write strobe signal and address line A0 and A1 are masked. MOV P4CONB, #00H ; P4.1 − P4.3 as general I/O port which are the same as PORT1 MOV P2ECON, #10H ; Write the P40SINV = 1 to inverse the P4.0 write strobe polarity ; default is negative. Then any instruction MOVX @DPTR, A (with DPTR = 1234H − 1237H) will generate the positive polarity write strobe signal at pin P4.0. And the instruction MOV P4, #XX will output the bit3 to bit1 of data #XX to pin P4.3 − P4.1. - 13 - Publication Release Date: December 4, 2006 Revision A11 W78E516B P4xCSINV P4 REGISTER P4.x DATA I/O RD_CS MUX 4->1 WR_CS READ WRITE RD/WR_CS PIN P4.x ADDRESS BUS P4xFUN0 P4xFUN1 EQUAL REGISTER P4xAL P4xAH Bit Length Selectable comparator P4.x INPUT DATA BUS REGISTER P4xCMP0 P4xCMP1 5.12 In-System Programming (ISP) Mode The W78E516B equips one 64K byte of main Flash EPROM bank for application program (called APROM) and one 4K byte of auxiliary Flash EPROM bank for loader program (called LDROM). In the normal operation, the microcontroller executes the code in the APROM. If the content of APROM needs to be modified, the W78E516B allows user to activate the In-System Programming (ISP) mode by setting the CHPCON register. The CHPCON is read-only by default, software must write two specific values 87H, then 59H sequentially to the CHPENR register to enable the CHPCON write attribute. Writing CHPENR register with the values except 87H and 59H will close CHPCON register write attribute. The W78E516B achieves all in-system programming operations including enter/exit ISP Mode, program, erase, read ... etc, during device in the idle mode. Setting the bit CHPCON.0 the device will enter in-system programming mode after a wake-up from idle mode. Because device needs proper time to complete the ISP operations before awaken from idle mode, software may use timer interrupt to control the duration for device wake-up from idle mode. To perform ISP operation for revising contents of APROM, software located at APROM setting the CHPCON register then enter idle mode, after awaken from idle mode the device executes the corresponding interrupt service routine in LDROM. Because the device will clear the program counter while switching from APROM to LDROM, the first execution of RETI instruction in interrupt service routine will jump to 00H at LDROM area. The device offers a software reset for switching back to APROM while the content of APROM has been updated completely. Setting CHPCON register bit 0, 1 and 7 to logic-1 will result a software reset to reset the CPU. The software reset serves as a external reset. This insystem programming feature makes the job easy and efficient in which the application needs to update firmware frequently. In some applications, the in-system programming feature make it possible to easily update the system firmware without opening the chassis. - 14 - W78E516B SFRAH, SFRAL: The objective address of on-chip Flash EPROM in the in-system programming mode. SFRFAH contains the high-order byte of address, SFRFAL contains the low-order byte of address. SFRFD: The programming data for on-chip Flash EPROM in programming mode. SFRCN: The control byte of on-chip Flash EPROM programming mode. SFRCN (C7) BIT NAME 7 - FUNCTION Reserve. On-chip Flash EPROM bank select for in-system programming. 6 WFWIN = 0: 64K bytes Flash EPROM bank is selected as destination for reprogramming. = 1: 4K bytes Flash EPROM bank is selected as destination for reprogramming. 5 OEN Flash EPROM output enable. 4 CEN Flash EPROM chip enable. 3, 2, 1, 0 CTRL[3:0] MODE The flash control signals WFWIN CTRL<3:0> OEN CEN SFRAH, SFRAL SFRFD Erase 64KB APROM 0 0010 1 0 X X Program 64KB APROM 0 0001 1 0 Address in Data in Read 64KB APROM 0 0000 0 0 Address in Data out Erase 4KB LDROM 1 0010 1 0 X X Program 4KB LDROM 1 0001 1 0 Address in Data in Read 4KB LDROM 1 0000 0 0 Address in Data out - 15 - Publication Release Date: December 4, 2006 Revision A11 W78E516B 5.13 In-System Programming Control Register (CHPCON) CHPCON (BFH) BIT 7 NAME FUNCTION When this bit is set to 1, and both FBOOTSL and FPROGEN are set to 1. It SWRESET will enforce microcontroller reset to initial condition just like power on reset. (F04KMODE) This action will re-boot the microcontroller and start to normal operation. To read this bit in logic-1 can determine that the F04KBOOT mode is running. 6 - Reserve. 5 - Reserve. 4 ENAUXRAM 3 0 Must set to 0. 2 0 Must set to 0. 1: Enable on-chip AUX-RAM. 0: Disable the on-chip AUX-RAM The Program Location Select. 1 FBOOTSL 0: The Loader Program locates at the 64 KB APROM. 4KB LDROM is destination for re-programming. 1: The Loader Program locates at the 4 KB memory bank. 64KB APROM is destination for re-programming. FLASH EPROM Programming Enable. 0 = 1: enable. The microcontroller enter the in-system programming mode after entering the idle mode and wake-up from interrupt. During in-system FPROGEN programming mode, the operation of erase, program and read are achieve when device enters idle mode. = 0: disable. The on-chip flash memory is read-only. In-system programmability is disabled. F04KBOOT Mode (Boot from LDROM) By default, the W78E516B boots from APROM program after a power on reset. On some occasions, user can force the W78E516B to boot from the LDROM program via following settings. The possible situation that you need to enter F04KBOOT mode when the APROM program can not run properly and device can not jump back to LDROM to execute in-system programming function. Then you can use this F04KBOOT mode to force the W78E516B jumps to LDROM and executes in-system programming procedure. When you design your system, you may reserve the pins P2.6, P2.7 to switches or jumpers. For example in a CD-ROM system, you can connect the P2.6 and P2.7 to PLAY and EJECT buttons on the panel. When the APROM program fails to execute the normal application program. User can press both two buttons at the same time and then turn on the power of the personal computer to force the W78E516B to enter the F04KBOOT mode. After power on of personal computer, you can release both buttons and finish the in-system programming procedure to update the APROM code. In application system design, user must take care of the P2, P3, ALE, EA and PSEN pin value at reset to prevent from accidentally activating the programming mode or F04KBOOT mode. - 16 - W78E516B F04KBOOT MODE P4.3 P2.7 P2.6 MODE X L L FO4KBOOT L X X FO4KBOOT The Reset Timing For Entering F04KBOOT Mode P2.7 Hi-Z P2.6 Hi-Z RST 30 mS 10 mS - 17 - Publication Release Date: December 4, 2006 Revision A11 W78E516B The Algorithm of In-System Programming Part 1:64KB APROM procedure of entering In-System Programming Mode START Enter In-System Programming Mode ? (conditions depend on user's application) No Yes Setting control registers MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#03H Execute the normal application program Setting Timer (about 1.5 us) and enable timer interrupt END Start Timer and enter idle Mode. (CPU will be wakened from idle mode by timer interrupt, then enter In-System Programming mode) CPU will be wakened by interrupt and re-boot from 4KB LDROM to execute the loader program. Go - 18 - W78E516B Part 2: 4KB LDROM Go Procedure of Updating the 64KB APROM Timer Interrupt Service Routine: Stop Timer & disable interrupt PGM Yes Yes Is F04KBOOT Mode? (CHPCON.7=1) End of Programming ? No No Reset the CHPCON Register: MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#03H Setting Timer and enable Timer interrupt for wake-up . (50us for program operation) Yes Is currently in the F04KBOOT Mode ? No Get the parameters of new code Setting Timer and enable Timer interrupt for wake-up . (15 ms for erasing operation) Setting erase operation mode: MOV SFRCN,#22H (Erase 64KB APROM) Start Timer and enter IDLE Mode. (Erasing...) (Address and data bytes) through I/O ports, UART or other interfaces. Software reset CPU and re-boot from the 64KB APROM. MOV CHPENR,#87H MOV CHPENR,#59H MOV CHPCON,#83H Setting control registers for programming: Hardware Reset to re-boot from new 64 KB APROM. (S/W reset is invalid in F04KBOOT Mode) MOV SFRAH,#ADDRESS_H MOV SFRAL,#ADDRESS_L MOV SFRFD,#DATA MOV SFRCN,#21H End of erase operation. CPU will be wakened by Timer interrupt. END Executing new code from address 00H in the 64KB APROM. PGM - 19 - Publication Release Date: December 4, 2006 Revision A11 W78E516B 6. SECURITY During the on-chip Flash EPROM programming mode, the Flash EPROM can be programmed and verified repeatedly. Until the code inside the Flash EPROM is confirmed OK, the code can be protected. The protection of Flash EPROM and those operations on it are described below. The W78E516B has a Special Setting Register, the Security Register, which can not be accessed in programming mode. Those bits of the Security Register can not be changed once they have been programmed from high to low. They can only be reset through erase-all operation. The Security Register is located at the 0FFFFH of the LDROM space. D7 D6 D5 D4 D3 D2 D1 D0 B7 Reserved B2 B1 B0 4KB Flash EPROM Security Bits Program Memory LDROM B0: Lock bit, logic 0: active B1: MOVC inhibit, logic 0: the MOVC instruction in external memory cannot access the code in internal memory. logic 1: no restriction. 0000h 0FFFh 64KB Flash EPROM Program Memory APROM Reserved Reserved B2: Encryption logic 0: the encryption logic enable logic 1: the encryption logic disable B07: Osillator Control logic 0: 1/2 gain logic 1: Full gain Default 1 for all security bits. Reserved bits must be kept in logic 1. Security Register FFFFh Special Setting Register 6.1 Lock Bit This bit is used to protect the customer's program code in the W78E516B. It may be set after the programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the Flash EPROM data and Special Setting Registers can not be accessed again. 6.2 MOVC Inhibit This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC instruction in external program memory from reading the internal program code. When this bit is set to logic 0, a MOVC instruction in external program memory space will be able to access code only in the external memory, not in the internal memory. A MOVC instruction in internal program memory space will always be able to access the ROM data in both internal and external memory. If this bit is logic 1, there are no restrictions on the MOVC instruction. - 20 - W78E516B 6.3 Encryption This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will reset this bit. 6.4 Oscillator Control W78E516B/E516 allow user to diminish the gain of on-chip oscillator amplifier by using programmer to set the bit B7 of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may improperly affect the external crystal operation at high frequency above 24 MHz. The value of R and C1, C2 may need some adjustment while running at lower gain. - 21 - Publication Release Date: December 4, 2006 Revision A11 W78E516B 7. ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings PARAMETER SYMBOL MIN. MAX. UNIT VDD − VSS -0.3 +6.0 V Input Voltage VIN VSS -0.3 VDD +0.3 V Operating Temperature TA 0 70 °C Storage Temperature TST -55 +150 °C DC Power Supply Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 7.2 D.C. Characteristics (VDD − VSS = 5V ±10%, TA = 25°C, Fosc = 20 MHz, unless otherwise specified.) PARAMETER SPECIFICATION SYM. TEST CONDITIONS MIN. MAX. UNIT Operating Voltage VDD 4.5 5.5 V Operating Current IDD - 20 mA No load VDD = 5.5V IIDLE - 6 mA Idle mode VDD = 5.5V IPWDN - 50 μA Power-down mode VDD = 5.5V Input Current P1, P2, P3, P4 IIN1 -50 +10 μA VDD = 5.5V VIN = 0V or VDD Input Current RST IIN2 -10 +300 μA VDD = 5.5V 0< VIN <VDD Input Leakage Current P0, EA ILK -10 +10 μA VDD = 5.5V 0V< VIN < VDD Logic 1 to 0 Transition Current P1, P2, P3, P4 ITL[*4] -500 - μA VDD = 5.5V VIN = 2.0V Input Low Voltage P0, P1, P2, P3, P4, EA VIL1 0 0.8 V VDD = 4.5V VIL2 0 0.8 V VDD = 4.5V VIL3 0 0.8 V VDD = 4.5V Idle Current Power Down Current Input Low Voltage RST Input Low Voltage XTAL1[*4] - 22 - RST = 1, P0 = VDD W78E516B D.C. Characteristics, continued PARAMETER SPECIFICATION SYM. TEST CONDITIONS MIN. MAX. UNIT VIH1 2.4 VDD +0.2 V VDD = 5.5V VIH2 3.5 VDD +0.2 V VDD = 5.5V VIH3 3.5 VDD +0.2 V VDD = 5.5V VOL1 - 0.45 V VOL2 - 0.45 V Isk1 4 12 mA Isk2 10 20 mA VOH1 2.4 - V VOH2 2.4 - V Isr1 -120 -250 μA Isr2 -8 -20 mA Input High Voltage P0, P1, P2, P3, P4, EA Input High Voltage RST Input High Voltage XTAL1[*4] Output Low Voltage P1, P2, P3, P4 Output Low Voltage P0, ALE, PSEN [*3] Sink Current P1, P3, P4 Sink Current P0, P2, ALE, PSEN Output High Voltage P1, P2, P3, P4 Output High Voltage P0, ALE, PSEN [*3] Source Current P1, P2, P3, P4 Source Current P0, P2, ALE, PSEN VDD = 4.5V IOL = +2 mA VDD = 4.5V IOL = +4 mA VDD = 4.5V VIN = 0.45V VDD = 4.5V VIN = 0.45V VDD = 4.5V IOH = -100 μA VDD = 4.5V IOH = -400 μA VDD = 4.5V VIN = 2.4V VDD = 4.5V VIN = 2.4V Notes: *1. RST pin is a Schmitt trigger input. *3. P0, ALE and PSEN are tested in the external access mode. *4. XTAL1 is a CMOS input. *5. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN approximates to 2V. - 23 - Publication Release Date: December 4, 2006 Revision A11 W78E516B 7.3 A.C. Characteristics The AC specifications are a function of the particular process used to manufacture the part, the ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually experience less than a ±20 nS variation. The numbers below represent the performance expected from a 0.6 micron CMOS process when using 2 and 4 mA output buffers. 7.3.1 Clock Input Waveform XTAL1 T CH T CL F OP, PARAMETER TCP SYMBOL MIN. TYP. MAX. UNIT NOTES Operating Speed Fop 0 - 40 MHz 1 Clock Period TCP 25 - - nS 2 Clock High Tch 10 - - nS 3 Clock Low Tcl 10 - - nS 3 Notes: 1. The clock may be stopped indefinitely in either state. 2. The TCP specification is used as a reference in other specifications. 3. There are no duty cycle requirements on the XTAL1 input. 7.3.2 Program Fetch Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES Address Valid to ALE Low TAAS 1 TCP-Δ - - nS 4 Address Hold from ALE Low TAAH 1 TCP-Δ - - nS 1, 4 ALE Low to PSEN Low TAPL 1 TCP-Δ - - nS 4 PSEN Low to Data Valid TPDA - - 2 TCP nS 2 Data Hold after PSEN High TPDH 0 - 1 TCP nS 3 Data Float after PSEN High TPDZ 0 - 1 TCP nS ALE Pulse Width TALW 2 TCP-Δ 2 TCP - nS 4 PSEN Pulse Width TPSW 3 TCP-Δ 3 TCP - nS 4 Notes: 1. P0.0 − P0.7, P2.0 − P2.7 remain stable throughout entire memory cycle. 2. Memory access time is 3 TCP. 3. Data have been latched internally prior to PSEN going high. 4. "Δ" (due to buffer driving delay and wire loading) is 20 nS. - 24 - W78E516B 7.3.3 Data Read Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES ALE Low to RD Low TDAR 3 TCP-Δ - 3 TCP+Δ nS 1, 2 RD Low to Data Valid TDDA - - 4 TCP nS 1 Data Hold from RD High TDDH 0 - 2 TCP nS Data Float from RD High TDDZ 0 - 2 TCP nS RD Pulse Width TDRD 6 TCP-Δ 6 TCP - nS 2 Notes: 1. Data memory access time is 8 TCP. 2. "Δ" (due to buffer driving delay and wire loading) is 20 nS. 7.3.4 Data Write Cycle PARAMETER SYMBOL MIN. TYP. MAX. UNIT ALE Low to WR Low TDAW 3 TCP-Δ - 3 TCP+Δ nS Data Valid to WR Low TDAD 1 TCP-Δ - - nS Data Hold from WR High TDWD 1 TCP-Δ - - nS WR Pulse Width TDWR 6 TCP-Δ 6 TCP - nS SYMBOL MIN. TYP. MAX. UNIT Port Input Setup to ALE Low TPDS 1 TCP - - nS Port Input Hold from ALE Low TPDH 0 - - nS Port Output to ALE TPDA 1 TCP - - nS Note: "Δ" (due to buffer driving delay and wire loading) is 20 nS. 7.3.5 Port Access Cycle PARAMETER Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to ALE, since it provides a convenient reference. - 25 - Publication Release Date: December 4, 2006 Revision A11 W78E516B 8. TIMING WAVEFORMS 8.1 Program Fetch Cycle S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 XTAL1 TALW ALE TAPL PSEN TPSW TAAS PORT 2 TPDA TAAH TPDH, TPDZ PORT 0 Code A0-A7 Data A0-A7 Code A0-A7 Data A0-A7 8.2 Data Read Cycle S4 S5 S6 S1 S2 S3 S4 S5 S6 XTAL1 ALE PSEN PORT 2 A8-A15 DATA A0-A7 PORT 0 T DAR T DDA RD T DRD - 26 - T DDH, T DDZ S1 S2 S3 W78E516B Timing Waveforms, continued 8.3 Data Write Cycle S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 XTAL1 ALE PSEN PORT 2 A8-A15 PORT 0 A0-A7 DATA OUT T DWD TDAD WR T DWR T DAW 8.4 Port Access Cycle S5 S6 S1 XTAL1 ALE TPDS T PDA TPDH DATA OUT PORT INPUT SAMPLE - 27 - Publication Release Date: December 4, 2006 Revision A11 W78E516B 9. TYPICAL APPLICATION CIRCUITS 9.1 External Program Memory and Crystal V DD 31 XTAL1 18 XTAL2 9 RST 12 13 14 15 INT0 INT1 T0 T1 1 2 3 4 5 6 7 8 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 10 u R CRYSTAL 8.2 K C1 EA 19 C2 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 39 AD0 38 AD1 37 AD2 36 AD3 35 AD4 34 AD5 33 AD6 32 AD7 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 21 22 23 24 25 26 27 28 GND RD WR PSEN ALE TXD RXD 17 16 29 30 11 10 A8 A9 A10 A11 A12 A13 A14 A15 3 4 7 8 13 14 17 18 1 11 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 A0 A1 A2 A3 A4 A5 A6 A7 OC G 74LS373 A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 A10 21 A11 23 A12 2 A13 26 A14 27 A15 1 GND 20 22 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 11 12 13 15 16 17 18 19 O0 O1 O2 O3 O4 O5 O6 O7 CE OE 27512 W78E516B Figure A CRYSTAL C1 C2 R 6 MHz 47P 47P - 16 MHz 30P 30P - 24 MHz 15P 10P - 32 MHz 10P 10P 6.8K 40 MHz 5P 5P 4.7K Above table shows the reference values for crystal applications. Notes: 1. C1, C2, R components refer to Figure A 2. Crystal layout must get close to XTAL1 and XTAL2 pins on user's application board. - 28 - AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 W78E516B Typical Application Circuits, continued 9.2 Expanded External Data Memory and Oscillator v DD VDD 31 19 10 u 8.2 K OSCILLATOR EA XTAL1 18 XTAL2 9 RST 12 13 14 15 1 2 3 4 5 6 7 8 INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 39 38 37 36 35 34 33 32 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 21 22 23 24 25 26 27 28 A8 A9 A10 A11 A12 A13 A14 RD WR 17 16 29 30 11 10 PSEN ALE TXD RXD AD0 3 AD1 4 AD2 7 AD3 8 AD4 13 AD5 14 AD6 17 AD7 18 GND 1 11 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 OC G 74LS373 2 5 6 9 12 15 16 19 A0 A1 A2 A3 A4 A5 A6 A7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 GND 20 22 27 CE OE WR D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 20256 W78E516B Figure B - 29 - Publication Release Date: December 4, 2006 Revision A11 W78E516B 10. PACKAGE DIMENSIONS 10.1 40-pin DIP Symbol A A1 A2 B B1 c D E E1 e1 L D 40 21 E1 Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max. 20 1 0.254 0.150 0.155 0.160 3.81 3.937 4.064 0.016 0.018 0.022 0.406 0.457 0.559 0.048 0.050 0.054 1.219 1.27 1.372 0.008 0.010 0.014 0.203 0.254 0.356 0.590 2.055 2.070 52.20 52.58 0.600 0.610 14.986 15.24 15.494 0.540 0.545 0.550 13.72 13.84 13.97 0.090 0.100 0.110 2.286 2.54 2.794 0.120 0.130 0.140 3.048 3.302 3.556 15 0 0.670 16.00 16.51 17.01 0 a eA S 5.334 0.210 0.010 0.630 0.650 15 0.090 2.286 Notes: E S 1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimension D & E1 include mold mismatch and . parting line. are determined at the mold 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. c A A2 A1 Base Plane Seating Plane L B e1 eA a B1 10.2 44-pin PLCC HD D 6 1 44 40 Symbol 39 7 E 17 HE GE 29 18 28 c A A1 A2 b1 b c D E e GD GE HD HE L y Dimension in inch Min. Nom. Max. Dimension in mm Min. Nom. Max. 0.185 0.020 4.699 0.508 0.145 0.150 0.155 0.026 0.028 0.032 0.016 0.018 0.022 0.008 0.010 0.014 0.203 0.254 0.356 0.648 0.653 0.658 16.46 16.59 16.71 16.46 16.59 16.71 0.648 0.653 0.050 0.658 BSC 3.81 3.937 0.66 0.711 0.813 0.406 0.457 0.559 3.683 1.27 0.590 0.610 0.630 14.99 15.49 16.00 0.590 0.610 0.630 14.99 15.49 16.00 0.680 0.690 0.700 17.27 17.53 17.78 0.680 0.690 0.700 17.27 17.53 17.78 0.090 0.100 0.110 2.296 2.54 2.794 0.004 L Notes: A2 A 1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec. θ e b b1 Seating Plane A1 y GD - 30 - BSC 0.10 W78E516B Package Dimensions, continued. 10.3 44-pin PQFP HD D Symbol 34 44 A A1 A2 b c D E e HD HE L L1 y θ 33 1 E HE 11 12 e b 22 Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max. --- --- --- --- 0.002 0.01 0.02 0.05 0.25 0.5 0.075 0.081 0.087 1.90 2.05 2.20 0.01 0.014 0.018 0.25 0.35 0.45 0.004 0.006 0.010 0.101 0.152 0.254 0.390 0.394 0.398 9.9 10.00 10.1 0.390 0.394 0.398 9.9 10.00 10.1 0.025 0.031 0.036 0.635 0.80 0.952 0.510 0.520 0.530 12.95 13.2 13.45 0.510 0.520 0.530 12.95 13.2 13.45 0.025 0.031 0.037 0.65 0.8 0.95 0.051 0.063 0.075 1.295 1.6 1.905 --- 0.08 0.003 0 7 --- 0 7 Notes: 1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeter 4. General appearance spec. should be based on final visual inspection spec. c A2 A A1 Seating Plane See Detail F y θ L L1 Detail F - 31 - Publication Release Date: December 4, 2006 Revision A11 W78E516B 11. APPLICATION NOTE 11.1 In-system Programming Software Examples This application note illustrates the in-system programmability of the Winbond W78E516B Flash EPROM microcontroller. In this example, microcontroller will boot from 64 KB APROM bank and waiting for a key to enter in-system programming mode for re-programming the contents of 64 KB APROM. While entering in-system programming mode, microcontroller executes the loader program in 4KB LDROM bank. The loader program erases the 64 KB APROM then reads the new code data from external SRAM buffer (or through other interfaces) to update the 64KB APROM. EXAMPLE 1: ;******************************************************************************************************************* ;* Example of 64K APROM program: Program will scan the P1.0. if P1.0 = 0, enters in-system ;* programming mode for updating the content of APROM code else executes the current ROM code. ;* XTAL = 40 MHz ;******************************************************************************************************************* .chip 8052 .RAMCHK OFF .symbols CHPCON CHPENR SFRAL SFRAH SFRFD SFRCN EQU EQU EQU EQU EQU EQU BFH F6H C4H C5H C6H C7H ORG 0H LJMP 100H ; JUMP TO MAIN PROGRAM ;************************************************************************ ;* TIMER0 SERVICE VECTOR ORG = 000BH ;************************************************************************ ORG 00BH CLR TR0 ; TR0 = 0, STOP TIMER0 MOV TL0, R6 MOV TH0, R7 RETI ;************************************************************************ ;* 64K APROM MAIN PROGRAM ;************************************************************************ ORG 100H MAIN_64K: MOV A, P1 ; SCAN P1.0 ANL A, #01H CJNE A, #01H, PROGRAM_64K ; IF P1.0 = 0, ENTER IN-SYSTEM PROGRAMMING MODE JMP NORMAL_MODE PROGRAM_64K: MOV CHPENR, #87H MOV CHPENR, #59H MOV CHPCON, #03H MOV TCON, #00H ; CHPENR = 87H, CHPCON REGISTER WRTE ENABLE ; CHPENR = 59H, CHPCON REGISTER WRITE ENABLE ; CHPCON = 03H, ENTER IN-SYSTEM PROGRAMMING MODE ; TR = 0 TIMER0 STOP - 32 - W78E516B MOV IP, #00H MOV IE, #82H MOV R6, #F0H MOV R7, #FFH MOV TL0, R6 MOV TH0, R7 MOV TMOD, #01H MOV TCON, #10H MOV PCON, #01H ; IP = 00H ; TIMER0 INTERRUPT ENABLE FOR WAKE-UP FROM IDLE MODE ; TL0 = F0H ; TH0 = FFH ; TMOD = 01H, SET TIMER0 A 16-BIT TIMER ; TCON = 10H, TR0 = 1,GO ; ENTER IDLE MODE FOR LAUNCHING THE IN-SYSTEM ; PROGRAMMABILITY ;******************************************************************************** ;* Normal mode 64KB APROM program: depending user's application ;******************************************************************************** NORMAL_MODE: . ; User's application program . . . EXAMPLE 2: ;***************************************************************************************************************************** ;* Example of 4KB LDROM program: This lorder program will erase the 64KB APROM first, then reads the new ;* code from external SRAM and program them into 64KB APROM bank. XTAL = 40 MHz ;***************************************************************************************************************************** .chip 8052 .RAMCHK OFF .symbols CHPCON CHPENR SFRAL SFRAH SFRFD SFRCN ORG LJMP EQU EQU EQU EQU EQU EQU 000H 100H BFH F6H C4H C5H C6H C7H ; JUMP TO MAIN PROGRAM ;************************************************************************ ;* 1. TIMER0 SERVICE VECTOR ORG = 0BH ;************************************************************************ ORG 000BH CLR TR0 ; TR0 = 0, STOP TIMER0 MOV TL0, R6 MOV TH0, R7 RETI ;************************************************************************ ;* 4KB LDROM MAIN PROGRAM ;************************************************************************ ORG 100H - 33 - Publication Release Date: December 4, 2006 Revision A11 W78E516B MAIN_4K: MOV SP, #C0H ; BE INITIAL SP REGISTER MOV CHPENR, #87H ; CHPENR = 87H, CHPCON WRITE ENABLE. MOV CHPENR, #59H ; CHPENR = 59H, CHPCON WRITE ENABLE. MOV A, CHPCON ANL A, #80H CJNE A, #80H, UPDATE_64K ; CHECK F04KBOOT MODE ? MOV CHPCON, #03H MOV CHPENR, #00H ; CHPCON = 03H, ENABLE IN-SYSTEM PROGRAMMING. ; DISABLE CHPCON WRITE ATTRIBUTE MOV TCON, #00H MOV TMOD, #01H MOV IP, #00H MOV IE, #82H MOV R6, #F0H MOV R7, #FFH MOV TL0, R6 MOV TH0, R7 MOV TCON, #10H MOV PCON, #01H ; TCON = 00H, TR = 0 TIMER0 STOP ; TMOD = 01H, SET TIMER0 A 16BIT TIMER ; IP = 00H ; IE = 82H, TIMER0 INTERRUPT ENABLED UPDATE_64K: MOV CHPENR, #00H MOV TCON, #00H MOV IP, #00H MOV IE, #82H MOV TMOD, #01H MOV R6, #3CH ; TCON = 10H, TR0 = 1, GO ; ENTER IDLE MODE ; DISABLE CHPCON WRITE-ATTRIBUTE ; TCON = 00H, TR = 0 TIM0 STOP ; IP = 00H ; IE = 82H, TIMER0 INTERRUPT ENABLED ; TMOD = 01H, MODE1 ; SET WAKE-UP TIME FOR ERASE OPERATION, ABOUT 15 mS. DEPENDING ; ON USER'S SYSTEM CLOCK RATE. MOV R7, #B0H MOV TL0, R6 MOV TH0, R7 ERASE_P_4K: MOV SFRCN, #22H MOV TCON, #10H MOV PCON, #01H ; SFRCN(C7H) = 22H ERASE 64K ; TCON = 10H, TR0 = 1,GO ; ENTER IDLE MODE (FOR ERASE OPERATION) ;********************************************************************* ;* BLANK CHECK ;********************************************************************* MOV SFRCN, #0H ; READ 64KB APROM MODE MOV SFRAH, #0H ; START ADDRESS = 0H MOV SFRAL, #0H MOV R6, #FBH ; SET TIMER FOR READ OPERATION, ABOUT 1.5 μS. MOV R7, #FFH MOV TL0, R6 MOV TH0, R7 BLANK_CHECK_LOOP: SETB TR0 ; ENABLE TIMER 0 MOV PCON, #01H ; ENTER IDLE MODE MOV A, SFRFD ; READ ONE BYTE CJNE A, #FFH, BLANK_CHECK_ERROR - 34 - W78E516B INC SFRAL ; NEXT ADDRESS MOV A, SFRAL JNZ BLANK_CHECK_LOOP INC SFRAH MOV A, SFRAH CJNE A, #0H, BLANK_CHECK_LOOP ; END ADDRESS = FFFFH JMP PROGRAM_64KROM BLANK_CHECK_ERROR: MOV P1, #F0H MOV P3, #F0H JMP $ ;******************************************************************************* ;* RE-PROGRAMMING 64KB APROM BANK ;******************************************************************************* PROGRAM_64KROM: MOV DPTR, #0H ; THE ADDRESS OF NEW ROM CODE MOV R2, #00H ; TARGET LOW BYTE ADDRESS MOV R1, #00H ; TARGET HIGH BYTE ADDRESS MOV DPTR, #0H ; EXTERNAL SRAM BUFFER ADDRESS MOV SFRAH, R1 ; SFRAH, TARGET HIGH ADDRESS MOV SFRCN, #21H ; SFRCN (C7H) = 21 (PROGRAM 64K) MOV R6, #5AH ; SET TIMER FOR PROGRAMMING, ABOUT 50 μS. MOV R7, #FFH MOV TL0, R6 MOV TH0, R7 PROG_D_64K: MOV SFRAL, R2 ; SFRAL (C4H) = LOW BYTE ADDRESS MOVX A, @DPTR ; READ DATA FROM EXTERNAL SRAM BUFFER MOV SFRFD, A ; SFRFD (C6H) = DATA IN MOV TCON, #10H ; TCON = 10H, TR0 = 1, GO MOV PCON, #01H ; ENTER IDLE MODE (PRORGAMMING) INC DPTR INC R2 CJNE R2, #0H, PROG_D_64K INC R1 MOV SFRAH, R1 CJNE R1, #0H, PROG_D_64K ;***************************************************************************** ; * VERIFY 64KB APROM BANK ;***************************************************************************** MOV R4, #03H ; ERROR COUNTER MOV R6, #FBH ; SET TIMER FOR READ VERIFY, ABOUT 1.5 μS. MOV R7, #FFH MOV TL0, R6 MOV TH0, R7 MOV DPTR, #0H ; The start address of sample code MOV R2, #0H ; Target low byte address MOV R1, #0H ; Target high byte address MOV SFRAH, R1 ; SFRAH, Target high address MOV SFRCN, #00H ; SFRCN = 00 (Read ROM CODE) - 35 - Publication Release Date: December 4, 2006 Revision A11 W78E516B READ_VERIFY_64K: MOV SFRAL, R2 ; SFRAL (C4H) = LOW ADDRESS MOV TCON, #10H ; TCON = 10H, TR0 = 1, GO MOV PCON, #01H INC R2 MOVX A, @DPTR INC DPTR CJNE A, SFRFD, ERROR_64K CJNE R2, #0H, READ_VERIFY_64K INC R1 MOV SFRAH, R1 CJNE R1, #0H, READ_VERIFY_64K ;****************************************************************************** ;* PROGRAMMING COMPLETLY, SOFTWARE RESET CPU ;****************************************************************************** MOV CHPENR, #87H ; CHPENR = 87H MOV CHPENR, #59H ; CHPENR = 59H MOV CHPCON, #83H ; CHPCON = 83H, SOFTWARE RESET. ERROR_64K: DJNZ R4, UPDATE_64K . . . . ; IF ERROR OCCURS, REPEAT 3 TIMES. ; IN-SYSTEM PROGRAMMING FAIL, USER'S PROCESS TO DEAL WITH IT. - 36 - W78E516B 12. REVISION HISTORY VERSION DATE PAGE DESCRIPTION A5 June, 2002 - Formerly issued A6 June, 2004 3 Revise part number in the item of packages A7 Aug, 2004 26 Revise title of 10.1 A8 Jan, 2005 3 Add Lead Free package A9 April 20, 2005 35 Add Important Notice A10 October 2, 2006 A11 December 4, 2006 Remove block diagram 3 Remove all Leaded package parts Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 37 - Publication Release Date: December 4, 2006 Revision A11