37 XA Spartan-3E Automotive FPGA Family Data Sheet R DS635 (v2.0) September 9, 2009 0 Product Specification Summary The Xilinx® Automotive (XA) Spartan®-3E family of FPGAs is specifically designed to meet the needs of high-volume, cost-sensitive automotive electronics applications. The five-member family offers densities ranging from 100,000 to 1.6 million system gates, as shown in Table 1. • Introduction XA devices are available in both extended-temperature Q-Grade (–40°C to +125°C TJ) and I-Grade (–40°C to +100°C TJ) and are qualified to the industry recognized AEC-Q100 standard. The XA Spartan-3E family builds on the success of the earlier XA Spartan-3 family by increasing the amount of logic per I/O, significantly reducing the cost per logic cell. New features improve system performance and reduce the cost of configuration. These XA Spartan-3E FPGA enhancements, combined with advanced 90 nm process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry. Because of their exceptionally low cost, XA Spartan-3E FPGAs are ideally suited to a wide range of automotive applications, including infotainment, driver information, and driver assistance modules. The XA Spartan-3E family is a superior alternative to mask programmed ASICs and ASSPs. FPGAs avoid the high initial mask set costs and lengthy development cycles, while also permitting design upgrades in the field with no hardware replacement necessary because of its inherent programmability, an impossibility with conventional ASICs and ASSPs with their inflexible hardware architecture. Features • • • Very low-cost, high-performance logic solution for high-volume automotive applications Proven advanced 90-nanometer process technology Multi-voltage, multi-standard SelectIO™ interface pins - Up to 376 I/O pins or 156 differential signal pairs - LVCMOS, LVTTL, HSTL, and SSTL single-ended signal standards - 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling - 622+ Mb/s data transfer rate per I/O - True LVDS, RSDS, mini-LVDS, differential HSTL/SSTL differential I/O • • • • • • • • - Enhanced Double Data Rate (DDR) support - DDR SDRAM support up to 266 Mb/s Abundant, flexible logic resources - Densities up to 33,192 logic cells, including optional shift register or distributed RAM support - Efficient wide multiplexers, wide logic - Fast look-ahead carry logic - Enhanced 18 x 18 multipliers with optional pipeline - IEEE 1149.1/1532 JTAG programming/debug port Hierarchical SelectRAM™ memory architecture - Up to 648 Kbits of fast block RAM - Up to 231 Kbits of efficient distributed RAM Up to eight Digital Clock Managers (DCMs) - Clock skew elimination (delay locked loop) - Frequency synthesis, multiplication, division - High-resolution phase shifting - Wide frequency range (5 MHz to over 300 MHz) Eight global clocks plus eight additional clocks per each half of device, plus abundant low-skew routing Configuration interface to industry-standard PROMs - Low-cost, space-saving SPI serial Flash PROM - x8 or x8/x16 parallel NOR Flash PROM Complete Xilinx ISE® and WebPACK™ software support MicroBlaze™ and PicoBlaze™ embedded processor cores Fully compliant 32-/64-bit 33 MHz PCI™ technology support Low-cost QFP and BGA packaging options - Common footprints support easy density migration Refer to Spartan-3E FPGA Family: Complete Data Sheet (DS312) for a full product description, AC and DC specifications, and package pinout descriptions. Any values shown specifically in this XA Spartan-3E Automotive FPGA Family data sheet override those shown in DS312. For information regarding reliability qualification, refer to RPT081 (Xilinx Spartan-3E Family Automotive Qualification Report) and RPT012 (Spartan-3/3E UMC-12A 90 nm Qualification Report). © 2007–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 1 R Key Feature Differences from Commercial XC Devices • • • • • AEC-Q100 device qualification and full production part approval process (PPAP) documentation support available in both extended temperature I- and Q-Grades Guaranteed to meet full electrical specification over the TJ = –40°C to +125°C temperature range (Q-Grade) XA Spartan-3E devices are available in the -4 speed grade only. PCI-66 is not supported in the XA Spartan-3E FPGA product line. The readback feature is not supported in the XA • • • • • • Spartan-3E FPGA product line. XA Spartan-3E devices are available in Step 1 only. JTAG configuration frequency reduced from 30 MHz to 25 MHz. Platform Flash is not supported within the XA family. XA Spartan-3E devices are available in Pb-free packaging only. MultiBoot is not supported in XA versions of this product. The XA Spartan-3E device must be power cycled prior to reconfiguration. Table 1: Summary of XA Spartan-3E FPGA Attributes Device CLB Array (One CLB = Four Slices) Equivalent Total Total Logic System Rows Columns CLBs Slices Cells Gates Distributed RAM bits(1) Block RAM bits(1) Dedicated Multipliers DCMs Maximum Maximum Differential I/O Pairs User I/O XA3S100E 100K 2,160 22 16 240 960 15K 72K 4 2 108 40 XA3S250E 250K 5,508 34 26 612 2,448 38K 216K 12 4 172 68 XA3S500E 500K 10,476 46 34 1,164 4,656 73K 360K 20 4 190 77 XA3S1200E 1200K 19,512 60 46 2,168 8,672 136K 504K 28 8 304 124 XA3S1600E 1600K 33,192 76 58 3,688 14,752 231K 648K 36 8 376 156 Notes: 1. By convention, one Kb is equivalent to 1,024 bits. Architectural Overview The XA Spartan-3E family architecture consists of five fundamental programmable functional elements: • • • • Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables (LUTs) that implement logic plus storage elements used as flip-flops or latches. CLBs perform a wide variety of logical functions as well as store data. Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. Each IOB supports bidirectional data flow plus 3-state operation. Supports a variety of signal standards, including four high-performance differential standards. Double Data-Rate (DDR) registers are included. Block RAM provides data storage in the form of 18-Kbit dual-port blocks. Multiplier Blocks accept two 18-bit binary numbers as inputs and calculate the product. DS635 (v2.0) September 9, 2009 Product Specification • Digital Clock Manager (DCM) Blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals. These elements are organized as shown in Figure 1. A ring of IOBs surrounds a regular array of CLBs. Each device has two columns of block RAM except for the XA3S100E, which has one column. Each RAM column consists of several 18-Kbit RAM blocks. Each block RAM is associated with a dedicated multiplier. The DCMs are positioned in the center with two at the top and two at the bottom of the device. The XA3S100E has only one DCM at the top and bottom, while the XA3S1200E and XA3S1600E add two DCMs in the middle of the left and right sides. The XA Spartan-3E family features a rich network of traces that interconnect all five functional elements, transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections to the routing. www.xilinx.com 2 R Notes: 1. The XA3S1200E and XA3S1600E have two additional DCMs on both the left and right sides as indicated by the dashed lines. The XA3S100E has only one DCM at the top and one at the bottom. Figure 1: XA Spartan-3E Family Architecture Configuration I/O Capabilities XA Spartan-3E FPGAs are programmed by loading configuration data into robust, reprogrammable, static CMOS configuration latches (CCLs) that collectively control all functional elements and routing resources. The FPGA’s configuration data is stored externally in a PROM or some other non-volatile medium, either on or off the board. After applying power, the configuration data is written to the FPGA using any of five different modes: The XA Spartan-3E FPGA SelectIO interface supports many popular single-ended and differential standards. Table 2 shows the number of user I/Os as well as the number of differential I/O pairs available for each device/package combination. • • • • • Serial Peripheral Interface (SPI) from an industry-standard SPI serial Flash Byte Peripheral Interface (BPI) Up or Down from an industry-standard x8 or x8/x16 parallel NOR Flash Slave Serial, typically downloaded from a processor Slave Parallel, typically downloaded from a processor Boundary Scan (JTAG), typically downloaded from a processor or system tester. DS635 (v2.0) September 9, 2009 Product Specification XA Spartan-3E FPGAs support the following single-ended standards: • • • • • 3.3V low-voltage TTL (LVTTL) Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V, 1.5V, or 1.2V 3V PCI at 33 MHz HSTL I and III at 1.8V, commonly used in memory applications SSTL I at 1.8V and 2.5V, commonly used for memory applications www.xilinx.com 3 R XA Spartan-3E FPGAs support the following differential standards: • • • • LVDS Bus LVDS mini-LVDS RSDS • • • Differential HSTL (1.8V, Types I and III) Differential SSTL (2.5V and 1.8V, Type I) 2.5V LVPECL inputs Table 2: Available User I/Os and Differential (Diff) I/O Pairs Package VQG100 CPG132 TQG144 PQG208 FTG256 FGG400 FGG484 Size (mm) 16 x 16 8x8 22 x 22 28 x 28 17 x 17 21 x 21 23 x 23 Device User Diff User Diff User Diff User Diff User Diff User Diff User Diff XA3S100E 66 (7) 30 (2) 83 (11) 35 (2) 108 (28) 40 (4) - - - - - - - - XA3S250E 66 (7) 30 (2) 92 (7) 41 (2) 108 (28) 40 (4) 158 (32) 65 (5) 172 (40) 68 (8) - - - - XA3S500E - - 92 (7) 41 (2) - - 158 (32) 65 (5) 190 (41) 77 (8) - - - - XA3S1200E - - - - - - - - 190 (40) 77 (8) 304 (72) 124 (20) - - XA3S1600E - - - - - - - - - - 304 (72) 124 (20) 376 (82) 156 (21) Notes: 1. 2. All XA Spartan-3E devices provided in the same package are pin-compatible as further described in Module 4: Pinout Descriptions of DS312. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number of input-only pins. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 4 R Package Marking for the quad-flat packages, except that the marking is rotated with respect to the ball A1 indicator. Figure 4 shows the top marking for XA Spartan-3E FPGAs in the CPG132 package. Figure 2 provides a top marking example for XA Spartan-3E FPGAs in the quad-flat packages. Figure 3 shows the top marking for XA Spartan-3E FPGAs in BGA packages except the 132-ball chip-scale package (CPG132). The markings for the BGA packages are nearly identical to those Note: No marking is shown for stepping. Mask Revision Code Fabrication Code R SPARTAN R Process Technology Device Type Package XA3S250E TM PQG208AGQ0525 D1234567A Date Code Speed Grade 4I Lot Code Temperature Range Pin P1 DS635-1_02_082807 Figure 2: XA Spartan-3E FPGA QFP Package Marking Example Mask Revision Code BGA Ball A1 R SPARTAN R XA3S250ETM FTG256AGQ0525 FTG256AGQ0525 D1234567A D1234567A 4I Device Type Package Fabrication Code Process Code Date Code Lot Code Speed Grade Temperature Range DS635_03_082807 Figure 3: XA Spartan-3E FPGA BGA Package Marking Example Ball A1 Lot Code 3S250E F1234567-0525 PHILIPPINES Package C6 = CPG132 C6AGQ Mask Revision Code Device Type Date Code Temperature Range 4I Speed Grade Process Code Fabrication Code DS635_04_082807 Figure 4: XA Spartan-3E FPGA CPG132 Package Marking Example DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 5 R Ordering Information XA Spartan-3E FPGAs are available in Pb-free packaging options for all device/package combinations. All devices are in Pb-free packages only, with a “G” character to the ordering code. All devices are available in either I-Grade or Q-Grade temperature ranges. Only the -4 speed grade is available for the XA Spartan-3E family. See Table 2 for valid device/package combinations. Pb-Free Packaging Example: XA3S250E -4 FT G 256 I Device Type Temperature Range: I = I-Grade (TJ = –40oC to 100oC) Q = Q-Grade (TJ = –40oC to 125oC) Number of Pins Pb-free Speed Grade Package Type DS635_06_121608 Device XA3S100E Speed Grade -4 Only Package Type / Number of Pins Temperature Range ( TJ ) VQG100 100-pin Very Thin Quad Flat Pack (VQFP) I I-Grade (–40°C to 100°C) XA3S250E CPG132 132-ball Chip-Scale Package (CSP) Q Q-Grade (–40°C to 125°C) XA3S500E TQG144 144-pin Thin Quad Flat Pack (TQFP) XA3S1200E PQG208 208-pin Plastic Quad Flat Pack (PQFP) XA3S1600E FTG256 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA) FGG400 400-ball Fine-Pitch Ball Grid Array (FBGA) FGG484 484-ball Fine-Pitch Ball Grid Array (FBGA) DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 6 R Power Supply Specifications Table 3: Supply Voltage Thresholds for Power-On Reset Symbol Description Min Max Units VCCINTT Threshold for the VCCINT supply 0.4 1.0 V VCCAUXT Threshold for the VCCAUX supply 0.8 2.0 V VCCO2T Threshold for the VCCO Bank 2 supply 0.4 1.0 V Notes: 1. 2. VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source. To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with no dips at any point. Table 4: Supply Voltage Ramp Rate Symbol Description Min Max Units VCCINTR Ramp rate from GND to valid VCCINT supply level 0.2 50 ms VCCAUXR Ramp rate from GND to valid VCCAUX supply level 0.2 50 ms VCCO2R Ramp rate from GND to valid VCCO Bank 2 supply level 0.2 50 ms Notes: 1. 2. VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (SPI Flash, parallel NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source. To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with no dips at any point. Table 5: Supply Voltage Levels Necessary for Preserving RAM Contents Symbol Description Min Units VDRINT VCCINT level required to retain RAM data 1.0 V VDRAUX VCCAUX level required to retain RAM data 2.0 V Notes: 1. RAM contents include configuration data. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 7 R DC Specifications Table 6: General Recommended Operating Conditions Symbol TJ (1) VCCAUX ΔVCCAUX (2) VIN(3,4,5,6) TIN Min Nominal Max Units I-Grade –40 25 100 °C Q-Grade –40 25 125 °C Internal supply voltage 1.140 1.200 1.260 V Output driver supply voltage 1.100 - 3.465 V Auxiliary supply voltage 2.375 2.500 2.625 V - - 10 mV/ms I/O, Input-only, and Dual-Purpose pins(3) –0.5 – VCCO + 0.5 V Dedicated pins(4) –0.5 – VCCAUX + 0.5 V – – 500 ns Junction temperature VCCINT VCCO Description Voltage variance on VCCAUX when using a DCM Input voltage extremes to avoid turning on I/O protection diodes Input signal transition time(7) Notes: 1. 2. 3. 4. 5. 6. 7. This VCCO range spans the lowest and highest operating voltages for all supported I/O standards. Table 9 lists the recommended VCCO range specific to each of the single-ended I/O standards, and Table 11 lists that specific to the differential standards. Only during DCM operation is it recommended that the rate of change of VCCAUX not exceed 10 mV/ms. Each of the User I/O and Dual-Purpose pins is associated with one of the four banks’ VCCO rails. Meeting the VIN limit ensures that the internal diode junctions that exist between these pins and their associated VCCO and GND rails do not turn on. See Absolute Maximum Ratings in DS312). All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail (2.5V). Meeting the VIN max limit ensures that the internal diode junctions that exist between each of these pins and the VCCAUX and GND rails do not turn on. Input voltages outside the recommended range is permissible provided that the IIK input clamp diode rating is met and no more than 100 pins exceed the range simultaneously. See Absolute Maximum Ratings in DS312). See XAPP459, "Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins." Measured between 10% and 90% VCCO. Follow Signal Integrity recommendations. General DC Characteristics for I/O Pins Table 7: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins Symbol IL IRPU(2) RPU(2) Description Leakage current at User I/O, Input-only, Dual-Purpose, and Dedicated pins Current through pull-up resistor at User I/O, Dual-Purpose, Input-only, and Dedicated pins Equivalent pull-up resistor value at User I/O, Dual-Purpose, Input-only, and Dedicated pins (based on IRPU per Note 2) DS635 (v2.0) September 9, 2009 Product Specification Test Conditions Min Typ Max Units Driver is in a high-impedance state, VIN = 0V or VCCO max, sample-tested –10 – +10 μA VIN = 0V, VCCO = 3.3V –0.36 – –1.24 mA VIN = 0V, VCCO = 2.5V –0.22 – –0.80 mA VIN = 0V, VCCO = 1.8V –0.10 – –0.42 mA VIN = 0V, VCCO = 1.5V –0.06 – –0.27 mA VIN = 0V, VCCO = 1.2V –0.04 – –0.22 mA VIN = 0V, VCCO = 3.0V to 3.465V 2.4 – 10.8 kΩ VIN = 0V, VCCO = 2.3V to 2.7V 2.7 – 11.8 kΩ VIN = 0V, VCCO = 1.7V to 1.9V 4.3 – 20.2 kΩ VIN = 0V, VCCO =1.4V to 1.6V 5.0 – 25.9 kΩ VIN = 0V, VCCO = 1.14V to 1.26V 5.5 – 32.0 kΩ www.xilinx.com 8 R Table 7: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins (Continued) Symbol Description Test Conditions Min Typ Max Units IRPD(2) Current through pull-down resistor at User I/O, Dual-Purpose, Input-only, and Dedicated pins VIN = VCCO 0.10 – 0.75 mA RPD(2) Equivalent pull-down resistor value at User I/O, Dual-Purpose, Input-only, and Dedicated pins (based on IRPD per Note 2) VIN = VCCO = 3.0V to 3.45V 4.0 – 34.5 kΩ VIN = VCCO = 2.3V to 2.7V 3.0 – 27.0 kΩ VIN = VCCO = 1.7V to 1.9V 2.3 – 19.0 kΩ VIN = VCCO = 1.4V to 1.6V 1.8 – 16.0 kΩ VIN = VCCO = 1.14V to 1.26V 1.5 – 12.6 kΩ All VCCO levels –10 – +10 μA - – – 10 pF VOCM Min ≤ VICM ≤ VOCM Max VOD Min ≤ VID ≤ VOD Max VCCO = 2.5V – 120 – Ω IREF VREF current per pin CIN Input capacitance RDT Resistance of optional differential termination circuit within a differential I/O pair. Not available on Input-only pairs. Notes: 1. 2. The numbers in this table are based on the conditions set forth in Table 6. This parameter is based on characterization. The pull-up resistance RPU = VCCO / IRPU. The pull-down resistance RPD = VIN / IRPD. Table 8: Quiescent Supply Current Characteristics Symbol ICCINTQ ICCOQ Description Quiescent VCCINT supply current Quiescent VCCO supply current DS635 (v2.0) September 9, 2009 Product Specification I-Grade Maximum Q-Grade Maximum Units XA3S100E 36 58 mA XA3S250E 104 158 mA XA3S500E 145 300 mA XA3S1200E 324 500 mA XA3S1600E 457 750 mA XA3S100E 1.5 2.0 mA XA3S250E 1.5 3.0 mA XA3S500E 1.5 3.0 mA XA3S1200E 2.5 4.0 mA XA3S1600E 2.5 4.0 mA Device www.xilinx.com 9 R Table 8: Quiescent Supply Current Characteristics (Continued) Symbol ICCAUXQ Description Quiescent VCCAUX supply current I-Grade Maximum Q-Grade Maximum Units XA3S100E 13 22 mA XA3S250E 26 43 mA XA3S500E 34 63 mA XA3S1200E 59 100 mA XA3S1600E 86 150 mA Device Notes: 1. 2. 3. 4. The numbers in this table are based on the conditions set forth in Table 6. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads disabled. Typical values are characterized using typical devices at room temperature (TJ of 25°C at VCCINT = 1.2 V, VCCO = 3.3V, and VCCAUX = 2.5V). The maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum voltage limits with VCCINT = 1.26V, VCCO = 3.465V, and VCCAUX = 2.625V. The FPGA is programmed with a “blank” configuration data file (i.e., a design with no functional elements instantiated). For conditions other than those described above, (e.g., a design including functional elements), measured quiescent current levels may be different than the values in the table. For more accurate estimates for a specific design, use the Xilinx XPower tools. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The Spartan-3E XPower Estimator provides quick, approximate, typical estimates, and does not require a netlist of the design. b) XPower Analyzer uses a netlist as input to provide maximum estimates as well as more accurate typical estimates. The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 10 R Single-Ended I/O Standards Table 9: Recommended Operating Conditions for User I/Os Using Single-Ended Standards IOSTANDARD Attribute VCCO for Drivers(2) VREF Min (V) Nom (V) Max (V) VIL VIH Max (V) Min (V) Min (V) Nom (V) Max (V) LVTTL 3.0 3.3 3.465 0.8 2.0 LVCMOS33(4) 3.0 3.3 3.465 0.8 2.0 LVCMOS25(4,5) 2.3 2.5 2.7 0.7 1.7 0.4 0.8 VREF is not used for these I/O standards LVCMOS18 1.65 1.8 1.95 LVCMOS15 1.4 1.5 1.6 0.4 0.8 LVCMOS12 1.1 1.2 1.3 0.4 0.7 PCI33_3 3.0 3.3 3.465 0.3 * VCCO 0.5 * VCCO HSTL_I_18 1.7 1.8 1.9 0.8 0.9 1.1 VREF - 0.1 VREF + 0.1 HSTL_III_18 1.7 1.8 1.9 - 1.1 - VREF - 0.1 VREF + 0.1 SSTL18_I 1.7 1.8 1.9 0.833 0.900 0.969 VREF - 0.125 VREF + 0.125 SSTL2_I 2.3 2.5 2.7 1.15 1.25 1.35 VREF - 0.125 VREF + 0.125 Notes: 1. 2. 3. 4. 5. 6. Descriptions of the symbols used in this table are as follows: VCCO – the supply voltage for output drivers VREF – the reference voltage for setting the input switching threshold VIL – the input voltage that indicates a Low logic level VIH – the input voltage that indicates a High logic level The VCCO rails supply only output drivers, not input circuits. For device operation, the maximum signal voltage (VIH max) may be as high as VIN max. See Table 72 in DS312. There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards. All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) use the LVCMOS25 standard and draw power from the VCCAUX rail (2.5V). The Dual-Purpose configuration pins use the LVCMOS standard before the User mode. When using these pins as part of a standard 2.5V configuration interface, apply 2.5V to the VCCO lines of Banks 0, 1, and 2 at power-on as well as throughout configuration. For information on PCI IP solutions, see www.xilinx.com/pci. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 11 R Table 10: DC Characteristics of User I/Os Using Single-Ended Standards (Continued) Table 10: DC Characteristics of User I/Os Using Single-Ended Standards Test Conditions LVCMOS33(3) LVCMOS25(3) LVCMOS18(3) LVCMOS15(3) Logic Level Characteristics IOL IOH (mA) (mA) VOL Max (V) VOH Min (V) 2 –2 0.4 VCCO - 0.4 PCI33_3(4) 1.5 –0.5 10% VCCO 90% VCCO –6 HSTL_I_18 8 –8 0.4 VCCO - 0.4 8 –8 HSTL_III_18 24 –8 0.4 VCCO - 0.4 12 12 –12 SSTL18_I 6.7 –6.7 VTT – 0.475 VTT + 0.475 16 16 –16 SSTL2_I 8.1 –8.1 VTT – 0.61 VTT + 0.61 2 2 –2 4 4 –4 1. 6 6 –6 2. 8 8 –8 12 12 –12 16 16 –16 2 2 –2 4 4 –4 6 6 –6 8 8 –8 12 12 –12 2 2 –2 4 4 –4 6 6 –6 8 8 –8 2 2 –2 4 4 –4 6 6 –6 IOL IOH (mA) (mA) VOL Max (V) VOH Min (V) 2 2 –2 0.4 2.4 4 4 –4 6 6 8 IOSTANDARD Attribute LVTTL(3) Test Conditions Logic Level Characteristics DS635 (v2.0) September 9, 2009 Product Specification 0.4 IOSTANDARD Attribute LVCMOS12(3) VCCO – 0.4 2 Notes: The numbers in this table are based on the conditions set forth in Table 6 and Table 9. Descriptions of the symbols used in this table are as follows: IOL – the output current condition under which VOL is tested IOH – the output current condition under which VOH is tested VOL – the output voltage that indicates a Low logic level VOH – the output voltage that indicates a High logic level VCCO – the supply voltage for output drivers VTT – the voltage applied to a resistor termination 0.4 VCCO – 0.4 3. 4. 0.4 VCCO – 0.4 0.4 VCCO – 0.4 For the LVCMOS and LVTTL standards: the same VOL and VOH limits apply for both the Fast and Slow slew attributes. Tested according to the relevant PCI specifications. For information on PCI IP solutions, see www.xilinx.com/pci. www.xilinx.com 12 R Differential I/O Standards Table 11: Recommended Operating Conditions for User I/Os Using Differential Signal Standards VCCO for Drivers(1) IOSTANDARD Attribute VID VICM Min (V) Nom (V) Max (V) Min (mV) Nom (mV) Max (mV) Min (V) Nom (V) Max (V) LVDS_25 2.375 2.50 2.625 100 350 600 0.30 1.25 2.20 BLVDS_25 2.375 2.50 2.625 100 350 600 0.30 1.25 2.20 MINI_LVDS_25 2.375 2.50 2.625 200 - 600 0.30 - 2.2 100 800 1000 0.5 1.2 2.0 LVPECL_25(2) Inputs Only RSDS_25 2.375 2.50 2.625 100 200 - 0.3 1.20 1.4 DIFF_HSTL_I_18 1.7 1.8 1.9 100 - - 0.8 - 1.1 DIFF_HSTL_III_18 1.7 1.8 1.9 100 - - 0.8 - 1.1 DIFF_SSTL18_I 1.7 1.8 1.9 100 - - 0.7 - 1.1 DIFF_SSTL2_I 2.3 2.5 2.7 100 - - 1.0 - 1.5 VOH VOL Notes: 1. 2. The VCCO rails supply only differential output drivers, not input circuits. VREF inputs are not used for any of the differential I/O standards. Table 12: DC Characteristics of User I/Os Using Differential Signal Standards ΔVOD VOD IOSTANDARD Attribute Min (mV) Typ (mV) ΔVOCM VOCM Max (mV) Min (mV) Max (mV) Min (V) Typ (V) Max (V) Min (mV) Max (mV) Min (V) Max (V) LVDS_25 250 350 450 – – 1.125 – 1.375 – – – – BLVDS_25 250 350 450 – – – 1.20 – – – – – MINI_LVDS_25 300 – 600 – 50 1.0 – 1.4 – 50 – – RSDS_25 100 – 400 – – 1.1 – 1.4 – – – – DIFF_HSTL_I_18 – – – – – – – – – – VCCO – 0.4 0.4 DIFF_HSTL_III_18 – – – – – – – – – – VCCO – 0.4 0.4 DIFF_SSTL18_I – – – – – – – – – – VTT + 0.475 VTT – 0.475 DIFF_SSTL2_I – – – – – – – – – – VTT + 0.61 VTT – 0.61 Notes: 1. 2. 3. The numbers in this table are based on the conditions set forth in Table 6, and Table 11. Output voltage measurements for all differential standards are made with a termination resistor (RT) of 100Ω across the N and P pins of the differential signal pair. The exception is for BLVDS, shown in Figure 5 below. At any given time, no more than two of the following differential output standards may be assigned to an I/O bank: LVDS_25, RSDS_25, MINI_LVDS_25 DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 13 R 1/4th of Bourns Part Number CAT16-LV4F12 VCCO = 2.5V 1/4th of Bourns Part Number CAT16-PT4F4 VCCO = 2.5V Z0 = 50Ω 165Ω 140Ω Z0 = 50Ω 100Ω 165Ω DS635_05_082807 Figure 5: External Termination Resistors for BLVDS Transmitter and BLVDS Receiver Switching Characteristics I/O Timing Table 13: Pin-to-Pin Clock-to-Output Times for the IOB Output Path -4 Speed Grade Symbol Description Conditions When reading from the Output Flip-Flop (OFF), the time from the active transition on the Global Clock pin to data appearing at the Output pin. The DCM is used. LVCMOS25(2), 12mA output drive, Fast slew rate, with DCM(3) Max Units XA3S100E 2.79 ns XA3S250E 3.45 ns XA3S500E 3.46 ns XA3S1200E 3.46 ns XA3S1600E 3.45 ns XA3S100E 5.92 ns XA3S250E 5.43 ns XA3S500E 5.51 ns XA3S1200E 5.94 ns XA3S1600E 6.05 ns Device Clock-to-Output Times TICKOFDCM TICKOF When reading from OFF, the time from the active transition on the Global Clock pin to data appearing at the Output pin. The DCM is not used. LVCMOS25(2), 12mA output drive, Fast slew rate, without DCM Notes: 1. 2. 3. 4. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in Table 6 and Table 9. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate Input adjustment from Table 17. If the latter is true, add the appropriate Output adjustment from Table 18. DCM output jitter is included in all measurements. For minimums, use the values reported by the Xilinx timing analyzer. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 14 R Table 14: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous) Symbol Description Conditions IFD_ DELAY_ VALUE= -4 Speed Grade Device Min Units XA3S100E 2.98 ns XA3S250E 2.59 ns XA3S500E 2.59 ns XA3S1200E 2.58 ns XA3S1600E 2.59 ns Setup Times TPSDCM TPSFD When writing to the Input Flip-Flop (IFF), the time from the setup of data at the Input pin to the active transition at a Global Clock pin. The DCM is used. No Input Delay is programmed. LVCMOS25(2), IFD_DELAY_VALUE = 0, with DCM(4) When writing to IFF, the time from the setup of data at the Input pin to an active transition at the Global Clock pin. The DCM is not used. The Input Delay is programmed. LVCMOS25(2), 2 XA3S100E 3.58 ns IFD_DELAY_VALUE = default software setting 3 XA3S250E 3.91 ns 2 XA3S500E 4.02 ns 5 XA3S1200E 5.52 ns 4 XA3S1600E 4.46 ns 0 XA3S100E –0.52 ns XA3S250E 0.14 ns XA3S500E 0.14 ns XA3S1200E 0.15 ns XA3S1600E 0.14 ns 0 Hold Times TPHDCM TPHFD When writing to IFF, the time from the active transition at the Global Clock pin to the point when data must be held at the Input pin. The DCM is used. No Input Delay is programmed. LVCMOS25(3), IFD_DELAY_VALUE = 0, with DCM(4) When writing to IFF, the time from the active transition at the Global Clock pin to the point when data must be held at the Input pin. The DCM is not used. The Input Delay is programmed. LVCMOS25(3), 2 XA3S100E –0.24 ns IFD_DELAY_VALUE = default software setting 3 XA3S250E –0.32 ns 2 XA3S500E –0.49 ns 5 XA3S1200E –0.63 ns 4 XA3S1600E –0.39 ns Notes: 1. 2. 3. 4. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in Table 6 and Table 9. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 17. If this is true of the data Input, add the appropriate Input adjustment from the same table. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 17. If this is true of the data Input, subtract the appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active edge. DCM output jitter is included in all measurements. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 15 R Table 15: Setup and Hold Times for the IOB Input Path Symbol Description Conditions -4 Speed Grade IFD_ DELAY_ VALUE Device Min Units All 2.12 ns Setup Times TIOPICK Time from the setup of data at the Input pin to the active transition at the ICLK input of the Input Flip-Flop (IFF). No Input Delay is programmed. LVCMOS25(2), IFD_DELAY_VALUE = 0 0 TIOPICKD Time from the setup of data at the Input pin to the active transition at the IFF’s ICLK input. The Input Delay is programmed. LVCMOS25(2), IFD_DELAY_VALUE = default software setting 2 XA3S100E 6.49 ns 3 XA3S250E 6.85 ns 2 XA3S500E 7.01 ns 5 XA3S1200E 8.67 ns 4 XA3S1600E 7.69 ns –0.76 ns Hold Times TIOICKP Time from the active transition at the IFF’s ICLK input to the point where data must be held at the Input pin. No Input Delay is programmed. LVCMOS25(2), IFD_DELAY_VALUE = 0 0 TIOICKPD Time from the active transition at the IFF’s ICLK input to the point where data must be held at the Input pin. The Input Delay is programmed. LVCMOS25(2), IFD_DELAY_VALUE = default software setting 2 XA3S100E –3.93 ns 3 XA3S250E –3.51 ns 2 XA3S500E –3.74 ns 5 XA3S1200E –4.30 ns 4 XA3S1600E –4.14 ns 1.80 ns All Set/Reset Pulse Width TRPW_IOB Minimum pulse width to SR control input on IOB All Notes: 1. 2. 3. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in Table 6 and Table 9. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the appropriate Input adjustment from Table 17. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract the appropriate Input adjustment from Table 17. When the hold time is negative, it is possible to change the data before the clock’s active edge. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 16 R Table 16: Propagation Times for the IOB Input Path Symbol -4 Speed Grade IFD_ DELAY_ VALUE Device Max Units All 2.25 ns Description Conditions TIOPLI The time it takes for data to travel from the Input pin through the IFF latch to the I output with no input delay programmed LVCMOS25(2), IFD_DELAY_VALUE = 0 0 TIOPLID The time it takes for data to travel from the Input pin through the IFF latch to the I output with the input delay programmed LVCMOS25(2), IFD_DELAY_VALUE = default software setting 2 XA3S100E 5.97 ns 3 XA3S250E 6.33 ns 2 XA3S500E 6.49 ns 5 XA3S1200E 8.15 ns 4 XA3S1600E 7.16 ns Propagation Times Notes: 1. 2. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in Table 6 and Table 9. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is true, add the appropriate Input adjustment from Table 17. Table 17: Input Timing Adjustments by IOSTANDARD Convert Input Time from LVCMOS25 to the Following Signal Standard (IOSTANDARD) Table 17: Input Timing Adjustments by IOSTANDARD Add the Adjustment Below -4 Speed Grade Convert Input Time from LVCMOS25 to the Following Signal Standard (IOSTANDARD) Units Add the Adjustment Below -4 Speed Grade Units Differential Standards Single-Ended Standards LVTTL 0.43 ns LVDS_25 0.49 ns LVCMOS33 0.43 ns BLVDS_25 0.39 ns LVCMOS25 0 ns MINI_LVDS_25 0.49 ns LVCMOS18 0.98 ns LVPECL_25 0.27 ns LVCMOS15 0.63 ns RSDS_25 0.49 ns LVCMOS12 0.27 ns DIFF_HSTL_I_18 0.49 ns PCI33_3 0.42 ns DIFF_HSTL_III_18 0.49 ns HSTL_I_18 0.12 ns DIFF_SSTL18_I 0.30 ns HSTL_III_18 0.17 ns DIFF_SSTL2_I 0.32 ns SSTL18_I 0.30 ns Notes: ns 1. SSTL2_I 0.15 2. DS635 (v2.0) September 9, 2009 Product Specification The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in Table 6, Table 9, and Table 11. These adjustments are used to convert input path times originally specified for the LVCMOS25 standard to times that correspond to other signal standards. www.xilinx.com 17 R Table 18: Output Timing Adjustments for IOB (Continued) Table 18: Output Timing Adjustments for IOB Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Add the Adjustment Below -4 Speed Grade Slow Units 2 mA 5.24 ns ns 4 mA 3.21 ns 2.49 ns 1.90 ns LVCMOS18 Fast LVCMOS33 Slow Fast LVCMOS25 Slow Fast 2 mA 5.41 Add the Adjustment Below -4 Speed Grade Units Single-Ended Standards LVTTL Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Slow 4 mA 2.41 ns 6 mA 6 mA 1.90 ns 8 mA 8 mA 0.67 ns Fast 2 mA 4.15 ns 2.13 ns 1.14 ns 12 mA 0.70 ns 4 mA 16 mA 0.43 ns 6 mA 2 mA 5.00 ns 4 mA 1.96 ns 6 mA 1.45 ns 8 mA 0.34 ns LVCMOS15 Slow Fast 8 mA 0.75 ns 2 mA 4.68 ns 4 mA 3.97 ns 6 mA 3.11 ns 2 mA 3.38 ns 12 mA 0.30 ns 16 mA 0.30 ns 4 mA 2.70 ns 6 mA 1.53 ns Slow 2 mA 6.63 ns Fast 2 mA 2 mA 5.29 ns 4 mA 1.89 ns 6 mA 1.04 ns LVCMOS12 4.44 ns 0.34 ns 0.55 ns 8 mA 0.69 ns HSTL_I_18 12 mA 0.42 ns HSTL_III_18 16 mA 0.43 ns PCI33_3 0.46 ns 0.25 ns –0.20 ns 2 mA 4.87 ns SSTL18_I 4 mA 1.52 ns SSTL2_I 6 mA 0.39 ns Differential Standards 8 mA 0.34 ns LVDS_25 –0.55 ns 12 mA 0.30 ns BLVDS_25 0.04 ns 16 mA 0.30 ns MINI_LVDS_25 –0.56 ns Input Only ns –0.48 ns 2 mA 4.21 ns LVPECL_25 4 mA 2.26 ns RSDS_25 6 mA 1.52 ns DIFF_HSTL_I_18 0.42 ns 0.55 ns 8 mA 1.08 ns DIFF_HSTL_III_18 12 mA 0.68 ns DIFF_SSTL18_I 0.40 ns 2 mA 3.67 ns DIFF_SSTL2_I 0.44 ns 4 mA 1.72 ns Notes: 6 mA 0.46 ns 1. 8 mA 0.21 ns 12 mA 0 ns DS635 (v2.0) September 9, 2009 Product Specification 2. The numbers in this table are tested using the methodology presented in Table 19 and are based on the operating conditions set forth in Table 6, Table 9, and Table 11. These adjustments are used to convert output- and three-state-path times originally specified for the LVCMOS25 standard with 12 mA drive and Fast slew rate to times that correspond to other signal standards. Do not adjust times that measure when outputs go into a high-impedance state. www.xilinx.com 18 R Table 19: Test Methods for Timing Measurement at I/Os Signal Standard (IOSTANDARD) Inputs Inputs and Outputs Outputs VREF (V) VL (V) VH (V) RT (Ω) VT (V) VM (V) LVTTL - 0 3.3 1M 0 1.4 LVCMOS33 - 0 3.3 1M 0 1.65 LVCMOS25 - 0 2.5 1M 0 1.25 LVCMOS18 - 0 1.8 1M 0 0.9 LVCMOS15 - 0 1.5 1M 0 0.75 LVCMOS12 - 0 1.2 1M 0 0.6 - Note 3 Note 3 25 0 0.94 25 3.3 2.03 Single-Ended PCI33_3 Rising Falling HSTL_I_18 0.9 VREF – 0.5 VREF + 0.5 50 0.9 VREF HSTL_III_18 1.1 VREF – 0.5 VREF + 0.5 50 1.8 VREF SSTL18_I 0.9 VREF – 0.5 VREF + 0.5 50 0.9 VREF SSTL2_I 1.25 VREF – 0.75 VREF + 0.75 50 1.25 VREF LVDS_25 - VICM – 0.125 VICM + 0.125 50 1.2 VICM BLVDS_25 - VICM – 0.125 VICM + 0.125 1M 0 VICM MINI_LVDS_25 - VICM – 0.125 VICM + 0.125 50 1.2 VICM LVPECL_25 - VICM – 0.3 VICM + 0.3 1M 0 VICM RSDS_25 - VICM – 0.1 VICM + 0.1 50 1.2 VICM DIFF_HSTL_I_18 - VREF – 0.5 VREF + 0.5 50 0.9 VICM DIFF_HSTL_III_18 - VREF – 0.5 VREF + 0.5 50 1.8 VICM DIFF_SSTL18_I - VREF – 0.5 VREF + 0.5 50 0.9 VICM DIFF_SSTL2_I - VREF – 0.5 VREF + 0.5 50 1.25 VICM Differential Notes: 1. 2. 3. Descriptions of the relevant symbols are as follows: VREF – The reference voltage for setting the input switching threshold VICM – The common mode input voltage VM – Voltage of measurement point on signal transition VL – Low-level test voltage at Input pin VH – High-level test voltage at Input pin RT – Effective termination resistance, which takes on a value of 1MΩ when no parallel termination is required VT – Termination voltage The load capacitance (CL) at the Output pin is 0 pF for all signal standards. According to the PCI specification. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 19 R Configurable Logic Block Timing Table 20: CLB (SLICEM) Timing -4 Speed Grade Symbol Description Min Max Units When reading from the FFX (FFY) Flip-Flop, the time from the active transition at the CLK input to data appearing at the XQ (YQ) output - 0.60 ns TAS Time from the setup of data at the F or G input to the active transition at the CLK input of the CLB 0.52 - ns TDICK Time from the setup of data at the BX or BY input to the active transition at the CLK input of the CLB 1.81 - ns Clock-to-Output Times TCKO Setup Times Hold Times TAH Time from the active transition at the CLK input to the point where data is last held at the F or G input 0 - ns TCKDI Time from the active transition at the CLK input to the point where data is last held at the BX or BY input 0 - ns Clock Timing TCH The High pulse width of the CLB’s CLK signal 0.80 - ns TCL The Low pulse width of the CLK signal 0.80 - ns FTOG Toggle frequency (for export control) 0 572 MHz - 0.76 ns 1.80 - ns Propagation Times TILO The time it takes for data to travel from the CLB’s F (G) input to the X (Y) output Set/Reset Pulse Width TRPW_CLB The minimum allowable pulse width, High or Low, to the CLB’s SR input Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 6. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 20 R Table 21: CLB Distributed RAM Switching Characteristics -4 Symbol Description Min Max Units - 2.35 ns Clock-to-Output Times TSHCKO Time from the active edge at the CLK input to data appearing on the distributed RAM output Setup Times TDS Setup time of data at the BX or BY input before the active transition at the CLK input of the distributed RAM 0.46 - ns TAS Setup time of the F/G address inputs before the active transition at the CLK input of the distributed RAM 0.52 - ns TWS Setup time of the write enable input before the active transition at the CLK input of the distributed RAM 0.40 - ns Hold time of the BX, BY data inputs after the active transition at the CLK input of the distributed RAM 0.15 - ns 0 - ns 1.01 - ns Min Max Units Time from the active edge at the CLK input to data appearing on the shift register output - 4.16 ns Setup time of data at the BX or BY input before the active transition at the CLK input of the shift register 0.46 - ns Hold time of the BX or BY data input after the active transition at the CLK input of the shift register 0.16 - ns 1.01 - ns Hold Times TDH TAH, TWH Hold time of the F/G address inputs or the write enable input after the active transition at the CLK input of the distributed RAM Clock Pulse Width TWPH, TWPL Minimum High or Low pulse width at CLK input Table 22: CLB Shift Register Switching Characteristics -4 Symbol Description Clock-to-Output Times TREG Setup Times TSRLDS Hold Times TSRLDH Clock Pulse Width TWPH, TWPL Minimum High or Low pulse width at CLK input DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 21 R Clock Buffer/Multiplexer Switching Characteristics Table 23: Clock Distribution Switching Characteristics Maximum Description Symbol -4 Speed Grade Units Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay TGIO 1.46 ns Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1 inputs. Same as BUFGCE enable CE-input TGSI 0.63 ns FBUFG 311 MHz Frequency of signals distributed on global buffers (all sides) 18 x 18 Embedded Multiplier Timing Table 24: 18 x 18 Embedded Multiplier Timing -4 Speed Grade Symbol Description Min Max Units Combinatorial multiplier propagation delay from the A and B inputs to the P outputs, assuming 18-bit inputs and a 36-bit product (AREG, BREG, and PREG registers unused) - 4.88(1) ns Combinatorial Delay TMULT Clock-to-Output Times TMSCKP_P Clock-to-output delay from the active transition of the CLK input to valid data appearing on the P outputs when using the PREG register(2) - 1.10 ns TMSCKP_A Clock-to-output delay from the active transition of the CLK input to valid data appearing on the P outputs when using either the AREG or BREG register(3) - 4.97 ns Data setup time at the A or B input before the active transition at the CLK when using only the PREG output register (AREG, BREG registers unused)(2) 3.98 - ns TMSDCK_A Data setup time at the A input before the active transition at the CLK when using the AREG input register(3) 0.23 - ns TMSDCK_B Data setup time at the B input before the active transition at the CLK when using the BREG input register(3) 0.39 - ns Data hold time at the A or B input before the active transition at the CLK when using only the PREG output register (AREG, BREG registers unused)(2) -0.97 TMSCKD_A Data hold time at the A input before the active transition at the CLK when using the AREG input register(3) 0.04 TMSCKD_B Data hold time at the B input before the active transition at the CLK when using the BREG input register(3) 0.05 TMSCKP_B Setup Times TMSDCK_P Hold Times TMSCKD_P DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 22 R Table 24: 18 x 18 Embedded Multiplier Timing (Continued) -4 Speed Grade Symbol Description Min Max Units Internal operating frequency for a two-stage 18x18 multiplier using the AREG and BREG input registers and the PREG output register(1) 0 240 MHz Clock Frequency FMULT Notes: 1. 2. 3. Combinatorial delay is less and pipelined performance is higher when multiplying input data with less than 18 bits. The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations. Input registers AREG or BREG are typically used when inferring a two-stage multiplier. Block RAM Timing Table 25: Block RAM Timing -4 Speed Grade Symbol Description Min Max Units When reading from block RAM, the delay from the active transition at the CLK input to data appearing at the DOUT output - 2.82 ns TBACK Setup time for the ADDR inputs before the active transition at the CLK input of the block RAM 0.38 - ns TBDCK Setup time for data at the DIN inputs before the active transition at the CLK input of the block RAM 0.23 - ns TBECK Setup time for the EN input before the active transition at the CLK input of the block RAM 0.77 - ns TBWCK Setup time for the WE input before the active transition at the CLK input of the block RAM 1.26 - ns TBCKA Hold time on the ADDR inputs after the active transition at the CLK input 0.14 - ns TBCKD Hold time on the DIN inputs after the active transition at the CLK input 0.13 - ns TBCKE Hold time on the EN input after the active transition at the CLK input 0 - ns TBCKW Hold time on the WE input after the active transition at the CLK input 0 - ns Clock-to-Output Times TBCKO Setup Times Hold Times DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 23 R Table 25: Block RAM Timing (Continued) -4 Speed Grade Symbol Description Min Max Units Clock Timing TBPWH High pulse width of the CLK signal 1.59 - ns TBPWL Low pulse width of the CLK signal 1.59 - ns 0 230 MHz Clock Frequency FBRAM Block RAM clock frequency. RAM read output value written back into RAM, for shift registers and circular buffers. Write-only or read-only performance is faster. Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 6. Digital Clock Manager Timing For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), and the Phase Shifter (PS). Aspects of DLL operation play a role in all DCM applications. All such applications inevitably use the CLKIN and the CLKFB inputs connected to either the CLK0 or the CLK2X feedback, respectively. Thus, specifications in the DLL tables (Table 26 and Table 27) apply to any application that only employs the DLL component. When the DFS and/or the PS components are used together with the DLL, then the specifications listed in the DFS and PS tables (Table 28 through Table 31) supersede any corresponding ones in the DLL tables. DLL specifications that do not change with the addition of DFS or PS functions are presented in Table 26 and Table 27. Period jitter and cycle-cycle jitter are two of many different ways of specifying clock jitter. Both specifications describe statistical variation from a mean value. Period jitter is the worst-case deviation from the ideal clock period over a collection of millions of samples. In a histogram of period jitter, the mean value is the clock period. Cycle-cycle jitter is the worst-case difference in clock period between adjacent clock cycles in the collection of clock periods sampled. In a histogram of cycle-cycle jitter, the mean value is zero. Spread Spectrum DCMs accept typical spread spectrum clocks as long as they meet the input requirements. The DLL will track the frequency changes created by the spread spectrum clock to drive the global clocks to the FPGA logic. See XAPP469, Spread-Spectrum Clocking Reception for Displays for details. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 24 R Delay-Locked Loop Table 26: Recommended Operating Conditions for the DLL -4 Speed Grade Symbol Description Min Max Units 5(2) 240(3) MHz FCLKIN < 150 MHz 40% 60% - FCLKIN > 150 MHz 45% 55% - FCLKIN < 150 MHz - ±300 ps FCLKIN > 150 MHz - ±150 ps Input Frequency Ranges FCLKIN CLKIN_FREQ_DLL Frequency of the CLKIN clock input Input Pulse Requirements CLKIN_PULSE CLKIN pulse width as a percentage of the CLKIN period Input Clock Jitter Tolerance and Delay Path Variation(4) CLKIN_CYC_JITT_DLL_LF CLKIN_CYC_JITT_DLL_HF Cycle-to-cycle jitter at the CLKIN input CLKIN_PER_JITT_DLL Period jitter at the CLKIN input - ±1 ns CLKFB_DELAY_VAR_EXT Allowable variation of off-chip feedback delay from the DCM output to the CLKFB input - ±1 ns Notes: 1. 2. 3. 4. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use. The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table 28. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming clock frequency by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input. CLKIN input jitter beyond these limits might cause the DCM to lose lock. Table 27: Switching Characteristics for the DLL -4 Speed Grade Symbol Description Min Max Units Output Frequency Ranges CLKOUT_FREQ_CLK0 Frequency for the CLK0 and CLK180 outputs 5 240 MHz CLKOUT_FREQ_CLK90 Frequency for the CLK90 and CLK270 outputs 5 200 MHz CLKOUT_FREQ_2X Frequency for the CLK2X and CLK2X180 outputs 10 311 MHz CLKOUT_FREQ_DV Frequency for the CLKDV output 0.3125 160 MHz Output Clock Jitter(2,3,4) CLKOUT_PER_JITT_0 Period jitter at the CLK0 output - ±100 ps CLKOUT_PER_JITT_90 Period jitter at the CLK90 output - ±150 ps CLKOUT_PER_JITT_180 Period jitter at the CLK180 output - ±150 ps CLKOUT_PER_JITT_270 Period jitter at the CLK270 output - ±150 ps CLKOUT_PER_JITT_2X Period jitter at the CLK2X and CLK2X180 outputs - ±[1% of CLKIN period + 150] ps CLKOUT_PER_JITT_DV1 Period jitter at the CLKDV output when performing integer division - ±150 ps CLKOUT_PER_JITT_DV2 Period jitter at the CLKDV output when performing non-integer division - ±[1% of CLKIN period + 200] ps DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 25 R Table 27: Switching Characteristics for the DLL (Continued) -4 Speed Grade Symbol Min Max Units Duty cycle variation for the CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV outputs, including the BUFGMUX and clock tree duty-cycle distortion - ±[1% of CLKIN period + 400] ps CLKIN_CLKFB_PHASE Phase offset between the CLKIN and CLKFB inputs - ±200 ps CLKOUT_PHASE_DLL Phase offset between DLL outputs CLK0 to CLK2X (not CLK2X180) - ±[1% of CLKIN period + 100] ps All others - ±[1% of CLKIN period + 200] ps 5 MHz < FCLKIN < 15 MHz - 5 ms FCLKIN > 15 MHz - 600 μs 20 40 ps Duty Description Cycle(4) CLKOUT_DUTY_CYCLE_DLL Phase Alignment(4) Lock Time LOCK_DLL(3) When using the DLL alone: The time from deassertion at the DCM’s Reset input to the rising transition at its LOCKED output. When the DCM is locked, the CLKIN and CLKFB signals are in phase Delay Lines DCM_DELAY_STEP Finest delay resolution Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 6 and Table 26. 2. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input. 3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute. 4. Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. Example: The data sheet specifies a maximum jitter of “±[1% of CLKIN period + 150]”. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250ps. Digital Frequency Synthesizer Table 28: Recommended Operating Conditions for the DFS -4 Speed Grade Symbol Description Min Max Units 0.200 333(4) MHz FCLKFX < 150 MHz - ±300 ps FCLKFX > 150 MHz - ±150 ps - ±1 ns Input Frequency Ranges(2) FCLKIN CLKIN_FREQ_FX Frequency for the CLKIN input Input Clock Jitter Tolerance(3) CLKIN_CYC_JITT_FX_HF CLKIN_CYC_JITT_FX_LF Cycle-to-cycle jitter at the CLKIN input, based on CLKFX output frequency CLKIN_PER_JITT_FX Period jitter at the CLKIN input Notes: 1. 2. 3. 4. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 26. CLKIN input jitter beyond these limits may cause the DCM to lose lock. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming clock frequency by two as it enters the DCM. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 26 R Table 29: Switching Characteristics for the DFS -4 Speed Grade Symbol Description Device Min Max Units Frequency for the CLKFX and CLKFX180 outputs All 5 311 MHz Period jitter at the CLKFX and CLKFX180 outputs All Typ Max Output Frequency Ranges CLKOUT_FREQ_FX Output Clock Jitter(2,3) CLKOUT_PER_JITT_FX CLKIN <20 MHz See Note 4 CLKIN > 20 MHz ps ±[1% of CLKFX period + 100] ±[1% of CLKFX period + 200] ps Duty Cycle(5,6) Duty cycle precision for the CLKFX and CLKFX180 outputs, including the BUFGMUX and clock tree duty-cycle distortion All - ±[1% of CLKFX period + 400] ps CLKOUT_PHASE_FX Phase offset between the DFS CLKFX output and the DLL CLK0 output when both the DFS and DLL are used All - ±200 ps CLKOUT_PHASE_FX180 Phase offset between the DFS CLKFX180 output and the DLL CLK0 output when both the DFS and DLL are used All - ±[1% of CLKFX period + 300] ps The time from deassertion at the DCM’s Reset input to the rising transition at its LOCKED output. The DFS asserts LOCKED when the CLKFX and CLKFX180 signals are valid. If using both the DLL and the DFS, use the longer locking time. All - 5 ms - 450 μs CLKOUT_DUTY_CYCLE_FX Phase Alignment(6) Lock Time LOCK_FX(2) 5 MHz < FCLKIN < 15 MHz FCLKIN > 15 MHz Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 6 and Table 28. 2. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute. 3. Maximum output jitter is characterized within a reasonable noise environment (150 ps input period jitter, 40 SSOs and 25% CLB switching). Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on the system application. 4. Use the Spartan-3A Jitter Calculator (www.xilinx.com/support/documentation/data_sheets/s3a_jitter_calc.zip) to estimate DFS output jitter. Use the Clocking Wizard to determine jitter for a specific design. 5. The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle. 6. Some duty-cycle and alignment specifications include 1% of the CLKFX output period or 0.01 UI. Example: The data sheet specifies a maximum jitter of “±[1% of CLKFX period + 300]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 300 ps] = ±400 ps. Phase Shifter Table 30: Recommended Operating Conditions for the PS in Variable Phase Mode -4 Speed Grade Symbol Description Min Max Units 1 167 MHz 40% 60% - Operating Frequency Ranges PSCLK_FREQ (FPSCLK) Frequency for the PSCLK input Input Pulse Requirements PSCLK_PULSE PSCLK pulse width as a percentage of the PSCLK period DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 27 R Table 31: Switching Characteristics for the PS in Variable Phase Mode Symbol Description Units Phase Shifting Range MAX_STEPS(2) Maximum allowed number of DCM_DELAY_STEP steps for a given CLKIN clock period, where T = CLKIN clock period in ns. If using CLKIN_DIVIDE_BY_2 = TRUE, double the clock effective clock period. CLKIN < 60 MHz ±[INTEGER(10 • (TCLKIN – 3 ns))] steps CLKIN > 60 MHz ±[INTEGER(15 • (TCLKIN – 3 ns))] steps FINE_SHIFT_RANGE_MIN Minimum guaranteed delay for variable phase shifting ±[MAX_STEPS • DCM_DELAY_STEP_MIN] ns FINE_SHIFT_RANGE_MAX Maximum guaranteed delay for variable phase shifting ±[MAX_STEPS • DCM_DELAY_STEP_MAX] ns Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 6 and Table 30. 2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, i.e., the PHASE_SHIFT attribute is set to 0. 3. The DCM_DELAY_STEP values are provided at the bottom of Table 27. Miscellaneous DCM Timing Table 32: Miscellaneous DCM Timing Symbol Description Min Max Units DCM_RST_PW_MIN(1) Minimum duration of a RST pulse width 3 - CLKIN cycles DCM_RST_PW_MAX(2) Maximum duration of a RST pulse width N/A N/A seconds N/A N/A seconds N/A N/A minutes N/A N/A minutes DCM_CONFIG_LAG_TIME(3) Maximum duration from VCCINT applied to FPGA configuration successfully completed (DONE pin goes High) and clocks applied to DCM DLL Notes: 1. 2. 3. This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV). The DCM DFS outputs (CLKFX, CLKFX180) are unaffected. This specification is equivalent to the Virtex-4 DCM_RESET specification. This specification does not apply for Spartan-3E FPGAs. This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3E FPGAs. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 28 R Configuration and JTAG Timing Table 33: Power-On Timing and the Beginning of Configuration -4 Speed Grade Symbol TPOR(2) Description Device The time from the application of VCCINT, VCCAUX, and VCCO Bank 2 supply voltage ramps (whichever occurs last) to the rising transition of the INIT_B pin Min Max Units XA3S100E - 5 ms XA3S250E - 5 ms XA3S500E - 5 ms XA3S1200E - 5 ms XA3S1600E - 7 ms 0.5 - μs XA3S100E - 0.5 ms XA3S250E - 0.5 ms XA3S500E - 1 ms XA3S1200E - 2 ms TPROG The width of the low-going pulse on the PROG_B pin All TPL(2) The time from the rising edge of the PROG_B pin to the rising transition on the INIT_B pin XA3S1600E - 2 ms TINIT Minimum Low pulse width on INIT_B output All 250 - ns TICCK(3) The time from the rising edge of the INIT_B pin to the generation of the configuration clock signal at the CCLK output pin All 0.5 4.0 μs Notes: 1. 2. 3. The numbers in this table are based on the operating conditions set forth in Table 6. This means power must be applied to all VCCINT, VCCO, and VCCAUX lines. Power-on reset and the clearing of configuration memory occurs during this period. This specification applies only to the Master Serial, SPI, BPI-Up, and BPI-Down modes. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 29 R Configuration Clock (CCLK) Characteristics Table 34: Master Mode CCLK Output Period by ConfigRate Option Setting ConfigRate Setting Temperature Range Minimum Maximum Units 1 (power-on value and default value) I-Grade Q-Grade 485 1,250 ns TCCLK3 3 I-Grade Q-Grade 242 625 ns TCCLK6 6 I-Grade Q-Grade 121 313 ns TCCLK12 12 I-Grade Q-Grade 60.6 157 ns TCCLK25 25 I-Grade Q-Grade 30.3 78.2 ns TCCLK50 50 I-Grade Q-Grade 15.1 39.1 ns Symbol TCCLK1 Description CCLK clock period by ConfigRate setting Notes: 1. Set the ConfigRate option value when generating a configuration bitstream. See Bitstream Generator (BitGen) Options in DS312, Module 2. Table 35: Master Mode CCLK Output Frequency by ConfigRate Option Setting ConfigRate Setting Temperature Range Minimum Maximum Units 1 (power-on value and default value) I-Grade Q-Grade 0.8 2.1 MHz FCCLK3 3 I-Grade Q-Grade 1.6 4.2 MHz FCCLK6 6 I-Grade Q-Grade 3.2 8.3 MHz FCCLK12 12 I-Grade Q-Grade 6.4 16.5 MHz FCCLK25 25 I-Grade Q-Grade 12.8 33.0 MHz FCCLK50 50 I-Grade Q-Grade 25.6 66.0 MHz Symbol FCCLK1 Description Equivalent CCLK clock frequency by ConfigRate setting Table 36: Master Mode CCLK Output Minimum Low and High Time Symbol TMCCL, TMCCH ConfigRate Setting Description Master mode CCLK minimum Low and High time I-Grade Q-Grade 1 3 6 12 25 50 235 117 58 29.3 14.5 7.3 Units ns Table 37: Slave Mode CCLK Input Low and High Time Symbol TSCCL, TSCCH Description CCLK Low and High time DS635 (v2.0) September 9, 2009 Product Specification Min Max Units 5 ∞ ns www.xilinx.com 30 R Master Serial and Slave Serial Mode Timing Table 38: Timing for the Master Serial and Slave Serial Configuration Modes Symbol Slave/ Master Description -4 Speed Grade Min Max Units Both 1.5 10.0 ns Both 11.0 - ns Both 0 - ns Clock-to-Output Times TCCO The time from the falling transition on the CCLK pin to data appearing at the DOUT pin Setup Times TDCC The time from the setup of data at the DIN pin to the active edge of the CCLK pin Hold Times TCCD The time from the active edge of the CCLK pin to the point when data is last held at the DIN pin Clock Timing TCCH TCCL FCCSER High pulse width at the CCLK input pin Low pulse width at the CCLK input pin Frequency of the clock signal at the CCLK input pin No bitstream compression With bitstream compression Master See Table 36 Slave See Table 37 Master See Table 36 Slave See Table 37 Slave 0 66(2) MHz 0 20 MHz Notes: 1. 2. The numbers in this table are based on the operating conditions set forth in Table 6. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 31 R Slave Parallel Mode Timing Table 39: Timing for the Slave Parallel Configuration Mode -4 Speed Grade Symbol Description Min Max Units The time from the rising transition on the CCLK pin to a signal transition at the BUSY pin - 12.0 ns TSMDCC The time from the setup of data at the D0-D7 pins to the active edge the CCLK pin 11.0 - ns TSMCSCC Setup time on the CSI_B pin before the active edge of the CCLK pin 10.0 - ns TSMCCW(2) Setup time on the RDWR_B pin before active edge of the CCLK pin 23.0 - ns TSMCCD The time from the active edge of the CCLK pin to the point when data is last held at the D0-D7 pins 1.0 - ns TSMCCCS The time from the active edge of the CCLK pin to the point when a logic level is last held at the CSO_B pin 0 - ns TSMWCC The time from the active edge of the CCLK pin to the point when a logic level is last held at the RDWR_B pin 0 - ns TCCH The High pulse width at the CCLK input pin 5 - ns TCCL The Low pulse width at the CCLK input pin 5 - ns FCCPAR Frequency of the clock signal at the CCLK input pin Not using the BUSY pin(2) 0 50 MHz Using the BUSY pin 0 66 MHz 0 20 MHz Clock-to-Output Times TSMCKBY Setup Times Hold Times Clock Timing No bitstream compression With bitstream compression Notes: 1. 2. 3. The numbers in this table are based on the operating conditions set forth in Table 6. In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification. Some Xilinx documents refer to Parallel modes as “SelectMAP” modes. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 32 R Serial Peripheral Interface Configuration Timing Table 40: Timing for SPI Configuration Mode Symbol Description Minimum Maximum Units TCCLK1 Initial CCLK clock period (see Table 34) TCCLKn CCLK clock period after FPGA loads ConfigRate setting (see Table 34) TMINIT Setup time on VS[2:0] and M[2:0] mode pins before the rising edge of INIT_B 50 - ns TINITM Hold time on VS[2:0] and M[2:0]mode pins after the rising edge of INIT_B 0 - ns TCCO MOSI output valid after CCLK edge See Table 38 TDCC Setup time on DIN data input before CCLK edge See Table 38 TCCD Hold time on DIN data input after CCLK edge See Table 38 Table 41: Configuration Timing Requirements for Attached SPI Serial Flash Symbol Description TCCS SPI serial Flash PROM chip-select time TDSU SPI serial Flash PROM data input setup time TDH SPI serial Flash PROM data input hold time TV SPI serial Flash PROM data clock-to-output time fC or fR Maximum SPI serial Flash PROM clock frequency (also depends on specific read command used) Requirement Units T CCS ≤ T MCCL1 – T CCO ns T DSU ≤ T MCCL1 – T CCO T DH ≤ T MCCH1 T V ≤ T MCCLn – T DCC 1 f C ≥ ------------------------------T CCLKn ( min ) ns ns ns MHz Notes: 1. 2. These requirements are for successful FPGA configuration in SPI mode, where the FPGA provides the CCLK frequency. The post configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source. Subtract additional printed circuit board routing delay as required by the application. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 33 R Byte Peripheral Interface Configuration Timing Table 42: Timing for BPI Configuration Mode Symbol Description Minimum Maximum Units TCCLK1 Initial CCLK clock period (see Table 34) TCCLKn CCLK clock period after FPGA loads ConfigRate setting (see Table 34) TMINIT Setup time on CSI_B, RDWR_B, and M[2:0] mode pins before the rising edge of INIT_B 50 - ns TINITM Hold time on CSI_B, RDWR_B, and M[2:0] mode pins after the rising edge of INIT_B 0 - ns TINITADDR Minimum period of initial A[23:0] address cycle; LDC[2:0] and HDC are asserted and valid BPI-UP: (M[2:0]=<0:1:0>) 5 5 TCCLK1 cycles BPI-DN: (M[2:0]=<0:1:1>) 2 2 TCCO Address A[23:0] outputs valid after CCLK falling edge See Table 38 TDCC Setup time on D[7:0] data inputs before CCLK rising edge See Table 38 TCCD Hold time on D[7:0] data inputs after CCLK rising edge See Table 38 Table 43: Configuration Timing Requirements for Attached Parallel NOR Flash Symbol TCE (tELQV) TOE (tGLQV) TACC (tAVQV) TBYTE (tFLQV, tFHQV) Description Requirement Units Parallel NOR Flash PROM chip-select time T CE ≤ T INITADDR ns Parallel NOR Flash PROM output-enable time T OE ≤ T INITADDR ns T ACC ≤ 0.5T CCLKn ( min ) – T CCO – T DCC – PCB ns T BYTE ≤ T INITADDR ns Parallel NOR Flash PROM read access time For x8/x16 PROMs only: BYTE# to output valid time(3) Notes: 1. 2. 3. These requirements are for successful FPGA configuration in BPI mode, where the FPGA provides the CCLK frequency. The post configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source. Subtract additional printed circuit board routing delay as required by the application. The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor value also depends on whether the FPGA’s HSWAP pin is High or Low. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 34 R IEEE 1149.1/1553 JTAG Test Access Port Timing Table 44: Timing for the JTAG Test Access Port -4 Speed Grade Symbol Description Min Max Units The time from the falling transition on the TCK pin to data appearing at the TDO pin 1.0 11.0 ns TTDITCK The time from the setup of data at the TDI pin to the rising transition at the TCK pin 7.0 - ns TTMSTCK The time from the setup of a logic level at the TMS pin to the rising transition at the TCK pin 7.0 - ns TTCKTDI The time from the rising transition at the TCK pin to the point when data is last held at the TDI pin 0 - ns TTCKTMS The time from the rising transition at the TCK pin to the point when a logic level is last held at the TMS pin 0 - ns TCCH The High pulse width at the TCK pin 5 - ns TCCL The Low pulse width at the TCK pin 5 - ns FTCK Frequency of the TCK signal - 25 MHz Clock-to-Output Times TTCKTDO Setup Times Hold Times Clock Timing Notes: 1. The numbers in this table are based on the operating conditions set forth in Table 6. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 35 R Revision History The following table shows the revision history for this document. Date Version Revision 08/31/07 1.0 Initial Xilinx release. 01/20/09 1.1 • • • • Updated "Key Feature Differences from Commercial XC Devices." Updated TACC requirement in Table 43. Updated description of TDCC and TCCD in Table 42. Removed Table 45: MultiBoot Trigger Timing. 09/09/09 2.0 • • • • • • Added package sizes to Table 2, page 4. Removed Genealogy Viewer Link from "Package Marking," page 5. Updated data and notes for Table 6, page 8. Updated test conditions for RPU and maximum value for CIN in Table 7, page 8. Updated notes for Table 8, page 9. Updated Max VCCO for LVTTL and LVCMOS33, removed PCIX data, updated VIL Max for LVCMOS18, LVCMOS15, and LVCMOS12, updated VIH Min for LVCMOS12, and added note 6 in Table 9, page 11. Removed PCIX data, revised note 2, and added note 4 in Table 10, page 12. Updated figure description of Figure 5, page 14. Added note 4 to Table 13, page 14. Removed PC166_3 and PCIX adjustment values from Table 17, page 17. Deleted Table 18 (duplicate of Table 17, page 17). Subsequent tables renumbered. Removed PCIX data Table 18, page 18. Removed PCIX data and removed VREF values for DIFF_HSTL_I_18, DIFF_HSTL_III_18, DIFF_SSTL18_I, and DIFF_SSTL2_I from Table 19, page 19. Updated TDICK minimum setup time in Table 20, page 20. Updated notes, references to notes, and revised the maximum clock-to-output times for TMSCKP_P Table 24, page 22. Added "Spread Spectrum," page 24. Updated note 3 in Table 26, page 25. Added note 4 Table 28, page 26. Updated notes, references to notes, and CLKOUT_PER_JITT_FX data in Table 29, page 27. Updated MAX_STEPS data in Table 31, page 28. Updated ConfigRate Setting for TCCLK1 to indicate 1 is the default value in Table 34, page 30. Updated ConfigRate Setting for FCCLK1 to indicate 1 is the default value in Table 35, page 30. • • • • • • • • • • • • • • • • Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 36 R Automotive Applications Disclaimer XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS. DS635 (v2.0) September 9, 2009 Product Specification www.xilinx.com 37