SN74ALVCH16903 3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS SCES095C – MARCH 1997 – REVISED MAY 1998 D D D D D D D D Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Checks Parity Able to Cascade With a Second SN74ALVCH16903 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic 300-mil Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages description This 12-bit universal bus driver is designed for 2.3-V to 3.6-V VCC operation. The SN74ALVCH16903 has dual outputs and can operate as a buffer or an edge-triggered register. In both modes, parity is checked on APAR, which arrives one cycle after the data to which it applies. The YERR output, which is produced one cycle after APAR, is open drain. DGG, DGV, OR DL PACKAGE (TOP VIEW) OE 1Y1 1Y2 GND 2Y1 2Y2 VCC 3Y1 3Y2 4Y1 GND 4Y2 5Y1 5Y2 6Y1 6Y2 7Y1 GND 7Y2 8Y1 8Y2 VCC 9Y1 9Y2 GND 10Y1 10Y2 PAROE 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 CLK 1A 11A/YERREN GND 11Y1 11Y2 VCC 2A 3A 4A GND 12A 12Y1 12Y2 5A 6A 7A GND APAR 8A YERR VCC 9A MODE GND 10A PARI/O CLKEN MODE selects one of the two data paths. When MODE is low, the device operates as an edge-triggered register. On the positive transition of the clock (CLK) input and when the clock-enable (CLKEN) input is low, data set up at the A inputs is stored in the internal registers. On the positive transition of CLK and when CLKEN is high, only data set up at the 9A–12A inputs is stored in their internal registers. When MODE is high, the device operates as a buffer and data at the A inputs passes directly to the outputs. 11A/YERREN serves a dual purpose; it acts as a normal data bit and also enables YERR data to be clocked into the YERR output register. When used as a single device, parity output enable (PAROE) must be tied high; when parity input/output (PARI/O) is low, even parity is selected and when PARI/O is high, odd parity is selected. When used in pairs and PAROE is low, the parity sum is output on PARI/O for cascading to the second SN74ALVCH16903. When used in pairs and PAROE is high, PARI/O accepts a partial parity sum from the first SN74ALVCH16903. A buffered output-enable (OE) input can be used to place the 24 outputs and YERR in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALVCH16903 3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS SCES095C – MARCH 1997 – REVISED MAY 1998 description (continued) OE does not affect the internal operation of the device. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH16903 is characterized for operation from 0°C to 70°C. Function Tables FUNCTION INPUTS OUTPUTS 1Yn† – 8Yn† H 9Yn† – 12Yn† H OE MODE CLKEN CLK A L L L ↑ H L L L ↑ L L L L L H ↑ H H L L H ↑ L Y0 Y0 L H X X H H H L H X X L L L H † n = 1, 2 X X X X Z Z L PARITY FUNCTION INPUTS 2 OE PAROE‡ 11A/YERREN§ PARI/O Σ OF INPUTS 1A – 10A = H APAR OUTPUT YERR L H L L 0, 2, 4, 6, 8, 10 L H L H L L 1, 3, 5, 7, 9 L L L H L L 0, 2, 4, 6, 8, 10 H L L H L L 1, 3, 5, 7, 9 H H L H L H 0, 2, 4, 6, 8, 10 L L L H L H 1, 3, 5, 7, 9 L H L H L H 0, 2, 4, 6, 8, 10 H H L H L H 1, 3, 5, 7, 9 H L H X X X X X H L X H X X X ‡ When used as a single device, PAROE must be tied high. § Valid after appropriate number of clock pulses have set internal register H POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVCH16903 3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS SCES095C – MARCH 1997 – REVISED MAY 1998 Function Tables (Continued) PARI/O FUNCTION† INPUTS OUTPUT PARI/O PAROE Σ OF INPUTS 1A – 10A = H APAR L 0, 2, 4, 6, 8, 10 L L L 1, 3, 5, 7, 9 L H L 0, 2, 4, 6, 8, 10 H H L 1, 3, 5, 7, 9 H L H X X Z † This table applies to the first device of a cascaded pair of ALVCH16903 devices. logic diagram (positive logic) OE MODE CLK 1 33 13 1A–12A, APAR (1A–12A) 12 13 1Y2–12Y2 13 CLKEN 1Y1–12Y1 12 56 29 (1A–8A) 8 13 12 (1A–11A/YERREN, APAR) D 11A/YERREN Q Flip-Flop 11 5 (9A–12A, APAR) APAR 5 APAR Flip-Flop D Q D Q 10 (1A–10A) Parity Check 36 XOR D Q YERR 30 PARI/O PAROE 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ALVCH16903 3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS SCES095C – MARCH 1997 – REVISED MAY 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) VCC Supply voltage MIN MAX 2.3 3.6 VIH High level input voltage High-level VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VIL Low level input voltage Low-level VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VI VO Input voltage 0 Output voltage 0 IOH VCC = 2.3 V VCC = 2.7 V High level output current High-level VCC = 3 V VCC = 2.3 V VCC = 2.7 V IOL Low-level output current VCC = 3 V ∆t/∆v Input transition rise or fall rate 1.7 UNIT V V 2 0.7 0.8 VCC VCC V V V –12 Y port –12 PARI/O –12 Y port –24 mA 12 Y port 12 PARI/O 12 Y port 24 YERR output 24 0 10 mA ns/V TA Operating free-air temperature 0 70 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVCH16903 3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS SCES095C – MARCH 1997 – REVISED MAY 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA IOH = –6 mA, VOH Y port PARI/O VIH = 1.7 V VIH = 1.7 V IOH = –12 mA VIH = 2 V IOH = –24 mA, IOH = –12 mA, VIH = 2 V VIH = 2 V IOL = 100 µA IOL = 6 mA, Y port VOL PARI/O YERR output II II(hold) ( ) IOH IOZ§ YERR output Ci Co IOL = 12 mA IOL = 24 mA, IOL = 12 mA, Data inputs YERR output Data outputs TYP† 2.3 V VCC–0.2 2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2 3V 2 MAX 0.2 2.3 V 0.4 2.3 V 0.7 VIL = 0.8 V VIL = 0.8 V 2.7 V 0.4 3V 0.55 VIL = 0.8 V 3V 0.55 3V 0.5 3.6 V ±5 2.3 V 45 2.3 V –45 VI = 0.8 V VI = 2 V 3V 75 3V –75 VI = 0 to 3.6 V‡ VO = VCC IO = 0 Other inputs at VCC or GND UNIT V VIL = 0.7 V VIL = 0.7 V VI = 0.7 V VI = 1.7 V One input at VCC –0.6 V, Control inputs MIN 2.3 V to 3.6 V IOL = 24 mA VI = VCC or GND VO = VCC or GND VI = VCC or GND, ICC ∆ICC VCC 2.3 V to 3.6 V V µA µA 3.6 V ±500 0 to 3.6 V ±10 µA 3.6 V ±10 µA 3.6 V 40 µA 750 µA 3 V to 3.6 V VI = VCC or GND 33V 3.3 VO = VCC or GND 33V 3.3 5.5 5.5 5 pF pF F 6 Cio PARI/O VO = VCC or GND 3.3 V † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ This is the bus-hold maximum dynamic current required to switch the input from one state to another. § For I/O ports, the parameter IOZ includes the input leakage current. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 pF 5 SN74ALVCH16903 3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS SCES095C – MARCH 1997 – REVISED MAY 1998 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figures 1 and 4) VCC = 2.5 V ± 0.2 V MIN fclock tw tsu Clock frequency MAX VCC = 3.3 V ± 0.3 V MIN 125 3 3 3 Register mode 1.7 1.9 1.45 1A–10A before CLK↑ Buffer mode 5.9 5.2 4.4 Register mode 1.2 1.5 1.3 Buffer mode 4.6 3.6 3.1 PARI/O before CLK↑ Both modes 2.4 2 1.7 11A/YERREN before CLK↑ Buffer mode 2 1.9 1.6 CLKEN before CLK↑ Register mode 2.5 2.6 2.2 1A–12A after CLK↑ Register mode 0.4 0.25 0.55 1A–10A after CLK↑ Buffer mode 0.25 0.25 0.25 0.7 0.4 0.7 Buffer mode 0.25 0.25 0.25 Register mode 0.25 0.25 0.4 Buffer mode 0.25 0.25 0.5 11A/YERREN after CLK↑ Buffer mode 0.25 0.25 0.4 CLKEN after CLK↑ Register mode 0.25 0.5 0.4 APAR before CLK↑ APAR after CLK↑ Hold time PARI/O after CLK↑ UNIT MAX 125 1A–12A before CLK↑ Register mode th MIN 125 Pulse duration, CLK↑ Setup time MAX VCC = 2.7 V MHz ns ns ns switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 and 4) PARAMETER FROM (INPUT) TO (OUTPUT) fmax MIN Both modes A CLK VCC = 2.7 V MIN MAX 125 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 125 MHz Y 1 4.4 4.2 1.1 3.8 YERR 1 5.7 4.9 1.4 4.4 PARI/O 1.2 8.6 7.9 1.7 6.6 ns tpd† Both modes CLK PARI/O 1 6.8 5.2 1.3 4.5 ns tpd Both modes MODE Y 1 5.9 5.8 1.3 4.9 ns tPLH tPHL Register mode CLK Y 1 6.1 5.5 1.2 4.8 1 5.9 4.9 1.2 4.6 ten Both modes tdi dis Both modes tPLH tPHL Both modes OE Y 1.1 6.5 6.4 1.4 5.4 PAROE PARI/O 1 5.6 6 1 4.8 OE Y 1 6.4 5.2 1.7 5 PAROE PARI/O 1 3.2 3.8 1.2 3.8 OE YERR 1 3.6 4.2 1.9 4 1.2 5.1 4.9 1.5 4.2 † See Figures 2 and 5 for the load specification. 6 MAX 125 Buffer mode tpd VCC = 2.5 V ± 0.2 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ns ns ns ns SN74ALVCH16903 3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS SCES095C – MARCH 1997 – REVISED MAY 1998 simultaneous switching characteristics (see Figures 3 and 6)† PARAMETER tPLH tPHL Register mode FROM (INPUT) TO (OUTPUT) CLK Y VCC = 2.5 V ± 0.2 V MIN MAX 1.8 1.4 VCC = 2.7 V MIN VCC = 3.3 V ± 0.3 V MAX MIN MAX 6.5 6.1 1.8 5 5.9 5.1 1.7 4.5 UNIT ns † All outputs switching operating characteristics for buffer mode, TA = 25°C PARAMETER Cpd d Power dissipation capacitance TEST CONDITIONS Outputs enabled Outputs disabled CL = 0 0, f = 10 MHz VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V TYP TYP 57.5 65 15 17.5 UNIT pF operating characteristics for register mode, TA = 25°C PARAMETER Cpd d Power dissipation capacitance TEST CONDITIONS Outputs enabled Outputs disabled POST OFFICE BOX 655303 CL = 0 0, f = 10 MHz • DALLAS, TEXAS 75265 VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V TYP TYP 57 87.5 16.5 34 UNIT pF 7 SN74ALVCH16903 3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS SCES095C – MARCH 1997 – REVISED MAY 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND YERR S1 tPHL (see Note H) tPLH (see Note I) LOAD CIRCUIT 2 × VCC 2 × VCC tw VCC Timing Input VCC/2 0V tsu VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VCC/2 0V th VCC Data Input Output VCC VCC/2 Input VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. tPHL is measured at VCC/2. I. tPLH is measured at VOL + 0.15 V. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVCH16903 3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS SCES095C – MARCH 1997 – REVISED MAY 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V From Output Under Test PARI/O Test Point PARI/O of Second ALVCH16903 ZO = 52 Ω Td = 63 ps CL = 0.6 pF (see Note A) CL = 0.6 pF (see Note A) LOAD CIRCUIT VCC Input VCC/2 VCC/2 0V tPLH tPHL VOH Output VCC/2 VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. C. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms VCC From Output Under Test Input RL = 10 Ω Test Point VCC/2 VCC/2 0V tPLH CL = 30 pF (see Note A) tPHL VOH Output VCC/2 VCC/2 VOL LOAD CIRCUIT VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. Figure 3. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN74ALVCH16903 3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS SCES095C – MARCH 1997 – REVISED MAY 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND 500 Ω YERR S1 tPHL (see Note H) tPLH (see Note I) 6V 6V LOAD CIRCUIT tw 2.7 V 2.7 V Timing Input 1.5 V 1.5 V Input 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) 2.7 V 1.5 V 0V tPZL 2.7 V Input 1.5 V 1.5 V 0V tPLH Output Waveform 1 S1 at 6 V (see Note B) 1.5 V tPLZ 3V 1.5 V VOL + 0.3 V VOL tPZH tPHL VOH Output 1.5 V 1.5 V VOL Output Waveform 2 S1 at GND (see Nte B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPHZ 1.5 V VOH VOH –0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. tPHL is measured at 1.5 V. I. tPLH is measured at VOL + 0.3 V. Figure 4. Load Circuit and Voltage Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVCH16903 3.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS SCES095C – MARCH 1997 – REVISED MAY 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V From Output Under Test PARI/O Test Point PARI/O of Second ALVCH16903 ZO = 52 Ω Td = 63 ps CL = 0.6 pF (see Note A) CL = 0.6 pF (see Note A) LOAD CIRCUIT 2.7 V Input 1.5 V 1.5 V 0V tPLH tPHL VOH Output 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. tPLH and tPHL are the same as tpd. Figure 5. Load Circuit and Voltage Waveforms 2.7 V From Output Under Test Input RL = 10 Ω Test Point 1.5 V 1.5 V 0V tPLH CL = 50 pF (see Note A) tPHL VOH Output 1.5 V 1.5 V VOL LOAD CIRCUIT VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. Figure 6. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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