TI JL101ABHA

LM101AJAN
LM101AJAN Operational Amplifiers
Literature Number: SNOSAJ8
LM101AJAN
Operational Amplifiers
tion. For example, in low frequency circuits it can be
overcompensated for increased stability margin. Or the
compensation can be optimized to give more than a
factor of ten improvement in high frequency performance
for most applications.
In addition, the device provides better accuracy and
lower noise in high impedance circuitry. The low input
currents also make it particularly well suited for long
interval integrators or timers, sample and hold circuits
and low frequency waveform generators. Further, replacing circuits where matched transistor pairs buffer the
inputs of conventional IC op amps, it can give lower offset
voltage and a drift at a lower cost.
General Description
The LM101A is a general purpose operational amplifier
which features improved performance over industry standards such as the LM709. Advanced processing techniques
make possible an order of magnitude reduction in input
currents, and a redesign of the biasing circuitry reduces the
temperature drift of input current. Improved specifications
include:
• Offset voltage 3 mV maximum over temperature
• Input current 100 nA maximum over temperature
• Offset current 20 nA maximum over temperature
• Guaranteed drift characteristics
• Offsets guaranteed over entire common mode and supply voltage ranges
• Slew rate of 10V/µs as a summing amplifier
This amplifier offers many features which make its application nearly foolproof: overload protection on the input
and output, no latch-up when the common mode range is
exceeded, and freedom from oscillations and compensation with a single 30 pF capacitor. It has advantages over
internally compensated amplifiers in that the frequency
compensation can be tailored to the particular applica-
Features
Offset voltage 3 mV maximum over temperature
Input current 100 nA maximum over temperature
Offset current 20 nA maximum over temperature
Guaranteed drift characteristics
Offsets guaranteed over entire common mode and
supply voltage ranges
n Slew rate of 10 V/µS as a summing amplifier
n
n
n
n
n
Ordering Information
NS Part Number
JL101ABGA
SMD Part Number
NS Package Number
JM38510/10103BGA
H08C
Package Description
8LD Metal Can
JL101ABPA
JM38510/10103BPA
J08A
8LD CERDIP
JL101ABHA
JM38510/10103BHA
W10A
10LD CERPACK
JL101ABCA
JM38510/10103BCA
J14A
14LD CERDIP
JL101ASGA
JM38510/10103SGA
H08C
8LD Metal Can
JL101ASPA
JM38510/10103SPA
J08A
8LD CERDIP
© 2006 National Semiconductor Corporation
DS201296
www.national.com
LM101AJAN Operational Amplifiers
January 2006
LM101AJAN
Schematic
(Note 8)
20129601
Connection Diagrams
(Top View)
Metal Can Package
(Top View)
Dual-In-Line Package
20129604
See NS Package Number J08A
20129602
Note: Pin 4 connected to case.
See NS Package Number H08C
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2
LM101AJAN
Connection Diagrams
(Continued)
(Top View)
Dual-In-Line Package
(Top View)
Ceramic Flatpack Package
20129640
See NS Package Number W10A
20129603
See NS Package Number J14A
Fast AC/DC Converter
20129633
Note 1: Feedforward compensation can be used to make a fast full wave rectifier without a filter.
3
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LM101AJAN
Absolute Maximum Ratings (Note 2)
± 22V
± 30V
± 15V
Supply Voltage
Differential Input Voltage
Input Voltage (Note 3)
Output Short Circuit Duration
Continuous
−55˚C ≤ TA ≤ +125˚C
Operating Ambient Temp. Range
TJ Max
150˚C
Power Dissipation at TA = 25˚C (Note 4)
H-Package
(Still Air)
750 mW
(500 LF / Min Air Flow)
1,200 mW
J8-Package
(Still Air)
1,000 mW
(500 LF / Min Air Flow)
1,500 mW
J14-Package
(Still Air)
1,200mW
(500 LF / Min Air Flow)
2,000mW
W-Package
(Still Air)
500mW
(500 LF / Min Air Flow)
800mW
Thermal Resistance
θJA
H-Package
(Still Air)
165˚C/W
(500 LF / Min Air Flow)
89˚C/W
J8-Package
(Still Air)
128˚C/W
(500 LF / Min Air Flow)
75˚C/W
J14-Package
(Still Air)
98˚C/W
(500 LF / Min Air Flow)
59˚C/W
W-Package
(Still Air)
233˚C/W
(500 LF / Min Air Flow)
155˚C/W
θJC (Typical)
H-Package
39˚C/W
J8-Package
26˚C/W
J14-Package
24˚C/W
W-Package
26˚C/W
−65˚C ≤ TA ≤ +150˚C
Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)
300˚C
ESD Tolerance (Note 5)
3000V
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4
LM101AJAN
Quality Conformance Inspection
Mil-Std-883, Method 5005 - Group A
Subgroup
Description
Temp (˚C)
1
Static tests at
25
2
Static tests at
125
3
Static tests at
-55
4
Dynamic tests at
25
5
Dynamic tests at
125
6
Dynamic tests at
-55
7
Functional tests at
25
8A
Functional tests at
125
8B
Functional tests at
-55
9
Switching tests at
25
10
Switching tests at
125
11
Switching tests at
-55
LM101A
JAN Electrical Characteristics
DC Parameters
The following conditions apply to all parameters, unless otherwise specified
VCC = ± 20V, VCM = 0V, RS = 50Ω
Symbol
Parameters
Conditions
VIO
Input Offset Voltage
Notes
Max
Unit
+VCC = 35V, -VCC = -5V,
VCM = -15V
-2.0
+2.0
mV
1
-3.0
+3.0
mV
2, 3
+VCC = 5V, -VCC = -35V,
VCM = +15V
-2.0
+2.0
mV
1
-3.0
+3.0
mV
2, 3
VCM = 0V
IIO
± IIB
Input Offset Current
Input Bias Current
-2.0
+2.0
mV
1
-3.0
+3.0
mV
2, 3
+VCC = 5V, -VCC = -5V,
VCM = 0V
-2.0
+2.0
mV
1
-3.0
+3.0
mV
2, 3
+VCC = 35V, -VCC = -5V,
VCM = -15V, RS = 100KΩ
-10
+10
nA
1, 2
-20
+20
nA
3
+VCC = 5V, -VCC = -35V,
VCM = +15V, RS = 100KΩ
-10
+10
nA
1, 2
-20
+20
nA
3
VCM = 0V, RS = 100KΩ
-10
+10
nA
1, 2
-20
+20
nA
3
+VCC = 5V, -VCC = -5V,
VCM = 0V, RS = 100KΩ
-10
+10
nA
1, 2
-20
+20
nA
3
+VCC = 35V, -VCC = -5V,
VCM = -15V, RS = 100KΩ
-0.1
75
nA
1, 2
-0.1
100
nA
3
+VCC = 5V, -VCC = -35V,
VCM = +15V, RS = 100KΩ
-0.1
75
nA
1, 2
-0.1
100
nA
3
VCM = 0V, RS = 100KΩ
-0.1
75
nA
1, 2
-0.1
100
nA
3
-0.1
75
nA
1, 2
-0.1
100
nA
3
+VCC = 5V, -VCC = -5V,
VCM = 0V, RS = 100KΩ
+PSRR
-PSRR
Power Supply Rejection Ratio
Power Supply Rejection Ratio
Subgroups
Min
+VCC = 10V, -VCC = -20V
+VCC = 20V, -VCC = -10V
5
-50
+50
µV/V
1
-100
+100
µV/V
2, 3
-50
+50
µV/V
1
-100
+100
µV/V
2, 3
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LM101AJAN
LM101A
JAN Electrical Characteristics
(Continued)
DC Parameters
(Continued)
The following conditions apply to all parameters, unless otherwise specified
VCC = ± 20V, VCM = 0V, RS = 50Ω
Symbol
Parameters
CMRR
Common Mode Rejection Ratio VCC = ± 35V to ± 5V,
VCM = ± 15V
+VIO Adj
Adjustment for Input Offset
Voltage
-VIO Adj
Adjustment for Input Offset
Voltage
+IOS
Output Short Circuit Current
+VCC = 15V, -VCC = -15V,
t ≤ 25mS, VCM = -15V
-IOS
Output Short Circuit Current
+VCC = 15V, -VCC = -15V,
t ≤ 25mS, VCM = +15V
ICC
Power Supply Current
+VCC = 15V, -VCC = -15V
∆VIO / ∆T
Temperature Coefficient of
Input Offset Voltage
∆ IIO / ∆T
Temperature Coefficient of
Input Offset Current
-AVS
Large Signal (Open Loop)
Voltage Gain
+AVS
Large Signal (Open Loop)
Voltage Gain
Conditions
Notes
+VOP
-VOP
Large Signal (Open Loop)
Voltage Gain
Output Voltage Swing
Output Voltage Swing
Subgroups
80
dB
1, 2, 3
4.0
mV
1, 2, 3
mV
1, 2, 3
mA
1, 2, 3
+60
mA
1, 2, 3
1
Max
-4.0
-60
3.0
mA
2.32
mA
2
3.5
mA
3
2
-55˚C ≤ TA ≤ +25˚C
(Note 6)
-18
+18
µV/˚C
+25˚C ≤ TA ≤ +125˚C
(Note 6)
-15
+15
µV/˚C
3
-55˚C ≤ TA ≤ +25˚C
(Note 6)
-200
+200
pA/˚C
2
+25˚C ≤ TA ≤ +125˚C
(Note 6)
-100
+100
pA/˚C
3
RL = 2KΩ, VO = -15V
(Note 7)
50
V/mV
4
(Note 7)
25
V/mV
5, 6
RL = 10KΩ, VO = -15V
(Note 7)
50
V/mV
4
(Note 7)
25
V/mV
5, 6
RL = 2KΩ, VO = +15V
(Note 7)
50
V/mV
4
(Note 7)
25
V/mV
5, 6
(Note 7)
50
V/mV
4
(Note 7)
25
V/mV
5, 6
VCC = ± 5V, RL = 2KΩ,
VO = ± 2V
(Note 7)
10
V/mV
4, 5, 6
VCC = ± 5V, RL = 10KΩ,
VO = ± 2V
(Note 7)
10
V/mV
4, 5, 6
RL = 10KΩ, VO = +15V
AVS
Unit
Min
RL = 10KΩ, VCM = -20V
+16
V
4, 5, 6
RL = 2KΩ, VCM = -20V
+15
V
4, 5, 6
RL = 10KΩ, VCM = 20V
-16
V
4, 5, 6
RL = 2KΩ, VCM = 20V
-15
V
4, 5, 6
Max
Units
Subgroups
AC Parameters
The following conditions apply to all parameters, unless otherwise specified
VCC = ± 20V, VCM = 0V, RS = 50Ω
Symbol
Parameter
Conditions
+SR
Slew Rate
AV = 1, VI = -5V to +5V
0.3
V/µS
7
-SR
Slew Rate
AV = 1, VI = +5V to -5V
0.3
V/µS
7
TRTR
Rise Time
AV = 1, VI = 50mV
800
nS
7
TROS
Overshoot
AV = 1, VI = 50mV
25
%
7
NIBB
Noise Broadband
BW = 10Hz to 5KHz, RS = 0Ω
15
µVRMS
7
NIPC
Noise Popcorn
BW = 10Hz to 5KHz,
RS = 100KΩ
80
µVPK
7
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Notes
6
Min
JAN Electrical Characteristics
DC Parameters:
LM101AJAN
LM101A
(Continued)
Drift Values
The following conditions apply to all parameters, unless otherwise specified
VCC = ± 20V, VCM = 0V, RS = 50Ω
Delta calculations performed on JAN S devices at group B, Subgroup 5 only.
Symbol
Parameter
Conditions
Min
Max
Units
Subgroups
VIO
Input Offset Voltage
± IIB
VCM = 0V
-0.5
0.5
mV
1
Input Bias Current
VCM = 0V, RS = 100KΩ
-7.5
7.5
nA
1
Notes
Notes
Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is
intended to be functional, but do no guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
test conditions.
Note 3: For supply voltages less than ± 15V, the absolute maximum input voltage is equal to the supply voltage.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package junction
to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax − TA) / θJA or the
number given in the Absolute Maximum Ratings, whichever is lower.
Note 5: Human body model, 100 pF discharged through 1.5 kΩ.
Note 6: Calculated parameter
Note 7: Datalog reading of K = V/mV.
Note 8: Pin connections shown are for 8-pin packages.
7
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LM101AJAN
Typical Performance Characteristics
LM101A
Input Voltage Range
Output Swing
20129642
20129641
Voltage Gain
20129643
Supply Current
Voltage Gain
20129647
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20129648
8
LM101A
LM101AJAN
Typical Performance Characteristics
(Continued)
Input Current,
LM101A
Maximum Power Dissipation
20129649
20129650
Current Limiting
Input Noise Voltage
20129651
20129652
Input Noise Current
Common Mode Rejection
20129653
20129654
9
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LM101AJAN
Typical Performance Characteristics
LM101A
(Continued)
Closed Loop Output
Impedance
Power Supply Rejection
20129655
20129656
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10
(Note 8)
Single Pole Compensation
Two Pole Compensation
20129608
20129612
CS= 30 pF
CS= 30 pF
C2 = 10 C1
Open Loop Frequency
Response
Feedforward Compensation
20129616
20129609
fo= 3 MHz
Open Loop Frequency
Response
Open Loop Frequency
Response
20129617
20129613
11
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LM101AJAN
Typical Performance Characteristics for Various Compensation Circuits
LM101AJAN
Typical Performance Characteristics for Various Compensation Circuits
(Note 8) (Continued)
Large Signal Frequency
Response
Large Signal Frequency
Response
20129614
20129610
Large Signal Frequency
Response
Voltage Follower Pulse
Response
20129618
20129611
Voltage Follower Pulse
Response
Inverter Pulse Response
20129615
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20129619
12
(Note 8)
LM101AJAN
Typical Applications
Inverting Amplifier
with Balancing Circuit
Variable Capacitance Multiplier
20129620
20129623
†May be zero or equal to parallel combination of R1 and R2 for minimum
Simulated Inductor
offset.
Sine Wave Oscillator
20129621
L . R1 R2 C1
RS = R2
RP = R1
Fast Inverting Amplifier
with High Input Impedance
20129624
fo = 10 kHz
Integrator with Bias Current Compensation
20129622
20129625
*Adjust for zero integrator drift. Current drift typically 0.1 nA/˚C over −55˚C
to +125˚C temperature range.
13
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LM101AJAN
Application Hints (Note 8)
Protecting Against Gross
Fault Conditions
20129626
*Protects input
†Protects output
‡ Protects output — not needed when R4 is used.
Compensating for Stray Input Capacitances
or Large Feedback Resistor
20129627
Isolating Large Capacitive Loads
20129628
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14
Typical Applications
LM101AJAN
Although the LM101A is designed for trouble free operation,
experience has indicated that it is wise to observe certain
precautions given below to protect the devices from abnormal operating conditions. It might be pointed out that the
advice given here is applicable to practically any IC op amp,
although the exact reason why may differ with different devices.
(Note 8)
Standard Compensation and
Offset Balancing Circuit
When driving either input from a low-impedance source, a
limiting resistor should be placed in series with the input lead
to limit the peak instantaneous output current of the source
to something less than 100 mA. This is especially important
when the inputs go outside a piece of equipment where they
could accidentally be connected to high voltage sources.
Large capacitors on the input (greater than 0.1 µF) should be
treated as a low source impedance and isolated with a
resistor. Low impedance sources do not cause a problem
unless their output voltage exceeds the supply voltage. However, the supplies go to zero when they are turned off, so the
isolation is usually needed.
The output circuitry is protected against damage from shorts
to ground. However, when the amplifier output is connected
to a test point, it should be isolated by a limiting resistor, as
test points frequently get shorted to bad places. Further,
when the amplifier drives a load external to the equipment, it
is also advisable to use some sort of limiting resistance to
preclude mishaps.
Precautions should be taken to insure that the power supplies for the integrated circuit never become
reversed — even under transient conditions. With reverse
voltages greater than 1V, the IC will conduct excessive current, fusing internal aluminum interconnects. If there is a
possibility of this happening, clamp diodes with a high peak
current rating should be installed on the supply lines. Reversal of the voltage between V+ and V− will always cause a
problem, although reversals with respect to ground may also
give difficulties in many circuits.
The minimum values given for the frequency compensation
capacitor are stable only for source resistances less than
10 kΩ, stray capacitances on the summing junction less than
5 pF and capacitive loads smaller than 100 pF. If any of
these conditions are not met, it becomes necessary to overcompensate the amplifier with a larger compensation capacitor. Alternately, lead capacitors can be used in the feedback
network to negate the effect of stray capacitance and large
feedback resistors or an RC network can be added to isolate
capacitive loads.
Although the LM101A is relatively unaffected by supply bypassing, this cannot be ignored altogether. Generally it is
necessary to bypass the supplies to ground at least once on
every circuit card, and more bypass points may be required
if more than five amplifiers are used. When feed-forward
compensation is employed, however, it is advisable to bypass the supply leads of each amplifier with low inductance
capacitors because of the higher frequencies involved.
20129629
Fast Voltage Follower
20129631
Power Bandwidth: 15 kHz
Slew Rate: 1V/µs
Fast Summing Amplifier
20129630
Power Bandwidth: 250 kHz
Small Signal Bandwiidth: 3.5 MHz
Slew Rate: 10V/µs
15
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LM101AJAN
Typical Applications (Note 8)
(Continued)
Bilateral Current Source
20129632
R3 = R4 + R5
R1 = R2
Fast AC/DC Converter (Note 9)
20129633
Note 9: Feedforward compensation can be used to make a fast full wave rectifier without a filter.
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16
LM101AJAN
Typical Applications (Note 8)
(Continued)
Instrumentation Amplifier
20129634
R1 = R4; R2 = R3
*,† Matching determines CMRR.
Voltage Comparator for Driving RTL Logic or High
Current Driver
Integrator with Bias Current Compensation
20129637
20129635
*Adjust for zero integrator drift. Current drift typically 0.1 nA/˚C over 0˚C to
+70˚C temperature range.
17
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LM101AJAN
Typical Applications (Note 8)
(Continued)
Low Frequency Square Wave Generator
20129636
Voltage Comparator for Driving
DTL or TTL Integrated Circuits
Low Drift Sample and Hold
20129639
20129638
*Polycarbonate-dielectric capacitor
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18
Date
Released
01/05/06
Revision
A
Section
Originator
Changes
New Release to corporate format
L. Lytle
1 MDS datasheets converted into one Corp.
datasheet format. MJLM101A-X Rev 1A0
datasheet will be archived.
19
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LM101AJAN
Revision History Section
LM101AJAN
Physical Dimensions
inches (millimeters) unless otherwise noted
Metal Can Package (H)
NS Package Number H08C
Ceramic Dual-In-Line Package (J)
NS Package Number J08A
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20
LM101AJAN
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Ceramic Dual-In-Line Package (J)
NS Package Number J14A
Ceramic Flatpack Package (W)
NS Package Number W10A
21
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LM101AJAN Operational Amplifiers
Notes
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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