A1PROS IMP811TEUS-T

IMP8 1 1 , IMP81 2
POWER MANAGEMENT
4-Pin µ P Volt ag e Super visor
wit h Manual R eset
The IMP811/IMP812 are low-power supervisors designed to monitor
voltage levels of 3.0V, 3.3V and 5.0V power supplies in low-power
microprocessor (µP), microcontroller (µC) and digital systems. Each features a debounced manual reset input. The IMP811/812 are improved
drop-in replacements for the Maxim MAX811/812 with extended
temperature specifications to 105°C.
Key Features
◆ Improved Maxim MAX811/MAX812 replacement
— Specified to 105°C
— New 4.0V threshold option
◆ 6µA supply current
◆ Monitor 5V, 3.3V and 3V supplies
◆ Manual reset input
A reset signal is issued if the power supply voltage drops below a preset
threshold and is asserted for at least 140ms after the supply has risen
above the reset threshold. The IMP811 has an active-low output RESET
that is guaranteed to be in the correct state for VCC down to 1.1V. The
IMP812 has an active-high output RESET. The reset comparator is
designed to ignore fast transients on VCC .
◆ 140ms min. reset pulse width
Low power consumption makes the IMP811/IMP812 ideal for use in
portable and battery-operated equipment. Available in a compact 4-pin
SOT143 package, the devices use minimal board space.
◆ No external components
◆ Guaranteed over temperature
◆ Active-LOW reset valid with 1.1V supply
(IMP811)
◆ Small 4-pin SOT-143 package
◆ Power-supply transient-immune design
Six voltage thresholds are available to support 3V to 5V systems:
Reset Threshold
Suffix
Voltage (V)
L
◆
◆
◆
◆
◆
◆
4.63
M
4.38
J
4.00
T
3.08
S
2.93
R
2.63
Applications
Computers and controllers
Embedded controllers
Battery operated systems
Intelligent instruments
Wireless communication systems
PDAs and handheld equipment
Block Diagrams
VCC
VCC
IMP811
(IMP812)
MR
Manual
Reset
RESET
(RESET)
GND
VCC
µC or µP
RESET
Input
GND
811/12_01.eps
IMP, Inc.
San Jose, CA
408-432-9100/www.impweb.com
IMP8 1 1 , IMP81 2
Pin Configuration
SOT143
GND
1
4
VCC
3
MR
IMP811
(IMP812)
(RESET) RESET
2
811/12_02.eps
Ordering Information
Part Number 1
Reset Threshold (V)
Temperature Range
IMP811 Active LOW Reset with Active LOW Manual Reset
Pin-Package
Package Marking2
(XX Lot Code)
AMXX
IMP811LEUS-T
4.63
– 40°C to +105°C
4-SOT143
IMP811MEUS-T
4.38
– 40°C to +105°C
4-SOT143
ANXX
IMP811JEUS-T
4.00
– 40°C to +105°C
4-SOT143
AOXX
IMP811TEUS-T
3.08
– 40°C to +105°C
4-SOT143
APXX
IMP811SEUS-T
2.93
– 40°C to +105°C
4-SOT143
AQXX
IMP811REUS-T
2.63
– 40°C to +105°C
4-SOT143
ARXX
IMP812 Active HIGH Reset with Active LOW Manual Reset
IMP812LEUS-T
4.63
– 40°C to +105°C
4-SOT143
ASXX
IMP812MEUS-T
4.38
– 40°C to +105°C
4-SOT143
ATXX
IMP812JEUS-T
4.00
– 40°C to +105°C
4-SOT143
AUXX
IMP812TEUS-T
3.08
– 40°C to +105°C
4-SOT143
AVXX
IMP812SEUS-T
2.93
– 40°C to +105°C
4-SOT143
AWXX
IMP812REUS-T
2.63
– 40°C to +105°C
4-SOT143
AXXX
Notes:
1. Tape and Reel packaging is indicated by the -T designation.
2. Devices may also be marked with full part number: 811L, 812M etc. XX refers to lot.
Absolute Maximum Ratings
Pin Terminal Voltage with Respect to Ground
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 6.0V
RESET,RE SET andM
R . . . . . . . . . . . . . . . . . –0.3V to (VCC + 0.3V)
Input Current at VCC andM
R . . . . . . . . . . . 20mA
Output Current: RESET orRE SET . . . . . . 20mA
Rate of Rise at VCC . . . . . . . . . . . . . . . . . . . . 100V/µs
These are stress ratings only and functional operation is not implied.
Exposure to absolute maximum ratings for prolonged time periods may
affect device reliability
2
Power Dissipation (TA = 70°C) . . . . . . . . . . 320mW
(Derate SOT-143 4mW/°C above 70°C)
Operating Temperature Range . . . . . . . . . . –40°C to 105°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to 160°C
Lead Temperature (soldering, 10 sec) . . . . . 300°C
IMP8 1 1 , IMP8 1 2
Electrical Characteristics
Unless otherwise noted VCC is over the full voltage range, TA = –40°C to 105°C.
Typical values at TA = 25°C, VCC = 5V for L/M/J devices, VCC = 3.3V for T/S devices and VCC = 3V for R devices.
Parameter
Symbol Conditions
Input Voltage (VCC) Range
VCC
Supply Current (Unloaded)
ICC
Reset Threshold
VTH
TA = 0°C to 70°C
TA = – 40°C to 105°C
TA = – 40°C to 85°C
TA = – 40°C to 85°C
TA = 85°C to 105°C
TA = 85°C to 105°C
L devices
M devices
J devices
T devices
S devices
R devices
Reset Threshold Temp. Coefficient
VCC to Reset Delay
VOL
MR Minimum Pulse Width
MR Glitch Immunity
MR to RESET Propagation Delay
MR Input Threshold
tMR
tMD
VIH
VIL
VIH
VIL
MR Pull-up Resistance
Low RESET Output Voltage (IMP811)
VOL
High RESET Output Voltage (IMP811)
VOH
Low RESET Output Voltage (IMP812)
VOL
High RESET Output Voltage (IMP812)
VOH
Typ
1.1
1.2
VCC < 5.5V, L/M/J
VCC < 3.6V, R/S/T
VCC < 5.5V, L/M/J
VCC < 3.6V, R/S/T
TA = 25°C
TA = – 40°C to 85°C
TA = 85°C to 105°C
TA = 25°C
TA = – 40°C to 85°C
TA = 85°C to 105°C
TA = 25°C
TA = – 40°C to 85°C
TA = 85°C to 105°C
TA = 25°C
TA = – 40°C to 85°C
TA = 85°C to 105°C
TA = 25°C
TA = – 40°C to 85°C
TA = 85°C to 105°C
TA = 25°C
TA = – 40°C to 85°C
TA = 85°C to 105°C
6
5
4.56
4.50
4.40
4.31
4.25
4.16
3.93
3.89
3.80
3.04
3.00
2.92
2.89
2.85
2.78
2.59
2.55
2.50
TCVTH
Reset Active Timeout Period
Notes:
Min
VCC = VTH to (VTH - 125mV), L/M/J devices
VCC = VTH to (VTH - 125mV), R/S/T devices
TA = 0°C to 70°C
TA = – 40°C to 105°C
Note 3
Note 2
VCC > VTH (MAX), IMP811/812L/M/J
4.63
4.38
4.00
3.08
2.93
2.63
Max
Units
5.5
5.5
15
10
25
20
4.70
4.75
4.86
4.45
4.50
4.56
4.06
4.10
4.20
3.11
3.15
3.23
2.96
3.00
3.08
2.66
2.70
2.76
V
30
40
20
140
100
10
µA
V
ppm/°C
µs
560
840
ms
µs
ns
µs
V
100
0.5
2.3
0.8
VCC > VTH (MAX), IMP811/812R/S/T
0.7VCC
10
VCC = VTH min., ISINK = 1.2mA, IMP811R/S/T
VCC = VTH min., ISINK = 3.2mA, IMP811L/M/J
VCC > 1.1V, ISINK = 50µA
VCC > VTH max., ISOURCE = 500µA, IMP811R/S/T 0.8VCC
VCC > VTH max., ISOURCE = 800µA, IMP811L/M/J VCC -1.5
VCC = VTH max., ISINK = 1.2mA, IMP812R/S/T
VCC = VTH max., ISINK = 3.2mA, IMP812L/M/J
1.8V < VCC < VTH min., ISOURCE = 150µA
0.8VCC
20
0.25VCC
30
0.3
0.4
0.3
kΩ
V
V
0.3
0.4
V
V
1. Production testing done at TA = 25°C. Over temperature specifications guaranteed by design only using six sigma design limits.
2.R
ESET output is active LOW for the IMP811 and RESET output is active HIGH for the IMP812.
3. Glitches of 100ns or less typically will not generate a reset pulse.
3
IMP8 1 1 , IMP81 2
Pin Descriptions
Pin Number
Name
1
GND
Function
2
(IMP811)
RESET
RESET is asserted LOW if VCC falls below the reset threshold and remains LOW for the
140ms minimum after the reset conditions are removed. In addition, RESET is active LOW
as long as the manual reset is low.
2
(IMP812)
RESET
RESET is asserted HIGH if VCC falls below the reset threshold and remains HIGH for the
140ms minimum after the reset conditions are removed. In addition, RESET is active
HIGH as long as the manual reset is low.
3
MR
Manual Reset Input. A logic LOW on MR asserts RESET. RESET remains active as long
as MR is LOW and for 180ms after MR returns HIGH. The active low input has an internal
20kΩ pull-up resistor. The input should be left open if not used. It can be driven by TTL or
CMOS logic or shorted to ground by a switch..
4
VCC
Power supply input voltage (3.0V, 3.3V, 5.0V)
Ground
Related Products
Max. Supply Current
Package Pins
Manual RESET input
Package Type
Active-HIGH RESET output
Active-LOW RESET output
4
IMP809
IMP810
IMP811
IMP812
15µA
3
15µA
3
SOT-23
SOT-23
■
15µA
4
■
SOT-143
15µA
4
■
SOT-143
■
■
■
IMP8 1 1 , IMP8 1 2
Detailed Description
Reset Timing and Manual Reset (MR)
The reset signal is asserted–LOW for the IMP811 and HIGH for
the IMP812 – when the VCC signal falls below the threshold trip
voltage and remains asserted for 140ms minimum after the VCC
has risen above the threshold.
MR may be connected to a normally-open switch connected to
ground without an external debounce circuit.
For added noise rejection, a 0.1µF capacitor from MR to Ground
can be added.
A logic low on MR asserts RESET LOW on the IMP811 and HIGH
on the IMP812. MR is internally pulled high through a 20kΩ
resistor and can be driven by TTL/CMOS gates or with open
collector/drain outputs. MR can be left open if not used.
5V
VTH
VCC
0V
Active Reset
Timeout Period
140ms
minimum
5V
MR
0V
Active Reset
Timeout Period
5V
RESET
IMP811
0V
5V
RESET
IMP812
0V
811/12_03.eps
Figure 1. Reset Timing and Manual Reset (MR)
5
IMP8 1 1 , IMP81 2
Application Information
RESET Output Operation
In µP/µC systems it is important to have the processor begin
operation from a known state or be able to return the system to a
known state. A RESET output to a processor is provided to prevent improper operation during power supply sequencing or low
voltage – brownout – conditions.
The IMP811/812 are designed to monitor the system power supply voltages and issue a RESET signal when levels are out of
range. RESET outputs are guaranteed to be active for VCC above
1.1V. When VCC exceeds the reset threshold, an internal timer
keeps RESET active for the reset timeout period, after which
RESET becomes inactive (HIGH for the IMP811 and LOW for the
IMP812).
If VCC drops below the reset threshold, RESET automatically
becomes active. Alternatively, external circuitry or a human operator can initiate this condition using the Manual Reset (MR) pin.
There is an internal pullup on MR so it can be left open if it is not
used. MR can be driven by TTL/CMOS logic or even an external
switch, since it is already debounced. If the switch is at the end of
a long cable, it might require a bypass (100nF) at the pin if noise
pickup is a problem.
Six voltage thresholds are available to support 3V and 5V systems:
Reset Threshold
Suffix
Voltage (V)
L
4.63
M
4.38
J
4.00
T
3.08
S
2.93
R
2.63
Valid Reset with VCC under 1.1V
Negative VCC Transients
To ensure that logic inputs connected to the IMP811 RESET pin
are in a known state when VCC is under 1.1V, a 100kΩ pull-down
resistor at RESET is needed. The value is not critical.
Typically short duration transients of 100mV amplitude and 20µs
duration do not cause a false RESET. A 0.1µF capacitor at VCC
increases transient immunity.
A similar pull-up resistor to VCC is needed with the IMP812.
VCC
VCC
100kΩ
IMP811
Power
Supply
MR
Power
Supply
MR
RESET
100kΩ
GND
811/12_04.eps
Figure 2. RESET Valid with VCC Under 1.1V
6
IMP812
RESET
GND
811/12_05.eps
Figure 3. RESET Valid with VCC Under 1.1V
IMP8 1 1 , IMP8 1 2
Bi-directional Reset Pin Interfacing
The IMP811/812 can interface with µP/µC bi-directional reset
pins by connecting a 4.7kΩ resistor in series with the IMP809/810
reset output and the µP/µC bi-directional reset pin.
BUF
Buffered
RESET
VCC
IMP811
Power
Supply
µC or µP
4.7kΩ
MR
RESET
RESET
Input
GND
GND
Bi-directional I/O Pin
(Example: 68HC11)
811/12_06.eps
Figure 4. Bi-directional Reset Pin Interface
Package Dimensions
Plastic SOT-143 (4-Pin)
Inches
B
e1
Min
E
H
A
0.031
0.047
0.787
1.194
A1
0.001
0.005
0.025
0.127
B
0.014
0.022
0.356
0.559
B1
0.030
0.038
0.762
0.965
C
0.0034
0.006
0.086
0.152
e
D
0.105
0.120
2.667
3.048
D
E
0.047
0.055
1.194
1.397
e
0.070
0.080
1.778
2.032
e1
0.071
0.079
1.803
2.007
H
0.082
0.098
2.083
2.489
I
0.004
0.012
0.102
0.305
B1
a = 0°-8°
A
A1
Millimeters
Max
Min
Max
Plastic SOT-143 (4-Pin)
e
C
L
SOT-143 (4-Pin).eps
7
IMP8 1 1 , IMP81 2
IMP, Inc.
Corporate Headquarters
2830 N. First Street
San Jose, CA 95134-2071
Tel: 408-432-9100
Tel: 800-438-3722
Fax: 408-434-0335
Fax-on-Demand: 1-800-249-1614 (USA)
Fax-on-Demand: 1-303-575-6156 (International)
e-mail: info@impinc.com
http://www.impweb.com
The IMP logo is a registered trademark of IMP, Inc.
All other company and product names are trademarks of their respective owners.
8
© 1998 IMP, Inc.
Printed in USA
Preliminary
Part No.: IMP811-812
Document Number: IMP811-6-6/98