HD3SS213 www.ti.com SLAS901A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 5.4Gbps DisplayPort 1.2a 2:1/1:2 Differential Switch Check for Samples: HD3SS213 FEATURES APPLICATIONS • • 4 4 4 4 DCx(n) AUXAx 2 Source A DDCA 2 DDCC DP Sink AUXCx 2 2 HPDA HPDC 2 2 AUXBx DDCB HPDB OE Source B Dx_SEL Control AUX_SEL DBx(p) DBx(n) HD3SS213 2:1 DAx(p) DCx(p) 4 DAx(n) DP Sink A DCx(n) AUXAx 2 • DCx(p) DAx(n) 4 • DAx(p) 4 • • • 4 • • • • • Motherboard Applications Needing DP and PCI Express Desktop and Notebook Applications – DP switching – PCI Express switching Docking 4 • Compatible with DisplayPort 1.2 Electrical Standard 2:1 and 1:2 Switching Supporting Data Rates up to 5.4Gbps Supports HPD Switching Supports AUX and DDC Switching Wide -3dB Differential BW of over 5.4 GHz Excellent Dynamic Characteristics (at 2.7GHz) – Crosstalk = –50dB – Isolation = –25dB – Insertion Loss = –1.5 dB – Return Loss = –13 dB – Max Bit-Bit Skew = 5 ps VDD Operating Range 3.3 V ±10% Package Options: – 5 mm x 5 mm, 50-Ball µ*BGA Output Enable (OE) Pin Disables Switch to Save Power HD3SS213 < 10 mW (Standby < 30 µW when OE = L) 4 1 2 DDCA DDCC DP Source 2 HPDA 2 AUXCx HPDC 2 AUXBx 2 DDCB HPDB OE DP Sink B Control Dx_SEL AUX_SEL 4 DBx(p) 4 DBx(n) HD3SS213 1:2 Figure 1. HD3SS213 Application Block Diagram DESCRIPTION The HD3SS213 is a high-speed passive switch capable of switching two full DisplayPort 4 lane ports from one of two sources to one target location in an application. It will also switch one source to one of two sinks. For DisplayPort applications the HD3SS213 supports switching of the Auxiliary (AUX), Display Data Channel (DDC) and Hot Plug Detect (HPD) signals in the ZEQ package. One typical application would be a mother board that includes two GPUs that need to drive one DisplayPort sink. The GPU is selected by the Dx_SEL pin. Another application is when one source needs to switch between one of two sinks, example would be a side connector and a docking station connector. The switching is controlled using the Dx_SEL and AUX_SEL pins. The HD3SS213 operates from a single supply voltage of 3.3V over the full industrial temperature range of –40°C to 105°C. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated HD3SS213 SLAS901A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. VDD DAz(p) 4 DAz(n) 4 SEL=0 4 (z = 0, 1, 2 or 3) DBz(p) DBz(n) 4 DCz(p) DCz(n) 4 4 SEL=1 SEL Dx_SEL SEL HPDA SEL=0 HPDB SEL=1 HPDC AUX_SEL AUXA(p) AUXA(n) AUXB(p) AUXB(n) SEL2 SEL AUXx(P) or DDCCLK_x AUXx(n) or DDCDAT_x AUXC(p) AUXC(n) DDCCLK_C DDCDAT_C DDCCLK_A DDCDAT_A DDCCLK_B DDCDAT_B OE HD3SS213 GND Figure 2. HD3SS213ZQE Functional Block Diagram 2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: HD3SS213 HD3SS213 www.ti.com SLAS901A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Ball Map (50-Ball ZQE µ*BGA Package) (Top View) 1 2 A Dx_SEL VDD B DC0(n) DC0(p) C 3 GND 4 5 6 DA0(n) DA1(n) DA2(n) DA0(p) DA1(p) DA2(p) 7 OE 8 9 DA3(p) DA3(n) DB0(p) DB0(n) AUX_SEL GND D DC1(n) DC1(p) DB1(p) DB1(n) E DC2(n) DC2(p) DB2(p) DB2(n) F DC3(n) DC3(p) DB3(p) DB3(n) GND GND G H AUXC(n) AUXC(p) HPDB GND DDCCLK_B AUXB(p) J HPDC HPDA DDCCLK_C VDD DDCDAT_B AUXB(n) GND DDCCLK_A AUXA(p) DDCDAT_C DDCDAT_A AUXA(n) Figure 3. HDS3SS213 Ball Map by Signal Name Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: HD3SS213 3 HD3SS213 SLAS901A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com PIN DESCRIPTIONS PIN ZQE A1 Dx_SEL Control I High Speed Port Selection Control Pins C2 AUX_SEL Control I AUX/DDC Selection Control Pin in Conjunction with Dx_SEL Pin B4 A4 DA0(p) DA0(n) I/O Port A, Channel 0, High Speed Positive Signal Port A, Channel 0, High Speed Negative Signal B5 A5 DA1(p) DA1(n) I/O Port A, Channel 1, High Speed Positive Signal Port A, Channel 1, High Speed Negative Signal B6 A6 DA2(p) DA2(n) I/O Port A, Channel 2, High Speed Positive Signal Port A, Channel 2, High Speed Negative Signal A8 A9 DA3(p) DA3(n) I/O Port A, Channel 3, High Speed Positive Signal Port A, Channel 3, High Speed Negative Signal B8 B9 DB0(p) DB0(n) I/O Port B, Channel 0, High Speed Positive Signal Port B, Channel 0, High Speed Negative Signal D8 D9 DB1(p) DB1(n) I/O Port B, Channel 1, High Speed Positive Signal Port B, Channel 1, High Speed Negative Signal E8 E9 DB2(p) DB2(n) I/O Port B, Channel 2, High Speed Positive Signal Port B, Channel 2, High Speed Negative Signal F8 F9 DB3(p) DB3(n) I/O Port B, Channel 3, High Speed Positive Signal Port B, Channel 3, High Speed Negative Signal B2 B1 DC0(p) DC0(n) I/O Port C, Channel 0, High Speed Positive Signal Port C, Channel 0, High Speed Negative Signal D2 D1 DC1(p) DC1(n) I/O Port C, Channel 1, High Speed Positive Signal Port C, Channel 1, High Speed Negative Signal E2 E1 DC2(p) DC2(n) I/O Port C, Channel 2, High Speed Positive Signal Port C, Channel 2, High Speed Negative Signal F2 F1 DC3(p) DC3(n) I/O Port C, Channel 3, High Speed Positive Signal Port C, Channel 3, High Speed Negative Signal H9 J9 AUXA(p) AUXA(n) I/O Port A AUX Positive Signal Port A AUX Negative Signal H6 J6 AUXB(p) AUXB(n) I/O Port B AUX Positive Signal Port B AUX Negative Signal H2 H1 AUXC(p) AUXC(n) I/O Port C AUX Positive Signal Port C AUX Negative Signal H8 J8 DDCCLK_A DDCDAT_A I/O Port A DDC Clock Signal Port A DDC Data Signal H5 J5 DDCCLK_B DDCDAT_B I/O Port B DDC Clock Signal Port B DDC Data Signal J3 J7 DDCCLK_C DDCDAT_C I/O Port C DDC Clock Signal Port C DDC Data Signal J2 HPDA I/O Port A Hot Plug Detect H3 HPDB I/O Port B Hot Plug Detect J1 HPDC I/O Port C Hot Plug Detect NA CADA/B/C I/O Port A/B/C Cable Activity Detect B7 OE I J4 VDD Supply 3.3V Positive power supply voltage B3, C8, G2, G8 H4, H7 GND Supply Ground (1) 4 DESCRIPTION (1) I/O NAME Output Enable: OE = VIH: Normal Operation OE = VIL: Standby Mode The high speed data ports incorporate 20kΩ pull down resistors that are switched in when a port is not selected and switched out when the port is selected. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: HD3SS213 HD3SS213 www.ti.com SLAS901A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 FUNCTIONAL DESCRIPTION Refer to Figure 2. The HD3SS213 behaves as a two to one or one to two using high bandwidth pass gates. The input ports are selected using the AUX_SEL and Dx_SEL pins which are shown in Table 1. Table 1. AUX/DDC Switch Control Logic CONTROL LINES (1) SWITCHED I/O PINS (2) AUX_SEL Dx_SEL AUXA AUXB AUXC DDCA DDCB DDCC L L To/From AUXC Z To/From AUXA Z Z Z L H Z To/From AUXC To/From AUXB Z Z Z H L Z Z To/From DDCA To/From AUXC Z Z H H Z Z To/From DDCB Z To/From AUXC Z M L To/From AUXC Z To/From AUXA To/From DDCC Z To/From DDCA M H Z To/From AUXC To/From AUXB Z To/From DDCC To/From DDCB (1) (2) The ports which are not selected by the control lines will be in high impedance status. OE pin - For normal operation, drive OE high. Driving the OE pin low will disable the switch. ABSOLUTE MAXIMUM RATINGS (1) (2) over operating free-air temperature range (unless otherwise noted) VALUE Supply voltage range (3) Voltage range Electrostatic discharge MIN MAX VDD –0.5 4 Differential I/O –0.5 4 Control pin –0.5 VDD + 0.5 V ±2000 V Charged-device model (5) ±500 V 105 °C –40 Continuous power dissipation (2) (3) (4) (5) V Human body model (4) Operating free-air temperature (1) UNIT See Thermal Table Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-B Tested in accordance with JEDEC Standard 22, Test Method C101-A Tested in accordance with JEDEC Standard 22, Test Method A115-A THERMAL INFORMATION THERMAL METRIC (1) HD3SS213 HIGH-K BOARD θJA Junction-to-ambient thermal resistance 90.5 θJCtop Junction-to-case (top) thermal resistance 41.9 θJB Junction-to-board thermal resistance 53.9 ψJT Junction-to-top characterization parameter 1.8 ψJB Junction-to-board characterization parameter 53.4 (1) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: HD3SS213 5 HD3SS213 SLAS901A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com RECOMMENDED OPERATING CONDITIONS Typical values for all parameters are at VCC = 3.3 V and TA = 25°C. All temperature limits are specified by design. PARAMETER VDD TEST CONDITIONS Supply voltage VIH Input high voltage Control pins, Signal pins (Dx_SEL, AUX_SEL, OE, HPDx) VIM Input mid level voltage AUX_SEL pin VIL Input low voltage Control pins, Signal pins (Dx_SEL, AUX_SEL, OE, HPDx) VI/O_Diff Differential voltage (Dx, AUXx) Switch I/O diff voltage Dx switching I/O common mode voltage VI/O_CM AUXx switching I/O common mode voltage MIN NOM MAX 3.0 3.3 3.6 V VDD V VDD/2 + 300 mV V -0.1 0.8 V 0 1.8 Vpp 0 2.0 0 3.6 –40 105 °C 2.0 VDD/2 - 300 mV VDD/2 Switch I/O common mode voltage UNITS V Operating free-air temperature IIH Input high current (Dx_SEL, AUX_SEL) VDD = 3.6 V, VIN = VDD 1 µA IIM Input mid level current (AUX_SEL) VDD = 3.6V, VIN = VDD/2 1 µA IIL Input low current (Dx_SEL, AUX_SEL) VDD = 3.6 V, VIN = GND 1 µA Leakage current (Dx_SEL, AUX_SEL) VDD = 3.3 V, VI = 2 V, OE = 3.3 V 1 VDD = 3.3 V, VI = 2 V, OE = 3.3V; Dx_SEL = 3.3 V 1 VDD = 3.3 V, VI = 2 V, OE = 3.3V; Dx_SEL = GND 1 ILK Leakage current (HPDx) Ioff Device shut down current VDD = 3.6 V, OE = GND IDD Supply current VDD = 3.6 V, Dx_SEL/AUX_SEL = VDD/GND 0.6 1.5 µA 2.5 1 mA DA, DB, DC HIGH SPEED SIGNAL PATH CON Outputs ON capacitance VI = 0 V, Outputs Open, Switch ON COFF Outputs OFF capacitance VI = 0 V, Outputs Open, Switch OFF 1 RON ON resistance VDD = 3.3 V, VCM = 0.5 V–1.5 V, IO = –40 mA 8 ΔRON On resistance match between pairs of the same channel VDD = 3.3 V, 0.5 V ≤ VI ≤ 1.2V, IO = –40mA RFLAT_ON On resistance flatness, RON(max) – RON(min) VDD = 3.3 V, 0.5 V ≤ VI ≤ 1.2 V pF pF 12 Ω 1.5 Ω 1.3 Ω pF AUXx, DDC SIGNAL PATH CON Outputs ON capacitance VI = 0 V, Outputs Open, Switch ON 9 COFF Outputs OFF capacitance VI = 0 V, Outputs Open, Switch OFF 3 RON(AUX) ON resistance VDD = 3.3 V, VCM = 0V – VDD, IO = –8 mA 6 10 Ω 20 30 Ω RON(DDC) (1) 6 ON resistance on DDC channel (1) VDD = 3.3V, VCM = 0.4V, IO = -3mA pF For Display port applications, check the connection diagram in Figure 4 and Figure 5. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: HD3SS213 HD3SS213 www.ti.com SLAS901A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 ELECTRICAL CHARACTERISTICS – DEVICE PARAMETERS (1) under recommended operating conditions; RL, RSC = 50 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS Switch propagation delay Ton Dx_SEL/AUX_SEL/-to-Switch Ton (Data, AUX and DDC) Toff Dx_SEL/AUX_SEL/-to-Switch Toff (Data, AUX and DDC) Ton Dx_SEL/AUX_SEL-to-Switch Ton (HPD) Toff Dx_SEL/AUX_SEL-to-Switch Toff (HPD) TSK(O) Inter-Pair Output Skew (CH-CH) TSK(b-b) Intra-pair output skew (bit-bit) Dx Differential return loss XTALK Dx Differential crosstalk OIRR Dx Differential off-isolation IL MAX UNITS 100 ps 0.7 1 µs 0.7 1 0.7 1 0.7 1 RSC and RL = 50 Ω, See Figure 6 RL = 50Ω, See Figure 6 RSC and RL = 1 kΩ, See Figure 7 1 1.35 GHz –17 2.7 GHz –13 2.7 GHz f = 1.35 GHz Dx Differential insertion loss f = 2.7 GHz µs 50 ps 5 ps dB –50 dB –25 dB –1 –1.5 AUX –3dB bandwidth (1) TYP RSC and RL = 50 Ω, See Figure 7 tPD RL MIN 360 dB MHz For Return Loss, Crosstalk, Off-Isolation, and Insertion Loss values the data was collected on a Rogers material board with minimum length traces on the input and output of the device under test. AUX CONNECTION DIAGRAMS Vdd Vbias 50Q AUXa(n) 100K AUXc(n) AUXa(p) Source A AUXc(p) 50Q Vbias 100K Sink connector Vbias 50Q AUXb(n) AUXb(p) Source B OE 50Q Dx_SEL Vbias Control AUX_SEL HD3SS213 2:1 Figure 4. HD3SS213 AUX Channel in 2:1 Application Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: HD3SS213 7 HD3SS213 SLAS901A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com Vdd 100K AUXa(n) AUXc(n) AUXa(p) AUXc(p) Sink connector A 100K Source Vdd 100K AUXb(n) AUXb(p) Sink connector B OE 100K Dx_SEL Control AUX_SEL HD3SS213 1:2 Figure 5. HD3SS213 AUX Channel in 1:2 Application TEST TIMING DIAGRAMS 50% Dx_SEL 90% VOUT 10% Toff Ton Figure 6. Select to Switch Ton and Toff 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: HD3SS213 HD3SS213 www.ti.com SLAS901A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 Vcc Rsc = 50 O DAx/DBx(p) HD3SS213 DCx(p) Rsc = 50 O RLoad = 50 O DCx(n) DAx/DBx(n) RLoad = 50 O SEL DAx/DBx(p) 50% 50% DAx/DBx(n) DCx(p) 50% 50% DCx(n) tP1 t1 tP2 t3 t2 t4 DCx(p) 50% DCx(n) DCy(p) tSK(O) DCy(n) tPD = Max(tp1, tp2) tSK(O) = Difference between tPD for any two pairs of outputs tSK(b-b) = 0.5 X |(t4 ± t3) + (t1 ± t2)| Figure 7. Propagation Delay and Skew Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: HD3SS213 9 HD3SS213 SLAS901A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013 www.ti.com REVISION HISTORY Changes from Original (September 2013) to Revision A • 10 Page Deleted Ordering Information ............................................................................................................................................... 2 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: HD3SS213 PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) HD3SS213IZQET PREVIEW BGA MICROSTAR JUNIOR ZQE 50 250 TBD Call TI Call TI HD3SS213ZQER ACTIVE BGA MICROSTAR JUNIOR ZQE 50 2500 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR (4/5) -40 to 105 HD3SS213 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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