CERAMIC SMD CRYSTAL CLOCK OSCILLATOR WITH VOLTAGE CONTROL Pb RoHS Compliant ALVD FEATURES: • Based on a proprietary digital multiplier • Tri-State Output • Low Phase Jitter • 2.5V to 3.3V +/- 5% operation • Ceramic SMD, low profile package 7.0 x 5.0 x 1.8mm | | | | | | | | | | | | | | | APPLICATIONS: • SONET, xDSL • SDH, CPE • STB STANDARD SPECIFICATIONS: PARAMETERS ABRACON P/N Frequency Range Operating Temperature Storage Temperature Overall Frequency Stability Supply Voltage (Vdd) Voltage Control (Vcc) Symmetry at 1/2 Vdd Output Level Pullability Tristate Function Aging per year RMS Phase Jitter Period Jitter (peak to peak) Phase Noise ALVD Series 750 KHz to 800 MHz 0°C to +70°C (see options) -55°C to +125°C ±50 PPM max. (see options) 3.3V ± 10% 0.3VDC min, 1.65VDC typ, 3.0 VDC max. 40/60% max. See options (PECL, CMOS, or LVDS) ± 50ppm (see option) "1" (VIH>= 0.7* Vdd) or open: Oscillation "0" (VIL < 0.3* Vdd) : Hi Z ±5 ppm max. 3ps typical, 5ps max. (12KHz~20MHz) 35 ps typical -112 dBc/Hz @ 1kHz Offset from 155.52MHz -125 dBc/Hz @ 10kHz Offset from 155.52MHz -123 dBc/Hz @ 100KHz Offset from 155.52MHz -109 dBc/Hz @ 1kHz Offset from 622.08MHz -110 dBc/Hz @ 10kHz Offset from 622.08MHz -109 dBc/Hz @ 100KHz Offset from 622.08MHz PECL: Supply current DD):25mA max (for Fo<24MHz),65mA max (for 24MHz<Fo<96MHz),100mA max (96MHz<Fo<700MHz) Output Logic High: Vdd-1.025V min, V dd-0.880V max. Output Logic Low: Vdd-1.810V min. V dd-1.620V max. Symmetry (Duty Cycle): 45% min, 50% typ, 55% max, Rise time: 0.6nSec typ,1.5nS max Fall time: 0.6nSec typ, 1.5nS max CMOS: Supply current (I DD):15mA max (for Fo<24MHz),30mA max (for 24MHz<Fo<96MHz), 40mA max (96MHz<Fo<700MHz) Output Clock Rise/ Fall Time [10%~90% VDD with 10pF load]: 1.2ns typ, 1.6ns max. Output Clock Duty Cycle [Measured @ 50% VDD]: 45% min, 50% typical, 55% max ABRACON IS ISO 9001 / QS 9000 CERTIFIED Visit www.abracon.com for Terms & Conditions of Sale Revised: 07.11.07 30332 Esperanza, Rancho Santa Margarita, California 92688 tel 949-546-8000 | fax 949-546-8001 | www.abracon.com CERAMIC SMD CRYSTAL CLOCK OSCILLATOR WITH VOLTAGE CONTROL Pb RoHS Compliant ALVD 7.0 x 5.0 x 1.8mm | | | | | | | | | | | | | | | LVDS: Supply current (I DD):25mA max (for Fo<24MHz),45mA max (for 24MHz<Fo<96MHz),80mA max (96MHz<Fo<700MHz) Output Clock Duty Cycle @ 1.25V: 45% min, 50% typical, 55% max Output Differential Voltage (V OD): 247mV min, 355mV typical, 454mV max VDD Magnitude Change (ΔVOD): -50mV min, 50mV max Output High Voltage : VOH = 1.4V typical, 1.6V max. Output Low Voltage: VOL = 0.9V min, 1.1V typical Offset Voltage [RL = 100Ω]: VOS = 1.125V min, 1.2V typical, 1.375V max Offset Magnitude Change [RL = 100Ω]: ΔVOS = 0mV min, 3mV typical, 25mV max Power-off Leakage (IOXD) [Vout=VDD or GND, VDD=0V] = ±1μA typical, ±10μA max. Differential Clock Rise Time (t r) [RL=100Ω, CL=10pF]: 0.2nS min, 0.7nS typical, 1.0nS,max Differential Clock Fall Time (t f) [RL=100Ω, CL=10pF]: 0.2nS min, 0.7nS typical, 1.0nS max PIN ASSIGNMENTS Name PIN # 1 Vc 2 Tristate GND 3 Q 4 5 Q VDD 6 DESRIPTION Voltage Control Tristate Ground PECL, LVDS, or CMOS Output. Complimentary PECL,LVDS, or NC. VDD Connection. TRI-STATE PIN OPERATION: OUTPUT TYPE OPTION Output State (Tri-state) PIN 2 logic level* Enabled Disabled Disabled Enabled Disabled Enabled Disabled Enabled 0 (Default) 1 0 P1 PECL1 1 0 V LVDS 1(Default) 0 C CMOS 1(Default) *Connect to VDD for logic level "1", connect to ground for logic level "0". P PECL OPTIONS & PART IDENTIFICATION: (Left blank if standard) ALVD - Frequency Frequency XX.XXXXMHz Operating Temp. D -10ºC~60ºC E -20ºC~70ºC F -30ºC~70ºC N -30ºC~85ºC L -40ºC~85ºC ABRACON IS ISO 9001 / QS 9000 CERTIFIED - - Frequency Stability R ±25ppm max. K ±30ppm max. H ±35ppm max. Output Level P PECL P1 PECL1 V LVDS C CMOS - Packaging Blank Bulk Tape and T Reel Pullability N100 ±100ppm Visit www.abracon.com for Terms & Conditions of Sale Revised: 07.11.07 30332 Esperanza, Rancho Santa Margarita, California 92688 tel 949-546-8000 | fax 949-546-8001 | www.abracon.com CERAMIC SMD CRYSTAL CLOCK OSCILLATOR WITH VOLTAGE CONTROL Pb RoHS Compliant ALVD 7.0 x 5.0 x 1.8mm | | | | | | | | | | | | | | | OUTLINE DRAWING: Dimensions: Inches (mm) PIN 1 2 3 4 *5 6 FUNCTION Vc Tri-state GND Q Q VDD Note: It is recommended to use an approximately 0.01uF bypass capacitor between PIN 3 and 6. *Complimentary PECL/LVDS or NC. TAPE & REEL: Dimensions: mm ABRACON IS ISO 9001 / QS 9000 CERTIFIED Visit www.abracon.com for Terms & Conditions of Sale Revised: 07.11.07 30332 Esperanza, Rancho Santa Margarita, California 92688 tel 949-546-8000 | fax 949-546-8001 | www.abracon.com