CD74FCT861A Data sheet acquired from Harris Semiconductor SCHS268 January 1997 Features BiCMOS FCT Interface Logic, 10-Bit Bus Transceiver, Three-State D ENDE M M O S EC IGN NOT R NEW DES ology n Tech FOR MOS Use C • Buffered Inputs • Typical Propagation Delay: 6.0ns at VCC = 5V, TA = 25oC, CL = 50pF • CD74FCT861A - Noninverting • • • • • • Circuit Design Speed of Bipolar FAST™/AS/S 48mA Output Sink Current Output Voltage Swing Limited to 3.7V at VCC = 5V Controlled Output Edge Rates Input/Output Isolation to VCC BiCMOS Technology with Low Quiescent Power • SCR Latchup Resistant BiCMOS Process and Ordering Information PART NUMBER CD74FCT861AM TEMP. RANGE (oC) 0 to 70 PKG. NO. PACKAGE 24 Ld SOIC M24.3 NOTE: When ordering the suffix M package, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. Pinout CD74FCT861A (SOIC) TOP VIEW 24 VCC OEBA 1 A0 2 23 B0 A1 3 22 B1 A2 4 21 B2 A3 5 20 B3 A4 6 19 B4 A5 7 18 B5 A6 8 17 B6 A7 9 16 B7 A8 10 15 B8 A9 11 14 B9 13 OEAB GND 12 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST™ is a trademark of Fairchild Semiconductor. Copyright © Harris Corporation 1996 8-1 File Number 2392.2 CD74FCT861A Functional Diagram A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 13 OEAB OEBA B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 1 GND = PIN 12 VCC = PIN 24 TRUTH TABLE (Note 1) INPUTS OUTPUTS OEBA OEAB B A B A FUNCTION L H L N/A N/A L B Data to A Bus L H H N/A N/A H B Data to A Bus H L N/A L L N/A A Data to B Bus H L N/A H H N/A A Data to B Bus H H X X Z Z High Z L L - - - - A Data to B Bus, B Data to A Bus NOTE: 1. H= HIGH Voltage Level L = LOW Voltage Level N/A = Not Applicable X = Immaterial Z = HIGH Impedance IEC Logic Symbol CD74FCT861A 13 1 2 EN 1 23 2 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 8-2 CD74FCT861A Absolute Maximum Ratings Thermal Information DC Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V DC Diode Current, IIK (For VI < -0.5V) . . . . . . . . . . . . . . . . . . -20mA DC Output Diode Current, IOK (for VO < -0.5V) . . . . . . . . . . . -50mA DC Output Sink Current per Output Pin, IO . . . . . . . . . . . . . . . 70mA DC Output Source Current per Output Pin, IO . . . . . . . . . . . . -30mA DC VCC Current (ICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264mA DC Ground Current (IGND). . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA Thermal Resistance (Typical, Note 2) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (Lead Tips Only) Operating Conditions Operating Temperature Range, TA . . . . . . . . . . . . . . . . .0oC to 70oC Supply Voltage Range, VCC . . . . . . . . . . . . . . . . . . .4.75V to 5.25V DC Input Voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC DC Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to ≤ VCC Input Rise and Fall Slew Rate, dt/dv. . . . . . . . . . . . . . . . 0 to 10ns/V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Commercial Temperature Range 0oC to 70oC, VCC Max = 5.25V, VCC Min = 4.75V AMBIENT TEMPERATURE (TA) 25oC TEST CONDITIONS PARAMETER SYMBOL VI (V) IO (mA) VCC (V) MIN 0oC TO 70oC MAX MIN MAX UNITS High Level Input Voltage VIH 4.75 to 5.25 2 - 2 - V Low Level Input Voltage VIL 4.75 to 5.25 - 0.8 - 0.8 V High Level Output Voltage VOH VIH or VIL -15 Min 2.4 - 2.4 - V Low Level Output Voltage VOL VIH or VIL 48 Min - 0.55 - 0.55 V High Level Input Current IIH VCC Max - 0.1 - 1 µA Low Level Input Current IIL GND Max - -0.1 - -1 µA IOZH VCC Max - 0.5 - 10 µA IOZL GND Max - -0.5 - -10 µA Input Clamp Voltage VIK VCC or GND Min - -1.2 - -1.2 V Short Circuit Output Current (Note 3) IOS VO = 0 VCC or GND Max -75 - -75 - mA Quiescent Supply Current, MSI ICC VCC or GND Max - 8 - 80 µA ∆ICC 3.4V (Note 4) Max - 1.6 - 1.6 mA Three State Leakage Current Additional Quiescent Supply Current per Input Pin TTL Inputs High, 1 Unit Load -18 0 NOTES: 3. Not more than one output should be shorted at one time. Test duration should not exceed 100ms. 4. Inputs that are not measured are at VCC or GND. 5. FCT Input Loading: All inputs are 1 unit load. Unit load is ∆ICC limit specified in Static Characteristics Chart, e.g., 1.6mA Max at 70oC. 8-3 CD74FCT861A Switching Specifications Over Operating Range FCT Series tr, tf = 2.5ns, CL = 50pF, RL (Figure 1) 25oC 0oC TO 70oC SYMBOL VCC (V) TYP MIN MAX UNITS Data to Outputs tPLH, tPHL 5 (Note 6) 6 1.5 8 ns Output Enable to Output tPZL, tPZH 5 9 1.5 12 ns Output Disable to Output tPLZ, tPHZ 5 7.5 1.5 10 ns CPD (Note 7) - - - - pF Minimum (Valley) VOHV During Switching of Other Outputs (Output Under Test Not Switching) VOHV 5 0.5 - - V Maximum (Peak) VOLP During Switching of Other Outputs (Output Under Test Not Switching) VOLP 5 1 - - V Input Capacitance CI - - - 10 pF Three-State Output Capacitance CO - - - 15 pF PARAMETER Propagation Delays Power Dissipation Capacitance NOTES: 6. 5V: Minimum is at 5.25V for 0oC to 70oC, Maximum is at 4.75V for 0oC to 70oC, Typical is at 5V. 7. CPD, measured per flip-flop, is used to determine the dynamic power consumption. PD (per package) = VCC ICC + Σ(VCC2 fI CPD + VO2 fOCL + VCC ∆ICC D) where: VCC = supply voltage ∆ICC = flow through current x unit load CL = output load capacitance D = duty cycle of input high fO = output frequency fI = input frequency 8-4 CD74FCT861A 8-5 Test Circuits and Waveforms VCC tr, tf = 2.5ns (NOTE 8) VI 3V 0 PULSE ZO GEN SWITCH POSITION 7V 500Ω RL V0 DUT CL 50pF RT RT = ZO 500Ω RL 8. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; ZOUT ≤ 50Ω; tf, tr ≤ 2.5ns. FIGURE 1. TEST CIRCUIT Closed tPHZ, tPZH, tPLH, tPHL Open 3V 1.5V 0V DATA INPUT tH 3V 1.5V 0V TIMING INPUT tREM ASYNCHRONOUS CONTROL SWITCH DEFINITIONS: CL = Load capacitance, includes jig and probe capacitance. RT = Termination resistance, should be equal to ZOUT of the Pulse Generator. VIN = 0V to 3V. Input: tr = tf = 2.5ns (10% to 90%), unless otherwise specified NOTE: tSH TEST tPLZ, tPZL, Open Drain 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tSH 3V 1.5V 0V tH HIGH-LOW-HIGH PULSE FIGURE 2. SETUP, HOLD, AND RELEASE TIMING ENABLE 1.5V FIGURE 3. PULSE WIDTH DISABLE 3V 3V SAME PHASE INPUT TRANSITION 1.5V CONTROL INPUT 0V 3.5V OUTPUT NORMALLY LOW SWITCH CLOSED SWITCH OPEN tPHL 3.5V VOH 1.5V 1.5V VOL OUTPUT 0.3V tPZH OUTPUT NORMALLY HIGH tPLH tPLZ tPZL 1.5V tPHZ 0.3V VOL tPLH tPHL VOH 3V OPPOSITE PHASE INPUT TRANSITION 1.5V 0V 0V 0V 1.5V 0V FIGURE 4. ENABLE AND DISABLE TIMING FIGURE 5. PROPAGATION DELAY 8-6 Test Circuits and Waveforms (Continued) VOH OTHER OUTPUTS VOL VOH OUTPUT UNDER TEST VOHV VOLP VOL NOTES: 9. VOLP is measured with respect to a ground reference near the output under test. VOHV is measured with respect to VOH. 10. Input pulses have the following characteristics: PRR ≤ 1MHz, tr = 2.5ns, tf = 2.5ns, skew 1ns. 11. R.F. fixture with 700MHz design rules required. IC should be soldered into test board and bypassed with 0.1µF capacitor. Scope and probes require 700MHz bandwidth. FIGURE 6. SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS 8-7 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CD74FCT861AM OBSOLETE SOIC DW 24 TBD Call TI Call TI CD74FCT861AM96 OBSOLETE SOIC DW 24 TBD Call TI Call TI Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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