TI TPD4S214YFFR

TPD4S214
www.ti.com
SLVSBR1A – JANUARY 2013 – REVISED FEBRUARY 2013
USB OTG Companion Device with VBUS Over Voltage, Over Current Protection, and Four
Channel ESD Clamps
Check for Samples: TPD4S214
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Input Voltage Protection at VBUS from –7 V to
30 V
Low RDS(ON) N-CH FET Switch for High
Efficiency
Compliant with USB2.0 and USB3.0 OTG spec
User Adjustable Current Limit From 250 mA to
Beyond 1.2 A
Built-in Soft-start
Reverse Current Blocking
Over Voltage Lock Out for VBUS
Under Voltage Lock Out for VOTG_IN
Thermal Shutdown and Short Circuit
Protection
Auto Retry on any Fault; no Latching off
States
Integrated VBUS Detection Circuit
Low Capacitance TVS ESD Clamp for USB2.0
High Speed Data Rate
Internal 16ms Startup Delay
ESD Performance D+, D-, ID, VBUS PINS
– ±15-kV Contact Discharge (IEC 61000-4-2)
– ±15-kV Air Gap Discharge (IEC 61000-4-2)
Space Saving WCSP (12-YFF) Package
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APPLICATIONS
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Cell Phones
Tablet, eBook
Set-Top Box
Portable Media Players
Digital Camera
YFF PACKAGE
(TOP SIDE/SEE-THROUGH VIEW)
1.4-mm
12-YFF Pin Proposal
1
2
3
A
V OTG_IN
DET
VBUS
B
V OTG_IN
FLT\
VBUS
C
EN
GND
ID
D
ADJ
D-
D+
DESCRIPTION
The TPD4S214 is a single-chip protection solution for USB On-the-Go and other current limited USB
applications. This device includes an integrated low (RDS(ON) N-channel current limited switch for OTG current
supply to peripheral devices. TPD4S214 offers low capacitance TVS ESD clamps for the D+, D-, ID pins for both
USB2.0 and USB3.0 applications. The VBUS pin can handle continuous voltage ranging from –7 V to 30 V. The
over voltage lock-out (OVLO) at the VBUS pin ensures that if there is a fault condition at the VBUS line, the
TPD4S214 is able to isolate it and protects the internal circuitry from damage. Similarly, the under voltage lock
out (UVLO) at the VOTG_IN pin ensures that there is no power drain from the internal OTG supply to external VBUS
if VOTG_IN droops below safe operating level.
When EN is high, the OTG switch is activated and the FLT pin indicates whether there is a fault condition. The
soft start feature waits 16 ms to turn on the OTG switch after all operating conditions are met. The FLT pin
asserts low during any one of the following fault conditions: OVLO (VBUS > VOVLO), UVLO condition (VOTG_IN <
VUVLO) over temperature, over current, short circuit condition, or reverse-current-condition (VBUS > VOTG_IN). The
OTG switch is turned off during any fault condition. Once the switch is turned off, the IC periodically rechecks the
faults internally. If the IC returns to normal operating conditions, the switch turns back on and FLT is reset to
high.
There is also a VBUS detection feature for facilitating USB communication between USB host and peripheral
device. See Table 2 for detection scheme. If this is not used, DET pin can be either floating or connected to
ground.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2013, Texas Instruments Incorporated
PRODUCT PREVIEW
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1.7-mm
FEATURES
1
TPD4S214
SLVSBR1A – JANUARY 2013 – REVISED FEBRUARY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGE (1) (2)
TA
–40°C to 85°C
(1)
(2)
WCSP – YFF (0.4-mm pitch)
ORDERABLE PART
NUMBER
TOP-SIDE MARKING
TPD4S214YFFR
B3214
Tape and reel
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
CIRCUIT SCHEMATIC DIAGRAM
DET
OTG Switch
VOTG_IN
PRODUCT PREVIEW
Current Limiting
Internal
Band Gap
Referance
VBUS
UVLO
VBUS Detection
+
OVLO
ADJ
FLT
Control Logic
+
Charge Pump
EN
GND
D+
D–
ID
Figure 1. Circuit Schematic
2
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Table 1. Device Operation
EN
VOTG_IN
VBUS
OCP
OTP
OTG SW
FLT
X
0
0
F
F
OFF
L
FAULT CONDITION
SW Disabled
X
X
X
X
T
OFF
L
Over Temperature
H
X
X
T
X
OFF
L
Over Current
H
VOTG_IN > VUVLO
VBUS > VOTG_IN
F
F
OFF
L
Reverse-current
H
X
VBUS > VOVLO
F
F
OFF
L
VBUS over-voltage
H
VOTG_IN < VUVLO
X
F
F
OFF
L
VOTG_IN under-voltage
H
VOTG_IN > VBUS and
VOTG_IN > VUVLO
VSHORT < VBUS < VOTG_IN and
VSHORT < VBUS < VOVLO
F
F
ON
H
Normal (SW Enabled)
Table 2. VBUS Detection Scheme (1)
(1)
EN
VOTG_IN (VBUS Detect Power)
VBUS
DET
X
X
VBUS_VALID- < VBUS < VBUS_VALID+
H
VBUS within VBUS_VALID
Condition
X
X
VBUS_VALID+ > VBUS or VBUS > VBUS_VALID+
L
VBUS outside of VBUS_VALID
X = Don’t Care, H = Signal High, and L = Signal Low
PIN
PRODUCT PREVIEW
PIN FUNCTIONS
DESCRIPTION
NAME
YFF
DRC
TYPE
D–
D2
TBD
I/O
USB data–
D+
D3
TBD
I/O
USB data+
ID
C3
TBD
I/O
USB ID signal
FLT
B2
TBD
O
Open-Drain Output. Connect a pullup resistor from FLT\ to the supply voltage of the
host system.
ADJ
D1
TBD
I
Attach external resistor to adjust the current limit
EN
C1
TBD
I
Enable Input. Drive EN high to enable the OTG switch.
VBUS
A3, B3
TBD
O
USB Power Output
VOTG_IN
A1, B1
TBD
I
USB OTG Supply Input
DET
A2
TBD
O
Open-Drain Output. Connect a pullup resistor from DET to the supply voltage of the
host system.
GND
C2
Thermal
Pad
Ground
Connect to PCB ground plane
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TPD4S214
SLVSBR1A – JANUARY 2013 – REVISED FEBRUARY 2013
ABSOLUTE MAXIMUM RATINGS
www.ti.com
(1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN
VOTG_IN, ADJ, EN
Input voltage
VBUS
Output voltage to USB connector
FLT, DET
Output voltage
–0.5
7
–7
30
–0.5
Input clamp current VI < 0
IOUT Continuous current through FLT and DET output
IGND Continuous current through GND
TJ(max) maximum junction temperature
MAX
–65
UNIT
V
7
-50
mA
10
mA
100
mA
150
°C
D+, D-, ID, VBUS
pins
IEC 61000-4-2 Contact Discharge at 25°C
±15
kV
D+, D-, ID, VBUS
pins
IEC 61000-4-2 Air-gap Discharge at 25°C
±15
kV
All pins
Human-Body Model at 25°C
±2
kV
D+, D-, ID pins
Peak Pulse Current (tp = 8/20 μs) at 25°C
7.8
A
D+, D-, ID pins
Peak Pulse Power (tp = 8/20 μs) at 25°C
84
W
(1)
PRODUCT PREVIEW
(2)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
TA
Operating free-air temperature
-40
VIH
High-level input voltage EN
1.2
VIL
Low-level input voltage EN
tEN
EN ramp rate for proper turn on
Valid ramp rate is between 10us and 100ms,
rising and falling
tUVLO_SLEW
VOTG_IN ramp rate for proper UVLO
operation
tOVLO_SLEW
VBUS ramp rate for proper OVLO
operation
TA_VBUS_ATT
Time to detect VBUS device attachment and turn on DET
TYP
MAX
85
UNIT
°C
V
0.4
V
0.01
100
ms
Valid ramp rate is between 10us and 100ms,
rising and falling
0.01
100
ms
Valid ramp rate is between 10us and 100ms,
rising and falling
0.01
100
ms
200
ms
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
THERMAL METRICS (1)
θJA
(1)
4
Package thermal impedance
Package thermal impedance
YFF
UNITS
89.1
°C/W
The published θJA was modeled assuming a 76mm x 114mm PCB with 4 copper layers and the exposed land pad of the PCB has
thermal vias connecting the exposed center pad of the package to an internal GND plane for maximum heat dissipation. For more
information about traditional and new thermal metrics, see the IC Package Metrics application report, SPRA953A.
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SLVSBR1A – JANUARY 2013 – REVISED FEBRUARY 2013
ELECTRICAL CHARACTERISTICS FOR EN, FLT, DET, D+, D–, VBUS, ID Pins
over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IIL_EN
EN pin input leakage current
EN = 3.3 V
1
IOL
FLT\, DET pin output leakage current
FLT, DET = 3.6 V
1
µA
VOL_FLT
Low-level output voltage FLT\
VBUS or VOTG_IN = 5 V or 0 V IOL = 100 µA
100
mV
VOL_DET
Low-level output voltage DET
VBUS and VOTG_IN = 5 V or 0 V IOL = 100 µA
100
mV
CEN
Enable capacitance
VBIAS = 1.8 V, f = 1 MHz, 30 mVpp ripple,
VOTG_IN = 5 V
VD
Diode forward voltage D+, D–, ID pins;
lower clamp diode
IO = 8 mA
0.95
V
IL_D
Leakage current on D+, D–, ID Pins
D+, D–, ID = 3.3 V
100
nA
ΔCIO
Differential capacitance between the D+,
D– lines
VBIAS = 1.8 V, f = 1 MHz, 30 mVpp ripple,
VOTG_IN = 5 V
0.04
pF
CIO
Capacitance to GND for the D+, D– lines VBIAS = 1.8 V, f = 1 MHz, 30 mVpp ripple,
VOTG_IN = 5 V
Capacitance to GND for the ID lines
VBR
RDYN
4.5
µA
pF
1.9
pF
1.9
Breakdown voltage D+, D–, ID pins
Ibr = 1 mA
6
V
Breakdown voltage on Vbus
Ibr = 1 mA
33
V
Dynamic on resistance D+, D–, ID
clamps
Ω
1
PRODUCT PREVIEW
PARAMETER
ELECTRICAL CHARACTERISTICS FOR UVLO / OVLO
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
INPUT UNDER-VOLTAGE LOCKOUT
VUVLO+
Under-voltage lock-out, input power
detected threshold rising
VOTG_IN increasing from 0 V to 5 V, No load on
VBUS pin
3.4
3.6
3.8
V
VUVLO–
Under-voltage lock-out, input power
detected threshold falling
VOTG_IN decreasing from 5 V to 0 V, No load on
VBUS pin
3.0
3.2
3.5
V
VHYS-UVLO
Hysteresis on UVLO
Δ of VUVLO+ and VUVLO–
TRUVLO
Recovery time from UVLO
TRESP_UVLO
Response time for UVLO
260
mV
VOTG_IN increasing from 0V to 5V, No load on
VBUS pin;
time from VOTG_IN = VUVLO+ to FLT toggles high
18
ms
VOTG_IN decreasing from 5V to 0V, No load on
VBUS pin;
time from VOTG_IN = VUVLO– to FLT\ toggles low
0.18
µs
OUTPUT OVERVOLTAGE LOCKOUT
VOVP+
OVLO rising threshold
Both VOTG_IN and VBUS increasing from 5 V to 7
V
5.55
6.15
6.45
V
VOVP–
OVLO falling threshold
Both VOTG_IN and VBUS decreasing from 7 V to 5
V
5.4
6
6.3
V
VHYS-OVP
Hysteresis on OVLO
Δ of VUVLO+ and VUVLO–
TROVLO
Recovery time from OVLO
TRESP_OVLO
Response time for OVLO
100
mV
Both VOTG_IN and VBUS decreasing from 7 V to
5 V, VOTG_IN = 5 V;
time from VBUS = VOVP– to FLT toggles high
9
ms
Both VOTG_IN and VBUS increasing from 5 V to 7
V, VOTG_IN = 5 V;
time from VBUS = VOVP+ to FLT toggles low
17
µs
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SLVSBR1A – JANUARY 2013 – REVISED FEBRUARY 2013
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ELECTRICAL CHARACTERISTICS FOR DET CIRCUITS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
VBUS_VALID–
Valid VBUS voltage detect
VBUS = 7 V to 0 V
2.7
2.9
3
V
VBUS_VALID+
Valid VBUS voltage detect
VBUS = 0 V to 7 V
5.3
5.4
5.6
V
TDET_DELAY–
VBUS detect propagation
delay–
VBUS 0 V to 4 V, 200 ns ramp; VBUS = VBUS_VALID– MIN to
DET toggles high
4.9
µs
TDET_DELAY+
VBUS detect propagation
delay+
VBUS 6 V to 4 V, 200 ns ramp; VBUS = VBUS_VALID+ MAX to
DET toggles low
1.8
µs
ELECTRICAL CHARACTERISTICS FOR OTG SWITCH
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
RDS_ON
OTG switch resistance
VBUS = 5 V, IOUT = 100 mA, RADJ = 75 kΩ (1)
263
290
mΩ
VDROP
OTG switch voltage drop
VBUS = 5 V, IOUT = 100 mA, RADJ = 75 kΩ
12.6
29
mV
IOTG_OFF_30V Leakage current at 30V
PRODUCT PREVIEW
IOTG_OFF_2V
Leakage current at–2V
IOTG_OFF
Standby Leakage current
Measured at
VOTG_IN
VBUS = 30 V, EN = 5 V, VOTG_IN = 5 V
6
µA
VBUS = 30 V, EN = 5 V, VOTG_IN = 0 V
11
nA
VBUS = -2 V, EN = 5 V, VOTG_IN = 5 V
30
µA
VBUS = 0 V, EN = 0 V, VOTG_IN = 5 V
32
µA
VBUS = 5 V, EN = 0 V, VOTG_IN = 0 V
10
nA
VBUS = 5 V, EN = 5 V, VOTG_IN = 0V
1
nA
VBUS = 5.5 V, EN = 5 V, VOTG_IN = 5 V
6
µA
IBUS_REV
Reverse Leakage current
TON
Turn-ON time
RL = 100 Ω, CL = 1 uF, RADJ = 75 kΩ
16
ms
TOFF_EN
Turn-OFF time
RL = 100 Ω, CL = 1 uF, RADJ = 75 kΩ, toggle EN
80
µs
TOFF_OTG
Turn-OFF time
RL = 100 Ω, CL = 1 uF, RADJ = 75 kΩ, toggle VOTG_IN
0.5
µs
TRISE
Output rise time
RL = 100 Ω, CL = 1 uF, RADJ = 75 kΩ
137
µs
TFALL
Output fall time
RL = 100 Ω, CL = 1 uF, RADJ = 75 kΩ
1.6
µs
(1)
RDS_ON is measured at 25°C
ELECTRICAL CHARACTERISTICS FOR CURRENT LIMIT and SHORT CIRCUIT PROTECTION
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Current−limit threshold
(maximum DC output current
IOUT delivered to load)
IOCP
TBLANK
Blanking time after enable
TDEGL
TDET_SC
TREG
Short circuit regulation time
TOCP
Short circuit over current
protection time
VSHORT
Short circuit threshold
IINRUSH
(1)
6
TEST CONDITIONS
VOTG_IN = 5 V
TYP
MAX
235
255
281
RADJ = 75 kΩ (1)
735
792
830
RADJ = 62 kΩ (1)
885
959
1005
RADJ = 45 kΩ (1)
1128
1200
1363
RL = 1 Ω, CL = 1 uF,
RADJ = 75 kΩ
UNIT
mA
4
ms
Deglitch time while enabled
9.4
ms
Response time to short circuit
10
µs
13
ms
153
ms
Inrush current during a startup
VOTG_IN = 5 V
MIN
RADJ = 226 kΩ (1)
VOTG_IN = 5 V, RL = 100 Ω,
CL = 1 uF, RADJ = 75 kΩ,
apply short to ground
Hiccup pulse width; autoretry time
Hiccup pulse period
4
See Figure 5 under test
configuration
RL = 100 Ω, CL = 22 µF,
RADJ = 75 kΩ
726
V
mA
External resistor tolerance is ±1%
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ELECTRICAL CHARACTERISTICS FOR REVERSE VOLTAGE PROTECTION
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VREV
Reverse-voltage comparator trip point (at VBUS port)
TRRVP
Time from reverse-voltage condition to MOSFET switch off
and FLG = low
TRREV
Re-arming time
MIN
VBUS > VOTG_IN
TYP
MAX
UNIT
50
mV
17.5
ms
25
µs
SUPPLY CURRENT CONSUMPTION
over operating free-air temperature range (unless otherwise noted)
PARAMETER
IVOTG_INON
TEST CONDITIONS
VOTG_IN = 5 V, No load on VBUS,
EN = 5 V
High-level VOTG_IN operating current
consumption
TYP
MAX
UNIT
RADJ = 75 kΩ
162
200
µA
RADJ = 226 kΩ
150
200
µA
TYP
MAX
UNIT
THERMAL SHUTDOWN
PARAMETER
TEST CONDITIONS
TSHDN+
Shutdown temp rising
141
ºC
TSHDN–
Shutdown temp falling
125
ºC
THYST
Thermal-shutdown Hysteresis
PMAX
Maximum power dissipation
TJMAX
Junction Temp at max power dissipation
16
VOTG_IN = 5 V, Rload = 5 Ω, EN = 5 V, RADJ = 75 KΩ
PRODUCT PREVIEW
over operating free-air temperature range (unless otherwise noted)
ºC
0.16
W
150
ºC
APPLICATION DIAGRAM
OTG 5 V
Source
COTG*
System Side Supply
(1.8 V to 3.6 V)
VOTG_IN
ADJ
USB Connector
VBUS
VBUS
TPD4S214
USB Controller
+
Detection
D+
D+
D–
D–
ID
ID
DET
FLT\
EN
GND
CBUS*
Figure 2. USB2.0 Application Diagram Without Using On-chip VBUS Detect
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TPD4S214
SLVSBR1A – JANUARY 2013 – REVISED FEBRUARY 2013
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OTG 5 V
Source
COTG*
System Side Supply
(1.8 V to 3.6 V)
VOTG_IN
ADJ
USB Connector
VBUS
VBUS
TPD4S214
D+
D+
D–
D–
ID
ID
DET
USB Controller
FLT\
EN
GND
CBUS*
PRODUCT PREVIEW
Figure 3. USB 2.0 Application Diagram Using On-chip VBUS Detect
OTG 5 V
Source
COTG*
System Side Supply
(1.8 V to 3.6 V)
VOTG_IN
ADJ
USB Connector
TX+
VBUS
VBUS
TX–
TPD4S214
D–
D+
GND
D–
USB Controller
+
Detection
D+
DET
RX+
GND
ID
FLT\
EN
RX–
CBUS*
*CBUS and COTG have minimum recommended values of 1 µF each
Figure 4. USB 3.0 Application Diagram Without Using On-chip VBUS Detect
8
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TEST CONFIGURATION
TPD4S214
VOTG_IN
VBUS
CLOAD
CIN
EN
RLOAD
ADJ
75 kΩ
Figure 5. Inrush Current Test Configuration.
PRODUCT PREVIEW
Enable is toggled from low to high. See the Application Information section for CIN and CLOAD value
recommendations.
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TYPICAL CHARACTERISTICS
400
1.8
±40ƒC
1.6
250mA
350
25ƒC
1.4
Switch Resistance (m
85ƒC
1.0
0.8
0.6
0.4
250
200
150
100
50
0.2
0.0
0
50
100
150
200
250
300
350
±40
400
RADJ (k )
±20
4.5
0.9
4.0
0.8
3.5
0.7
3.0
0.6
2.5
0.5
2.0
0.4
Voltage (V)
1.0
Current (A)
Voltage (V)
PRODUCT PREVIEW
1.1
5.0
0.3
1.5
1.0
0.2
Votgin
Vbus
Iotgin
0.5
0.0
15
30
45
60
75
90
105
0.1
0.0
±2
0
20
40
60
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
±0.2
4
6
8
10
12
14
16
Time ( s)
80
100
Voltage (V)
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
±0.2
Current (A)
Voltage (V)
C002
C004
Figure 9. 10 Ω Load to Short, 2 µs
Time ( s)
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
±0.5
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
±0.2
Votgin
Vbus
Iotgin
±5
C005
Figure 10. 10 Ω Load to Short, 20 µs
10
2
C003
Votgin
Vbus
Iotgin
0
80
Votgin
Vbus
Iotgin
Figure 8. Inrush, RADJ = 75 kΩ
±20
60
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
±0.5
120
Time ( s)
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
±0.5
40
Figure 7. 3RDSON vs. Temperature
5.5
0
20
Temperature (ƒC)
Figure 6. IOCP vs. RADJ
±15
0
C001
Current (A)
0
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0
5
10
15
Time (ms)
Current (A)
Current (A)
1.2
500mA
300
20
C006
Figure 11. 10 Ω Load to Short, 5 ms
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Votgin
Vbus
Iotgin
100
200
300
400
0
±3
±6
±15
±18
±21
±24
±27
500
Time (ms)
±9
±12
1M
C007
10M
100M
1G
10G
Frequency (Hz)
Figure 12. 10 Ω Load to Short, 100 ms
70
ID
D+
D±
10
50
0
40
±10
Voltage (V)
Voltage (V)
20
ID
D+
D±
60
30
20
±20
±30
10
±40
0
±50
±10
±60
±20
±70
±15 0
15 30 45 60 75 90 105 120 135 150 165 180
Time (ns)
±15 0
15 30 45 60 75 90 105 120 135 150 165 180
Time (ns)
C009
Figure 14. +8 kV Contact, 1 GHz
C010
Figure 15. -8 kV Contact, 1 GHz
2.4
7
VBUS
EN
FLT
2.2
6
2.0
1.8
5
1.6
Voltage (V)
Capacitance (pF)
C008
Figure 13. Data Line Insertion Loss
PRODUCT PREVIEW
0
3
Gain (dB)
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
±0.2
Current (A)
Voltage (V)
TYPICAL CHARACTERISTICS (continued)
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
±0.5
±100
1.4
1.2
1.0
0.8
4
3
2
0.6
0.4
1
0.2
0.0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VBIAS (V)
4.5
5.0
±5
Figure 16. CIO vs. VBIAS, f = 1 MHz
0
5
10
15
20
Time (ms)
C011
25
C012
Figure 17. TPD4S214 Turn On Characteristics
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TPD4S214
SLVSBR1A – JANUARY 2013 – REVISED FEBRUARY 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
6
5
VBUS
VOTG
FLT
5
4
Voltage (V)
Voltage (V)
6
VBUS
EN
FLT
3
4
3
2
2
1
1
0
0
±25
0
25
50
75
100
125
150
175
200
Time ( s)
225
0
10
20
8
60
70
80
C014
9.0
VBUS
8.0
DET
7.0
PRODUCT PREVIEW
Voltage (V)
7
Voltage (V)
50
Figure 19. UVLO
VBUS
VOTG
FLT
9
40
Time (ms)
Figure 18. TPD4S214 Turn Off Characteristics
10
30
C013
6
5
4
6.0
5.0
4.0
3.0
3
2
2.0
1
1.0
0
0.0
0
25
50
75
100
125
150
Time (ms)
175
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Time (ms)
C015
Figure 20. OVLO
4.0
4.5
C016
Figure 21. VBUS Valid Detect Upper
3.5
VBUS
3.0
DET
Voltage (V)
2.5
2.0
1.5
1.0
0.5
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Time (ms)
4.5
C017
Figure 22. VBUS Valid Detect Lower
12
4.0
Figure 23. Eye Diagram with no EVM and no IC, Full USB2.0
Speed at 480 Mbps
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TYPICAL CHARACTERISTICS (continued)
Figure 25. Eye Diagram with TPD4S214EVM and IC, Full
USB2.0 Speed at 480 Mbps
PRODUCT PREVIEW
Figure 24. Eye Diagram with TPD4S214EVM but no IC, Full
USB2.0 Speed at 480 Mbps
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TPD4S214
SLVSBR1A – JANUARY 2013 – REVISED FEBRUARY 2013
www.ti.com
APPLICATION INFORMATION
A USB OTG device’s one and only connector is the AB receptacle, which accepts either an A or B plug. When
an A-plug is inserted, the OTG device is called the A-device and when a B-plug is inserted it is called the Bdevice. A-device is often times referred to as “Targeted Host” and B-device as “USB peripheral”. TPD4S214
supports an OTG device when TPD4S214’s system is acting as an A-device and powering the USB interface.
The TPD4S214 may also be used in non-OTG applications where it resides on the current source side.
Inrush Current Protection
As soon as TPD4S214 is enabled, its logic block detects the presence of any fault conditions highlighted in
Table 1. In the absence of any fault condition, a counter waits for 16 ms, after which a trickle charge of 1 µA
slowly turns on the main switch. During the inrush period, the peak inrush current will be limited to no more than
the current limit set by the external resistor RADJ.
INPUT CAPACITOR (OPTIONAL)
To limit the voltage drop on the input supply caused by transient in-rush currents when the switch turns on into a
discharged load capacitor or short-circuit, a capacitor needs to be placed between VOTG_IN and GND. A 10-μF
ceramic capacitor, CIN, placed close to the pins, is usually sufficient. Higher values of CIN can be used to further
reduce the voltage drop during high-current application. When switching heavy loads, it is recommended to have
an input capacitor about 10 times higher than the output capacitor to avoid excessive voltage drop.
PRODUCT PREVIEW
OUTPUT CAPACITOR (OPTIONAL)
Due to the integrated body diode in the NMOS switch, a CIN greater than CLOAD is highly recommended. A CLOAD
greater than CIN can cause VBUS to exceed VOTG_IN when the system supply is removed. A CIN to CLOAD ratio of
10 to 1 is recommended for minimizing VOTG_IN dip caused by inrush currents during startup.
Current Limit
The TPD4S214 provides current limiting function, which is set by an external resistor connected from the ADJ pin
to ground shown in Figure 26. The current limiting threshold IOCP is set by the external resistor RADJ. Figure 6
shows the minimum, typical, and maximum current limit for a corresponding RADJ value with ±1% tolerance.
ADJ
RADJ
TPD4S214
Figure 26.
R ADJ =
55.358
IOCP
(1)
Where:
RADJ = external resistor used to set the current limit (kΩ)
IOCP = current limit set by the external RADJ resistor (A)
RADJ is placed between the ADJ pin and ground, shown in the figure above, providing a minimum current limit
between 250 mA and 1.2 A.
14
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SLVSBR1A – JANUARY 2013 – REVISED FEBRUARY 2013
VBUS Detection
There are several important protocols defined in [OTG and EH Supplement] that governs communication
between Targeted Hosts (A-device) and USB peripherals (B-device). Communication between host and
peripheral is usually done on the ID pin only. In case when two OTG devices that could both act as either host or
peripheral are connected, measuring voltage level on VBUS will aid in the handshaking process. If an embedded
host instead of a USB device is connected to the OTG device, OTG charging would not be required and the
system’s OTG source should remain off to conserve power. The TPD4S214 VBUS detection block aids power
conservation and is powered from VBUS. See figure 3. The DET pin is an open drain PMOS output with default
state low.
In the event when an A-plug is attached, the system detects ID pin as FALSE, in which case ID pin resistance to
ground is less than 10 Ω. For a B-plug, the system detects ID pin as TRUE and ID pin resistance to ground is
greater than 100 kΩ. For the system to power a USB device through OTG switch once it is connected, voltage on
VBUS should remain below VBUS_VALID MIN within TA_VBUS_ATT of the ID pin becoming FALSE. After this event, the
system confirms that the USB device requires power and enables both TPD4S214 and OTG source. However, if
VBUS_VALID is detected on VBUS within TA_VBUS_ATT of the ID pin becoming FALSE, there is either a system error or
the device connected does not require charging. OTG source remains switched off and the entire sequence
would restart when the system detects another FALSE on the ID pin.
Table 3. VBUS Detection scheme
VOTG_IN (VBUS Detect Power)
VBUS
DET
X
X
Condition
X
VBUS_VALID- < VBUS < VBUS_VALID+
H
VBUS within VBUS_VALID
X
VBUS_VALID- > VBUS or VBUS > VBUS_VALID+
L
VBUS outside of VBUS_VALID
Figure 27 and Figure 28 shows suggested system level timing diagram for detecting VBUS according to [OTG and
EH Supplement]. Figure 3 shows the application diagram. In Figure 27, DET pin remains low after ID pin
becomes FALSE, indicating there is not an active voltage source on VBUS. The USB controller proceeds to turn
on OTG 5V source and the TPD4S214 respectively; this sequence is recommended because TPD4S214 is
powered through the OTG source. After a period of tON, current starts to flow through the OTG switch and VBUS is
ramped to the voltage level of VOTG_IN.
TA_VBUS_ATT
ID Pin
HIGH
TON
LOW
HIGH
VBUS Pin
LOW
HIGH
DET Pin
LOW
HIGH
OTG 5V Source
LOW
HIGH
TPD4S214 EN
LOW
Figure 27. Timing Diagram for Valid USB Device
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15
PRODUCT PREVIEW
EN
TPD4S214
SLVSBR1A – JANUARY 2013 – REVISED FEBRUARY 2013
www.ti.com
In Figure 28, DET pin toggles high after an active voltage is detected on VBUS within TA_VBUS_ATT. This indicates
that the USB device attached is not suitable for OTG charging and both OTV 5V source and TPD4S214 remain
off.
TA_VBUS_ATT
ID Pin
HIGH
LOW
HIGH
VBUS Pin
VBUS_VALID MIN
LOW
TDET_DELAY
HIGH
DET Pin
LOW
HIGH
OTG 5V Source
LOW
HIGH
PRODUCT PREVIEW
TPD4S214 EN LOW
Figure 28. System Level Timing Diagram for invalid USB Device
Related Documents
OTG and EH Supplement] On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification,
July 14th, 2011. www.usb.org
16
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Feb-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
TPD4S214AYFFR
PREVIEW
DSBGA
YFF
12
3000
TBD
Call TI
Call TI
-40 to 85
TPD4S214YFFR
ACTIVE
DSBGA
YFF
12
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPD4S214YFFR
Package Package Pins
Type Drawing
SPQ
DSBGA
3000
YFF
12
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
8.4
Pack Materials-Page 1
1.48
B0
(mm)
K0
(mm)
P1
(mm)
1.78
0.69
4.0
W
Pin1
(mm) Quadrant
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Mar-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPD4S214YFFR
DSBGA
YFF
12
3000
210.0
185.0
35.0
Pack Materials-Page 2
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