AKM AK7742

[AK7742]
= Preliminary =
AK7742
24bit 2ch ADC + 24bit 4ch DAC with Audio DSP
GENERAL DESCRIPTION
The AK7742 is a highly integrated audio digital processor, including two stereo 24bit DAC’s and one
stereo ADC with input selector. The stereo DAC and ADC feature high performance, archiving 106dB and
96dB dynamic range respectively, 8kHz to 96kHz sampling rate are supported. The audio DSP has
1536step/fs parallel processing power, and 74k-bit delay memory allows surround processing, acoustic
effect and parametric equalizers. As the AK7742 is a RAM based DSP, it is programmable for user
requirements. The AK7742 is available in a space saving small 48pin LQFP package.
FEATURES
■ DSP:
■
■
- Word length: 24bit (Data RAM 24bit floating point)
- Instruction cycle: 13.6 ns (1536step/fs fs=48kHz; 9216step/fs fs=8kHz)
- Multiplier 20 x 16 → 36bit (double precision available)
- Divider 20 / 20 → 20bit
- ALU: 40bit arithmetic operation (overflow margin 4bit) 24bit floating point arithmetic and
logic operation
- Program RAM: 1536 x 36bit
- Coefficient RAM: 1536 x 16bit
- Data RAM: 1536 x 24-bit (24bit floating point)
- Delay RAM: 74kbit (3072 x 24bit)
- Sampling frequency: 8kHz ~ 96kHz
- Master / Slave operation
- Serial signal input port (4ch) MSB justified 24bit / LSB justified 24 / 20 / 16bit and I2S
- Serial signal output port (6ch) MSB justified 24bit / LSB justified 24 / 16bit and I2S
ADC: 2ch (stereo)
- 24bit 64 x Over-sampling delta sigma (fs=8kHz~48kHz)
- DR, S/N: 96dB (fs=48kHz, fully differential input)
- S/(N+D): 84dB (fs=48kHz)
- Differential, Single-end Inputs
- Digital HPF (fc=1Hz)
- 3:1 Analog input selector
- Digital Volume (24dB~-103dB, 0.5dB Step, Mute)
DAC: 4ch (two stereo pairs)
- 24bit 128 x Over-sampling advanced multi-bit (fs=8kHz~96kHz)
- DR, S/N: 106dB
- S/(N+D): 92dB
- Differential output
- Digital Volume (24dB~-103dB, 0.5dB Step, Mute)
DSP Through Mode
■
■ I2C BUS interface for micro-controller
■ Power supply: +3.3V ±0.3V, internal regulator for 1.8V
■ Operating temperature range: -20°C~70°C
■ Package: 48pin LQFP (0.5mm pitch)
Rev.0.5b_PB
2008/08
-1-
[AK7742]
■ Block Diagram
LFLT
Hi-z
2 DVDD
3 VSS1
3
Open Drain
3 AVDD
pull down
XTO
2 VSS2
XTI
BICK
LRCK
IRESETN
CKM[2:0]
TESTI
AVDRV
ASEL[1:0]
3
CLKOE
ADC
DVOL
SELDO3
CLKO/SDOUT3
VCOM
REF
CLKGEN & CONT
0
1
SDOUTAD
DIN3
DOUT5
JX0E
0
1
2
3
AIN3L,AIN3R
2
AIN2L,AIN2R
0
4
AIN1LP,AIN1LN
AIN1RP,AIN1RN
DVOL
0
1
2
3
AOUT2LP
AOUT2LN
AOUT2RP
AOUT2RN
SDINDA2
JX0
DOUT4
SDIN1 / JX1
DAC2
DVOL
DAC1
DIN2
JX1E
2
DOUT3
SELDO5[1:0]
SDIN2 / JX0
2
1
AOUT1LP
AOUT1LN
AOUT1RP
AOUT1RN
SDINDA1
SELDO4[1:0]
JX1
DIN1
DOUT1
OUT1E
1
0
SELDO1
SELDO2[1:0]
DOUT2
GPO
3
2
MICIF
SDOUT1
RDY
SO
OUT2EN
SO/RDY/GPO/SDOUT2
1
0
I2CSEL
CAD1
SCL
CAD0
SDA
DS
Figure 1. Block Diagram
Rev.0.5b_PB
2008/08
-2-
[AK7742]
CP0, CP1
DLP0, DLP1
DP0, DP1
OFREG
64W x 13-Bit
DLRAM
3072W x 24-Bit
DRAM
1536W x 24-Bit
CRAM
1536W x 16-Bit
CBUS(16-Bit)
DBUS(24-Bit)
MPX16
Micon I/F
MPX20
X
Control
DEC
Y
Multiply
16 x 20 → 36-Bit
Serial I/F
PRAM
1536w x 36-Bit
PC
Stack : 5level(max)
TMP 8 x 24-Bit
24-Bit
36-Bit
PTMP(LIFO) 6 x 24-Bit
MUL
DBUS
SHIFT
40-Bit
40-Bit
A
B
2 x 24,16-Bit
ALU
DIN3 (ADC)
2 x 24,20,16-Bit DIN2
40-Bit
Overflow Margin: 4-Bit
2 x 24,20,16-Bit DIN1
40-Bit
DR0 ∼ 3
40-Bit
Over Flow Data
Generator
Division
20÷20→20
2 x 24,16-Bit
DOUT5 (DAC2)
2 x 24,16-Bit
DOUT4 (DAC1)
2 x 24,20,16-Bit
DOUT3
2 x 24,20,16-Bit
DOUT2
2 x 24,20,16-Bit
DOUT1
Peak Detector
Figure 2. AK7742 DSP Block
Rev.0.5b_PB
2008/08
-3-
[AK7742]
■ Ordering Guide
-20 ∼ +70°C
48pin LQFP (0.5mm pitch)
Evaluation board for the AK7742
AK7742EQ
AKD7742
AOUT2LN
AOUT2RP
AOUT2RN
AVDD
AVDRV
VSS1
CAD1
CAD0
SCL
SDA
SO/RDY/GPO/SDOUT2
34
33
32
31
30
29
28
27
26
25
AOUT1RP
35
37
AOUT2LP
AOUT1RN
36
■ Pin Layout
IRESET
AIN1RN
AIN1RP
44
17
CKM[0]
45
16
CKM[1]
AIN1LN
46
15
SDIN2/JX0
AIN1LP
AIN3R
47
14
SDIN1/JX1
48
13
SDOUT1
12
18
XTO
(TOP VIEW)
11
43
XTI
AVDD
10
I2CSEL
VSS2
19
9
42
DVDD
DVDD
8
20
VCOM
48pin LQFP
CKM[2]
41
7
VSS1
TESI1
VSS2
6
21
LFLT
40
VSS1
AOUT1LP
5
LRCK
4
22
AVDD
39
3
AOUT1LN
AIN2L
BICK
AIN2R
23
2
38
1
CLKO/SDOUT3
AIN3L
24
pin
Input
Output
I/O
Power
Rev.0.5b_PB
2008/08
-4-
[AK7742]
PIN FUNCTION
No.
1
2
3
4
5
Pin name
AIN3L
AIN2R
AIN2L
AVDD
VSS1
I/O
Function
Classification
I ADC Lch Single-end input 3 pin
Analog input
I ADC Rch Single-end input 2 pin
Analog input
I ADC Lch Single-end input 2 pin
Analog input
Power supply pin for analog section 3.0V ~ 3.6V
Analog power supply
Analog ground 0V
Analog power supply
Filter connection pin for PLL
6 LFLT
O
Analog output
Connect C=12nF to VSS1. “L” output during initial reset.
Test pin (internal pull-down resistor)
7 TESTI
I
Test
Connect to VSS2
8 CKM[2]
I Clock mode select pin 2
Mode select
9 DVDD
Power supply pin for digital section 3.0V ~ 3.6V
Digital power supply
10 VSS2
Digital ground 0V
Digital power supply
Master clock input pin
11 XTI
I
When using a crystal oscillator, connect it between this pin and XTO.
Clock
When using external main clock, input to this pin with CMOS level.
Crystal oscillator output pin
When using a crystal oscillator, connect it between this pin and XTI.
12 XTO
O
Clock
When not using crystal oscillator, leave open. Output during initial reset is
not determined.
O DSP serial data output pin
13 SDOUT1
Data interface
“L” output during initial reset
14 SDIN1/JX1
I Serial data input pin 1 / JX1
Data interface
15 SDIN2/JX0
I Serial data input pin 2 / JX0
Data interface
16 CKM[1]
I Clock mode select pin 1
Mode select
17 CKM[0]
I Clock mode select pin 0
Mode select
18 IRESETN
I Reset pin (for initialization)
Reset
I2CBUS select pin
19 I2CSEL
I
Microcomputer I/F
Connect to DVDD
20 DVDD
Power supply pin for digital section 3.0V ~ 3.6V
Digital power supply
21 VSS2
Digital ground 0V
Digital power supply
I/O LR channel select clock pin
22 LRCK
Data interface
“L” output during initial reset with master mode.
I/O Serial bit clock pin
23 BICK
Data interface
“L” output during initial reset with master mode.
O Clock output / DSP serial data output pin
24 CLKO/SDOUT3
Clock
“L” output during initial reset
Serial data output pin / Data write ready output pin / General purpose output
SO/RDY/GPO/
25
O / DSP serial data output pin
Microcomputer I/F
SDOUT2
“L” output during initial reset
26 SDA
I/O SDA I2C bus interface
Microcomputer I/F
27 SCL
I SCL I2C bus interface
Microcomputer I/F
28 CAD0
I I2C bus address pin 0
Microcomputer I/F
29 CAD1
I I2C bus address pin 1
Microcomputer I/F
30 VSS1
Analog ground 0V
Analog power supply
Rev.0.5b_PB
2008/08
-5-
[AK7742]
31 AVDRV
O
32 AVDD
33 AOUT2RN
34 AOUT2RP
35 AOUT2LN
36 AOUT2LP
37 AOUT1RN
38 AOUT1RP
39 AOUT1LN
40 AOUT1LP
O
O
O
O
O
O
O
O
41 VSS1
42 VCOM
O
43
44
45
46
47
48
I
I
I
I
I
AVDD
AIN1RN
AIN1RP
AIN1LN
AIN1LP
AIN3R
AVDRV Pin
Connect 1μF to VSS1. Never to use for external circuit. “L” output during Analog power supply
initial reset
Power supply pin for analog section 3.0V ~ 3.6V
Analog power supply
DAC2 Rch differential inverted analog output pin
Analog output
“Hi-Z” output during initial reset
DAC2 Rch differential non-inverted analog output pin
Analog output
“Hi-Z” output during initial reset
DAC2 Lch differential inverted analog output pin
Analog output
“Hi-Z” output during initial reset
DAC2 Lch differential non-inverted analog output pin
Analog output
“Hi-Z” output during initial reset
DAC1 Rch differential inverted analog output pin
Analog output
“Hi-Z” output during initial reset
DAC1 Rch differential non-inverted analog output pin
Analog output
“Hi-Z” output during initial reset
DAC1 Lch differential inverted analog output pin
Analog output
“Hi-Z” output during initial reset
DAC1 Lch differential non-inverted analog output pin
Analog output
“Hi-Z” output during initial reset
Analog ground 0V
Analog power supply
Analog common voltage
Connect 0.1μF and 2.2μF in parallel to VSS1. Never to use for external Analog output
circuit. “L” output during initial reset
Power supply pin for analog section 3.0V ~ 3.6V
Analog power supply
ADC Rch differential inverted analog input pin
Analog input
ADC Rch differential non-inverted analog input pin
Analog input
ADC Lch differential inverted analog input pin
Analog input
ADC Lch differential non-inverted analog input pin
Analog input
ADC Rch Single-end input 3 pin
Analog input
Note:
Digital input pins are never to be left open.
If analog input pins (AIN1LP, AIN1LN, AIN1RP, AIN1RN, AIN2L, AIN2R, AIN3L, AIN3R) are not used, leave
them open.
Rev.0.5b_PB
2008/08
-6-
[AK7742]
ABSOLUTE MAXMUM RATING
(VSS1=VSS2=0V: Note 1)
Item
Symbol
min
max
Power supply voltage (AVDD= DVDD)
Analog
AVDD
-0.3
4.3
Digital
DVDD
-0.3
4.3
Input current (except for power supply pin)
IIN
±10
Analog input voltage (Note 2)
AIN1LP, AINL1N, AIN1RP, AINR1N,
VINA
-0.3
(AVDD+0.3) or 4.3
AIN2L, AIN2R, AIN3L, AIN3R
Digital input voltage (Note 3)
VIND
-0.3
(DVDD+0.3) or 4.3
Operating ambient temperature
Ta
-20
70
Storage temperature
Tstg
-65
150
Note 1. All indicated voltages are with respect to ground. VSS1 and VSS2 must be the same voltage.
Note 2. The maximum value of analog input voltage is smaller value between (AVDD+0.3)V and 4.3V.
Note 3. The maximum value of digital input voltage is smaller value between (DVDD+ 0.3)V and 4.3V.
Unit
V
V
mA
V
V
ºC
ºC
WARNING: Operating at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these critical conditions.
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=0V: Note 1)
Item
Power supply voltage
Analog
Digital
Symbol
min
typ
max
Unit
AVDD
DVDD
3.0
3.0
3.3
3.3
3.6
3.6
V
V
WARNING: AKEMD assumes no responsibility for the usage beyond the conditions in the datasheet.
Note) Do not turn off the power of the AK7742 during the power supplies of surrounding devices are turned on. VDD
must not exceed the pull-up of SDA and SCL of I2C BUS. (The diode exists for DVDD in the SDA and SCL pins.)
Rev.0.5b_PB
2008/08
-7-
[AK7742]
ANALOG CHARACTERISTICS
■ ADC Characteristics
(Ta=25ºC; AVDD=DVDD=3.3V; BICK=64fs; signal frequency 1kHz; Measurement bandwidth=20Hz~20kHz,
fs=48kHz, ADC differential input, CKM mode 0 (CKM[2:0]=000), unless otherwise specified)
Parameter
min
typ
max
Unit
Resolution
24
Bits
Stereo
ADC
Dynamic characteristics
S/(N+D)
(-1dBFS)
(Note 4)
TDB
84
dB
Dynamic range (A-weighted)
(Note 4)
TDB
96
dB
S/N
(A-weighted)
(Note 4)
TDB
96
dB
Inter-channel isolation (f=1kHz) (Note 5)
90
105
dB
DC accuracy
Channel gain mismatch
0.1
0.3
dB
Analog input
Input voltage (differential input) (Note 6)
±1.85
±2.00
±2.15
Vp-p
Input voltage (single-end input)
(Note 7)
1.85
2.00
2.15
Vp-p
41
62
kΩ
Input impedance
(Note 8)
Note 4. This value is not guaranteed for single-ended inputs.
Note 5. Indicates isolation between L and R when -1dBFS signal is applied.
Note 6. Target input pins are AIN1LP, AIN1LN, AIN1RP, AIN1RN.
Note 7. Target input pins are AIN2L, AIN2R, AIN3L, AIN3R.
Note 8. Target input pins are AIN1LP, AIN1LN, AIN1RP, AIN1RN, AIN2L, AIN2R, AIN3L, AIN3R.
■ DAC Characteristics
(Ta=25ºC; AVDD=DVDD=3.3V; BICK=64fs; signal frequency 1kHz; Measurement bandwidth=20Hz~20kHz,
fs=48kHz, ADC differential input, CKM mode 0 (CKM[2:0]=000), unless otherwise specified)
Parameter
min
typ
max
Unit
Resolution
24
Bits
Stereo
DAC
Dynamic characteristics
S/(N+D)
(0dBFS)
TBD
92
dB
Dynamic range (A-weighted)
TBD
106
dB
S/N
(A-weighted)
TBD
106
dB
Inter-channel isolation (f=1kHz)(Note 9)
90
105
dB
DC accuracy
Channel gain mismatch
0.2
0.5
dB
Analog output
Output voltage (Note 10)
3.36
3.66
3.96
Vp-p
Load resistance
5
kΩ
Load capacitance
30
pF
Note 9. Indicates isolation between each DAC’s of Lch and Rch when -1dBFS signal is applied.
Note 10. Full scale output voltage. The output voltage scales with AVDD.
Rev.0.5b_PB
2008/08
-8-
[AK7742]
DC CHARACTERISTICS
(Ta=-20ºC ~70ºC; AVDD=DVDD=3.0~3.6V)
Parameter
Symbol
min
High level input voltage
(Note 11)
VIH
80%DVDD
Low level input voltage
(Note 11)
VIL
SCL, SDA High level input voltage
VIH
70%DVDD
SCL, SDA Low level input voltage
VIL
VOH
DVDD-0.5
High level output voltage Iout=-100μA
VOL
Low level output voltage Iout=100μA (Note 12)
SDA Low level output voltage Iout=3mA
VOL
Input leak current
(Note 13)
Iin
Input leak current (pull-down)
(Note 14)
Iid
Input leak current XTI pin
Iix
typ
max
20%DVDD
30%DVDD
0.5
0.4
±10
22
26
Unit
V
V
V
V
V
V
V
μA
μA
μA
Note 11. Except for the SCL, SDA pin.
Note 12. Except for the SDA pin.
Note 13. Except for the TESTI pin, XTI pin.
Note 14. The TESTI pin has an internal pull-down device, nominally 150kΩ.
POWER CONSUMPTION
(Ta=25ºC; AVDD=DVDD=3.0~3.6V(typ=3.3V, max=3.6V))
Parameter
min
typ
max
Unit
Power supply current (Note 15)
Normal Operation
75
TBD
mA
AVDD+DVDD
Reset (IRESETN= “L” reference data)
2
mA
AVDD+DVDD (Note 16)
Note 15. Depends on the system frequency and contents of DSP program.
Note 16. This is a reference value when using a crystal oscillator. Since most of the supply current at the initial reset state
is in the oscillator section, the value may vary according to the crystal type and the external circuit. This value is
just reference.
Rev.0.5b_PB
2008/08
-9-
[AK7742]
DIGITAL FILTER CHARACTERISTICS
■ ADC
(Ta=-20ºC ~70ºC, AVDD=DVDD=3.0~3.6V, fs=48kHz; Note 17)
Parameter
Symbol
min
typ
max
Unit
Pass band (±0.005dB)
(Note 18)
PB
0
21.5
kHz
(-0.02dB)
21.768
kHz
(-6.0dB)
24.00
kHz
Stop band
SB
26.5
kHz
Pass band ripple
(Note 18)
PR
±0.005
dB
Stop band attenuation (Note 19, Note 20)
SA
80
dB
Group delay distortion
∆GD
0
μs
Group delay (Ts=1/fs)
GD
30
Ts
Digital filter + Analog filter characteristics
Amplitude characteristic 20Hz~20.0kHz
±0.01
dB
Note 17. Each parameter is related to the sampling frequency (fs). HPF response is not included.
Note 18. Pass band is from DC to 21.5kHz when fs=48kHz.
Note 19. Stop band is from 26.5kHz to 3.0455MHz when fs=48kHz.
Note 20. When fs=48kHz, the analog modulator samples the analog input at 3.072MHz. Therefore the input signal is not
attenuated by the digital filter in multiple bands (n x 3.072MHz ±21.99kHz; n=0, 1, 2, 3 …) of the sampling
frequency.
■ DAC
(Ta=-20ºC ~70ºC, AVDD=DVDD=3.0~3.6V, fs=48kHz; Note 17)
Parameter
Symbol
min
typ
max
Unit
Digital filter
Pass band ±0.07dB
(Note 21)
PB
0
21.7
kHz
(-6.0dB)
24.0
kHz
Stop band
(Note 21)
SB
26.2
kHz
Pass band ripple
PR
±0.01
dB
Stop band attenuation
SA
64
dB
Group delay
(Ts=1/fs) (Note 22)
GD
24
Ts
Digital filter + Analog filter
Amplitude characteristic 0~20.0kHz
±0.5
dB
Note 21. Pass band and Stop band parameter is related to sampling frequency(fs). PB=0.4535fs (at-0.05dB),
SB=0.5465fs.
Note 22.The digital filter’s delay is calculated as the time from setting 24-bit data into the input register until an analog
signal is output.
Rev.0.5b_PB
2008/08
- 10 -
[AK7742]
SWITCHING CHARACTERISTICS
■ System Clock
(Ta=-20ºC~70ºC; AVDD=DVDD=3.0~3.6V)
Parameter
Symbol
XTI
a)with a crystal oscillator
Frequency(256fs)
fs=44.1KHz
fXTI
fs=48KHz
CKM[2:0]= 000
CKM[2:0]= 001
fXTI
b)with an external clock
Duty cycle
Frequency(256fs)
CKM[2:0]= 000, 010
Frequency (384fs)
CKM[2:0]= 001
fs=44.1KHz
fs=48KHz
fs=44.1KHz
fs=48KHz
LRCK frequency (Note 23)
min
typ
max
Unit
-
11.2896
12.288
16.9344
18.432
-
MHz
-
MHz
-
Duty
fXTI
40
11.0
50
11.2896
12.288
60
12.4
%
MHz
fXTI
16.5
16.9344
18.432
18.6
MHz
Fs
7.35
48
96
kHz
BICK frequency
32
64
fs
a) CKM[2:0]= 001, 010
High level width
tBCLKH
64
ns
Low level width
tBCLKL
64
ns
Frequency
0.46
3.072
6.144
MHz
fBCLK
64
fs
b) CKM[2:0]= 011 (Note 25)
Duty cycle
Duty
40
50
60
%
Frequency
fBCLK
2.75
3.072
3.1
MHz
32
fs
c) CKM[2:0]= 100 (Note 26)
Duty cycle
Duty
40
50
60
%
Frequency
fBCLK
230
256
258
kHz
64
fs
d) CKM[2:0]= 101 (Note 27)
Duty cycle
Duty
40
50
60
%
Frequency
fBCLK
460
512
516
kHz
Note 23. LRCK frequency and sampling rate (fs) should be the same.
Note 24. The BICK must be divided 32, 48 or 64 clocks correctly. (BICK can be selected from 32fs, 48fs or 64fs)
Note 25. When BICK is resource of internal MCLK. The BICK must be divided 64 clocks correctly. 64fs fixed.
Note 26. When BICK is resource of internal MCLK. The BICK must be divided 32 clocks correctly. 32fs fixed.
Note 27. When BICK is resource of internal MCLK. The BICK must be divided 64 clocks correctly. 64fs fixed.
Rev.0.5b_PB
2008/08
- 11 -
[AK7742]
■ Reset
(Ta=-20ºC ~70ºC; AVDD=DVDD=3.0~3.6V)
Parameter
Symbol
min
typ
max
Unit
IRESET
(Note 28)
tRST
600
ns
Note 28. It is necessity that the power is supplied and master clock is input when the IRESET pin goes to “H”.
■ Audio Interface
1) SDIN1, SDIN2, SDOUT1, SDOUT2, SDOUT3
(Ta=-20ºC ~70ºC; AVDD=DVDD=3.0~3.6V, CL=20pF)
Parameter
Slave mode
BICK frequency
BICK low level width
BICK high level width
Delay time from BICK “↑” to LRCK (Note 29)
Delay time from LRCK to BICK “↑” (Note 29)
Serial data input latch setup time
Serial data input latch hold time
Delay time from LRCK to serial data output
Delay time from BICK “↓” to serial data output (Note 30)
Master mode
BICK frequency
BICK duty cycle
Delay time from BICK “↑” to LRCK
Delay time from LRCK to BICK “↑”
Serial data input latch setup time
Serial data input latch hold time
Delay time from BICK “↓” to serial data output (Note 30)
Symbol
min
typ
fBCLK
tBCLKL
tBCLKH
tBLRD
tLRBD
tBSIDS
tBSIDH
tLRD
tBSOD
32
150
150
40
40
40
40
-10
-10
64
fBCLK
tBLRD
tLRBD
tBSIDS
tBSIDH
tBSOD
max
Unit
40
40
fs
ns
ns
ns
ns
ns
ns
ns
ns
40
fs
%
ns
ns
ns
ns
ns
64
50
40
40
40
40
-30
Note 29. BICK rising edge must not occur at the same time as LRCK edge.
Note 30. The serial data output is synchronized to BICK falling edge, and held until next BICK falling (spec -10ns) in
Slave mode. In case of the LRCK edge comes before BICK edge, data will be held until LRCK edge (spec
-10ns). In Master mode, serial data is held until 30ns before falling edge of BICK. Therefore, please use BICK
rising edge in both slave and master modes for a safety latch.
.
Rev.0.5b_PB
2008/08
- 12 -
[AK7742]
■ I2CBUS Interface
(Ta=-20ºC~70ºC; AVDD=DVDD=3.0~3.6V)
Parameter
I2C Timing
SCL clock frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first Clock
pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed
by Input Filter
Capacitive load on bus
Symbol
min
fSCL
tBUF
tHD:STA
1.3
0.6
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
Cb
1.3
0.6
0.6
0
0.1
typ
max
Unit
400
KHz
μs
μs
50
μs
μs
μs
μs
μs
μs
μs
μs
ns
400
pF
0.9
0.3
0.3
0.6
0
Note 31. I2C is a registered trademark of Philips Semiconductors.
Rev.0.5b_PB
2008/08
- 13 -
[AK7742]
PACKAGE
48pin LQFP (Unit: mm)
1.70Max
9.0 ± 0.2
0.13 ± 0.13
7.0
1.4± 0.05
25
24
48
13
7.0
37
1
9.0 ± 0.2
36
12
0.09 ∼ 0.20
0.5
0.22 ± 0.08
0.10 M
0° ∼ 10°
0.10
0.3 ∼ 0.75
■ Materials and Lead Specification
Package:
Lead frame:
Lead-finish:
Epoxy
Copper
Soldering (Pb free) plate
Rev.0.5b_PB
2008/08
- 14 -
[AK7742]
MARKING
AKM
AK7742EQ
XXXXXXX
1
1)
2)
3)
4)
Pin #1 indication
Date Code: XXXXXXX(7digits)
Marking Code: AK7742EQ
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IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any
and all claims arising from the use of said product in the absence of such notification.
Rev.0.5b_PB
2008/08
- 15 -
[AK7742]
Thank you for your access to AKEMD product information.
More detail product information is available, please contact our
sales office or authorized distributors.
Rev.0.5b_PB
2008/08
- 16 -