[AK4372] AK4372 DAC with built-in PLL & HP-AMP GENERAL DESCRIPTION The AK4372 is a 24-bit DAC with an integrated PLL and headphone amplifier. The PLL input frequency is synchronized to typical mobile phone clock frequencies. The AK4372 features an analog mixing circuit that allows easy interfacing in mobile phone and portable communication designs. The integrated headphone amplifier features “pop-noise free” power-on/off, a mute control, and it delivers 40mW of power into 16Ω. The AK4372 is packaged in a 24-pin CSP (2.5mm×2.5mm) package, ideal for portable applications. FEATURE Multi-bit ΔΣ DAC Sampling Rate - 8kHz ~ 48kHz On chip perfect filtering 8 times FIR interpolator - Passband: 20kHz - Passband Ripple: ±0.02dB - Stopband Attenuation: 54dB Digital De-emphasis Filter: 32kHz, 44.1kHz and 48kHz System Clock - PLL Mode (MCKI): 27MHz, 26MHz, 19.8MHz, 19.68MHz, 19.2MHz, 15.36MHz, 14.4MHz, 13MHz, 12MHz and 11.2896MHz - PLL Mode (BICK or LRCK): 64fs, 32fs or fs - EXT Mode: 256fs/384fs/512fs/768fs/1024fs - Input Level: AC Couple Input Available Audio I/F Format: MSB First, 2’s Complement - I2S, 24bit MSB justified, 24bit/20bit/16bit LSB justified - Master/Slave Mode Digital Mixing: LR, LL, RR, (L+R)/2 Bass Boost Function Digital ATT Analog Mixing Circuit: 3 Inputs (Single-ended or Full-differential) Stereo Lineout - S/N: [email protected] - Output Volume: +6 to –24dB (or 0 to –30dB), 2dB step Headphone Amplifier - Output Power: 40mW x 2ch @16Ω, 3.3V - S/N: [email protected] - Pop Noise Free at Power-ON/OFF and Mute - Output Volume: 0 ~ –63dB & +12/+6/0 dB Gain 1.5dB step (0 ~ –30dB), 3dB step (–30 ~ –63dB) μP Interface: 3-wire/I2C Power Supply: 1.6V ∼ 3.6V Power Supply Current: 3.8mA @1.8V (6.8mW, DAC+HP, No output) AK4372ECB: Ta= −30 ∼ 85°C AK4372VCB: Ta= −40 ∼ 85°C Small Package: 24pin CSP (2.5mm x 2.5mm, 0.4mm pitch) Register Compatible with AK4368 MS0684-E-02 2008/12 -1- [AK4372] ■ Block Diagram MCKO BICK LRCK SDATA Audio Interface MCKI LIN/IN− MIN AVDD VSS1 PLL VCOM VCOM DVDD VSS2 VCOC DAC Digital Volume Deemphasis Bass Boost Digital Filter LOUT (Lch) ROUT DAC (Rch) PDN I2C HDP Amp MUTE HPL HDP Amp MUTE HPR CAD0/CSN SCL/CCLK Serial I/F SDA/CDTI RIN/IN+ MUTET Figure 1. Block Diagram MS0684-E-02 2008/12 -2- [AK4372] ■ Ordering Guide AK4372ECB AK4372VCB AKD4372 −30 ∼ +85°C 24pin CSP (0.4mm pitch) −40 ∼ +85°C 24pin CSP (0.4mm pitch) Evaluation board for AK4372 Black Type Black Type ■ Pin Layout 5 4 3 Top View 2 1 A B C D E 5 VSS2 CCLK CSN PDN MUTET 4 VCOC MCKO CDTI LOUT ROUT 3 MCKI LRCK DVDD I2C VCOM BICK LIN HPR AVDD SDATA RIN MIN HPL VSS1 A B C D E 2 1 Top View MS0684-E-02 2008/12 -3- [AK4372] ■ Comparison with AK4370/71 1 Function Function PLL Internal VREF Hands-free Amp AK4370 2-Stereo Single-ended Input or Full-differential Input No No No AK4371 3-Stereo Single-ended Input or Full-differential Input Yes Yes Yes Ta −30 ∼ +85°C −30 ∼ +85°C Package 24 pin QFN (4mm x 4mm, 0.5mm pitch) 32 pin QFN (4mm x 4mm, 0.4mm pitch) Analog Mixing AK4372 1-Stereo + 1-Mono Single-ended Input or Full-differential Input Yes No No AK4372ECB: −30 ∼ +85°C AK4372VCB: −40 ∼ +85°C 24 pin CSP (2.5mm x 2.5mm, 0.4mm pitch) 2 Register (difference from AK4370/71) Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H Register Name Power Management 0 PLL Control Clock Control Mode Control 0 Mode Control 1 DAC Lch ATT DAC Rch ATT Headphone Out Select 0 Lineout Select 0 Lineout ATT Reserved Reserved Reserved Headphone Out Select 1 Headphone ATT Lineout Select 1 Mono Mixing Differential Select Reserved Reserved D7 PMVREF FS3 PLL4 0 ATS ATTL7 ATTR7 HPG1 0 0 0 0 0 RIN3HR 0 RIN3R 0 0 RIN3M 0 D6 D5 D4 D3 D2 PMPLL PMLO MUTEN PMHPR PMHPL FS2 FS1 FS0 PLL3 PLL2 MCKAC 0 M/S BF PS0 MONO1 MONO0 BCKP LRP DIF2 DATTC LMUTE SMUTE BST1 BST0 ATTL6 ATTL5 ATTL4 ATTL3 ATTL2 ATTR6 ATTR5 ATTR4 ATTR3 ATTR2 HPG0 MINHR MINHL RINHR LINHL LOG MINR MINL RINR LINL 0 0 0 ATTS3 ATTS2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RIN3HL LIN3HR LIN3HL RIN2HR RIN2HL HPZ HMUTE ATTH4 ATTH3 ATTH2 RIN3L LIN3R LIN3L RIN2R RIN2L 0 L3M L3HM L2M L2HM 0 0 0 0 LDIFM LIN3M RIN2M LIN2M RIN1M LIN1M MMUTE PMMO MOG ATTM3 ATTM2 These bits are changed from the AK4370/71. These bits are deleted in the AK4372. These bits are deleted in the AK4370. MS0684-E-02 D1 PMDAC PLL1 PS1 DIF1 DEM1 ATTL1 ATTR1 DARHR DARR ATTS1 0 0 0 LINHR ATTH1 LINR LM LDIFH DARM ATTM1 D0 PMVCM PLL0 MCKO DIF0 DEM0 ATTL0 ATTR0 DALHL DALL ATTS0 0 0 0 RINHL ATTH0 RINL LHM LDIF DALM ATTM0 2008/12 -4- [AK4372] PIN/FUNCTION No. A1 B2 B3 A3 C3 Pin Name SDATA BICK LRCK MCKI DVDD I/O I I/O I/O I - Function Audio Serial Data Input Pin Audio Serial Data Clock Pin Input / Output Channel Clock Pin External Master Clock Input Pin Digital Power Supply Pin, 1.6 ∼ 3.6V Output for Loop Filter of PLL Circuit A4 VCOC O This pin must be connected to VSS2 with one resistor and one capacitor in series. A5 VSS2 Ground 2 Pin. Connected to VSS1. B4 MCKO O Master Clock Output Pin SDA I/O Control Data Input/Output Pin (I2C mode : I2C pin = “H”) C4 CDTI I Control Data Input Pin (3-wire serial mode : I2C pin = “L”) SCL I Control Data Clock Pin (I2C mode : I2C pin = “H”) B5 CCLK I Control Data Clock Pin (3-wire serial mode : I2C pin = “L”) CAD0 I Chip Address 0 Select Pin (I2C mode : I2C pin = “H”) C5 CSN I Chip Select Pin (3-wire serial mode : I2C pin = “L”) Power-down & Reset D5 PDN I When “L”, the AK4372 is in power-down mode and is held in reset. The AK4372 must be reset once upon power-up. Control Mode Select Pin D3 I2C I “H”: I2C Bus, “L”: 3-wire Serial Mute Time Constant Control pin E5 MUTET O Connected to the VSS1 pin with a capacitor for mute time constant. D4 LOUT O Lch Stereo Line Output Pin E4 ROUT O Rch Stereo Line Output Pin Common Voltage Output Pin E3 VCOM O Normally connected to the VSS1 pin with a 2.2μF electrolytic capacitor. E2 AVDD Analog & PLL Power Supply Pin, 1.6 ∼ 3.6V E1 VSS1 Ground 1 Pin D2 HPR O Rch Headphone Amp Output D1 HPL O Lch Headphone Amp Output C1 MIN I Mono Analog Input Pin I Rch Analog Input Pin (LDIF bit =“0” : Single-ended Input) RIN B1 IN+ I Positive Line Input Pin (LDIF bit =“1” : Full-differential Input) LIN I Rch Analog Input Pin (LDIF bit =“0” : Single-ended Input) C2 I Negative Line Input Pin (LDIF bit =“1” : Full-differential Input ) IN− Note 1. All digital input pins (I2C, SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN) must not be left floating. The MCKI pin can be left floating only when the PDN pin = “L”. MS0684-E-02 2008/12 -5- [AK4372] ■ Handling of Unused Pin The unused I/O pins must be processed appropriately as below. Classification Analog Digital Pin Name LOUT, ROUT, MUTET, HPR, HPL, MIN, RIN/IN+, LIN/IN− MCKI MCKO Setting These pins must be open. This pin must be connected to VSS2. This pin must be open. ABSOLUTE MAXIMUM RATING (VSS1 = VSS2 =0V; Note 2, Note 3) Parameter Symbol min max Units Power Supplies Analog AVDD 4.6 V −0.3 Digital DVDD 4.6 V −0.3 Input Current (any pins except for supplies) IIN mA ±10 Analog Input Voltage (Note 4) VINA (AVDD+0.3) or 4.6 V −0.3 Digital Input Voltage (Note 5) VIND (DVDD+0.3) or 4.6 V −0.3 AK4372ECB Ta 85 −30 °C Ambient Temperature AK4372VCB Ta 85 −40 °C Storage Temperature Tstg 150 −65 °C Note 2. All voltages with respect to ground. Note 3. VSS1 and VSS2 must be connected to the same analog ground plane. Note 4. LIN/IN−, RIN/IN+ and MIN pins. Max is smaller value between (AVDD+0.3)V and 4.6V. Note 5. SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN and I2C pins. Max is smaller value between (DVDD+0.3)V and 4.6V. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMEND OPERATING CONDITIONS (VSS1 = VSS2 =0V; Note 2) Parameter Symbol min typ max Units Power Supplies Analog AVDD 1.6 2.4 3.6 V (Note 6) Digital (Note 7) DVDD 1.6 2.4 (AVDD+0.2) or 3.6 V Note 1. All voltages with respect to ground. Note 6. When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or more. When the AK4372 is powered-down, DVDD should be powered-down at the same time or later than AVDD. Note 7. Max is smaller value between (AVDD+0.2)V and 3.6V. * AKEMD assumes no responsibility for usage beyond the conditions in this datasheet. MS0684-E-02 2008/12 -6- [AK4372] ANALOG CHARACTERISTICS (Ta=25°C; AVDD=DVDD=2.4V, VSS1=VSS2=0V; fs=44.1kHz; EXT mode; BOOST OFF; Slave Mode; Signal Frequency =1kHz; Measurement band width=20Hz ∼ 20kHz; Headphone-Amp: Load impedance is a serial connection with RL =16Ω and CL=220μF. (Refer to Figure 50; unless otherwise specified) Parameter min typ max Units 24 bit DAC Resolution Headphone-Amp: (HPL/HPR pins) (Note 8) Analog Output Characteristics THD+N dB −3dBFS Output, 2.4V, Po=10mW@16Ω −50 −40 dB 0dBFS Output, 3.3V, Po=40mW@16Ω −20 82 90 dB D-Range −60dBFS Output, A-weighted, 2.4V 92 dB −60dBFS Output, A-weighted, 3.3V S/N A-weighted, 2.4V 82 90 dB A-weighted, 3.3V 92 dB Interchannel Isolation 60 80 dB DC Accuracy Interchannel Gain Mismatch 0.3 0.8 dB Gain Drift 200 ppm/°C Load Resistance (Note 9) 16 Ω Load Capacitance 300 pF 1.04 1.16 1.28 Vpp Output Voltage −3dBFS Output (Note 10) 0dBFS Output, 3.3V, 0.8 Vrms Po=40mW@16Ω Output Volume: (HPL/HPR pins) Step Size 0.1 1.5 2.9 dB 0 ∼ –30dB (HPG1-0 bits = “00”) 0.1 3 5.9 dB –30 ∼ –63dB Gain Control Range Max (ATT4-0 bits = 00H) 0 dB (HPG1-0 bits = “00”) Min (ATT4-0 bits = 1FH) dB −63 Stereo Line Output: (LOUT/ROUT pins, RL=10kΩ) (Note 11) Analog Output Characteristics: THD+N (0dBFS Output) dB −60 −50 S/N A-weighted, 2.4V 80 87 dB A-weighted, 3.3V 90 dB DC Accuracy Gain Drift 200 ppm/°C Load Resistance (Note 9) 10 kΩ Load Capacitance 25 pF Output Voltage (0dBFS Output) (Note 12) 1.32 1.47 1.61 Vpp Output Volume: (LOUT/ROUT pins) Step Size 1 2 3 dB Gain Control Range Max (ATTS3-0 bits = FH) 0 dB (LOG1-0 bit = “0”) Min (ATTS3-0 bits = 0H) dB −30 Note 8. DALHL=DARHR bits = “1”, LINHL=RINHL=MINHL=LINHR=RINHR=MINHR bits = “0”. Note 9. AC load. Note 10. Output voltage is proportional to AVDD voltage. Vout = 0.48 x AVDD(typ)@−3dBFS. Note 11. DALL=DARR bits = “1”, LINL=RINL=MINL=LINR=RINR=MINR bits = “0” Note 12. Output voltage is proportional to AVDD voltage. Vout = 0.61 x AVDD(typ)@0dBFS. MS0684-E-02 2008/12 -7- [AK4372] Parameter LINEIN: (LIN/RIN/MIN pins) Analog Input Characteristics Input Resistance (See Figure 25, Figure 26, Figure 27) LIN pin LINHL=LINHR=LINL=LINR= bits = “1” LINHL bit = “1”, LINHR=LINL=LINR bits = “0” LINHR bit = “1”, LINHL=LINL=LINR bits = “0” LINL bit = “1”, LINHL=LINHR=LINR bits = “0” LINR bit = “1”, LINHL=LINHR=LINL bits = “0” RIN pin RINHL=RINHR=RINL=RINR bits = “1” RINHL bit = “1”, RINHR=RINL=RINR bits = “0” RINHR bit = “1”, RINHL=RINL=RINR bits = “0” RINL bit = “1”, RINHL=RINHR=RINR bits = “0” RINR bit = “1”, RINHL=RINHR=RINL bits = “0” MIN pin MINHL=MINHR=MINL=MINR bits = “1” MINHL bit = “1”, MINHR=MINL=MINR bits = “0” MINHR bit = “1”, MINHL=MINL=MINR bits = “0” MINL bit = “1”, MINHL=MINHR=MINR bits = “0” MINR bit = “1”, MINHL=MINHR=MINL bits = “0” Gain LIN/RIN/MIN Æ LOUT/ROUT LIN/RIN/MIN Æ HPL/HPR Power Supplies Power Supply Current Normal Operation (PDN pin = “H”) (Note 13) AVDD+DVDD Power-Down Mode (PDN pin = “L”) (Note 14) min typ max Units 14 - 25 100 100 100 100 - kΩ kΩ kΩ kΩ kΩ 14 - 25 100 100 100 100 - kΩ kΩ kΩ kΩ kΩ 14 - 25 100 100 100 100 - kΩ kΩ kΩ kΩ kΩ −1 −0.05 0 +0.95 +1 +1.95 dB dB - 5.0 1 8.0 100 mA μA Note 13. PMDAC=PMHPL=PMHPR=PMLO bits = “1”, MUTEN bit = “1”, MCKO bit = “0”, HP-Amp no output. PMDAC=PMHPL=PMHPR= “1”, PMLO bit= “0”, AVDD+DVDD=4.0mA (typ) @2.4V, 3.8mA (typ) @1.8V. Note 14. All digital input pins are fixed to VSS2. MS0684-E-02 2008/12 -8- [AK4372] FILTER CHARACTERISTICS (Ta=25°C; AVDD = DVDD=1.6 ∼ 3.6V; fs=44.1kHz; De-emphasis = OFF) Parameter Symbol min DAC Digital Filter: (Note 15) Passband (Note 16) PB 0 −0.05dB −6.0dB Stopband (Note 16) SB 24.1 Passband Ripple PR Stopband Attenuation SA 54 Group Delay (Note 17) GD Group Delay Distortion ΔGD DAC Digital Filter + Analog Filter: (Note 15, Note 18) Frequency Response FR 0 ∼ 20.0kHz Analog Filter: (Note 19) Frequency Response FR 0 ∼ 20.0kHz BOOST Filter: (Note 18, Note 20) Frequency Response 20Hz FR MIN 100Hz 1kHz 20Hz FR MID 100Hz 1kHz 20Hz FR MAX 100Hz 1kHz - typ max Units 22.05 22 0 20.0 ±0.02 - kHz kHz kHz dB dB 1/fs µs ±0.5 - dB ±1.0 - dB 5.76 2.92 0.02 10.80 6.84 0.13 16.06 10.54 0.37 - dB dB dB dB dB dB dB dB dB Note 15. BOOST OFF (BST1-0 bit = “00”) Note 16. The passband and stopband frequencies scale with fs (system sampling rate). For example, PB=0.4535fs(@−0.05dB). SB=0.546fs(@−54dB). Note 17. This time is from setting the 24-bit data of both channels from the input register to the output of analog signal. Note 18. DAC Æ HPL, HPR, LOUT, ROUT Note 19. LIN/MIN Æ HPL/LOUT, RIN/MIN Æ HPR/ROUT Note 20. These frequency responses scale with fs. If high-level signal is input, the output clips at low frequency. Boost Filter (fs=44.1kHz) 20 MAX 15 Gain [dB] MID 10 MIN 5 0 -5 10 100 1000 10000 Frequency [Hz] Figure 2. Boost Frequency (fs=44.1kHz) MS0684-E-02 2008/12 -9- [AK4372] DC CHARACTERISTICS (Ta=25°C; AVDD = DVDD=1.6 ∼ 3.6V) Parameter High-Level Input Voltage 2.2V≤DVDD≤3.6V 1.6V≤DVDD<2.2V Low-Level Input Voltage 2.2V≤DVDD≤3.6V 1.6V≤DVDD<2.2V Input Voltage at AC Coupling (Note 21) High-Level Output Voltage (Iout=−200μA) Low-Level Output Voltage (Except SDA pin: Iout=200μA) (SDA pin, 2.0V≤DVDD≤3.6V: Iout=3mA) (SDA pin, 1.6V≤DVDD<2.0V: Iout=3mA) Input Leakage Current Symbol VIH VIH VIL VIL VAC VOH min 70%DVDD 80%DVDD 0.4 DVDD−0.2 typ - max 30%DVDD 20%DVDD - Units V V V V Vpp V VOL VOL VOL Iin - - 0.2 0.4 20%DVDD ±10 V V V μA Note 21. The MCKI pin is connected to a capacitor. (Figure 50) MS0684-E-02 2008/12 - 10 - [AK4372] SWITCHING CHARACTERISTICS (Ta=25°C; AVDD = DVDD=1.6 ∼ 3.6V; CL = 20pF; unless otherwise specified) Parameter Symbol min Master Clock Input Timing Frequency (PLL mode) fCLK 11.2896 (EXT mode) fCLK 2.048 Pulse Width Low (Note 22) tCLKL 0.4/fCLK Pulse Width High (Note 22) tCLKH 0.4/fCLK AC Pulse Width (Note 23) tACW 18.5 LRCK Timing Frequency fs 8 Duty Cycle: Slave Mode Duty 45 Master Mode Duty MCKO Output Timing (PLL mode) Frequency fCLKO 0.256 Duty Cycle (Except fs=32kHz, PS1-0= “00”) dMCK 40 (fs=32kHz, PS1-0= “00”) dMCK Serial Interface Timing (Note 24) Slave Mode (M/S bit = “0”): BICK Period (Note 25) (Except PLL Mode, PLL4-0 bit = “01110”, “01111”) tBCK 312.5 or 1/(64fs) (PLL Mode, PLL4-0 bits = “01110”) tBCK (PLL Mode, PLL4-0 bits = “01111”) tBCK BICK Pulse Width Low (Except PLL Mode, PLL4-0 bit = “01110”, “01111”) tBCKL 100 (PLL Mode, PLL4-0 bit = “01110”, “01111”) tBCKL 0.4 x tBCK BICK Pulse Width High (Except PLL Mode, PLL4-0 bit = “01110”, “01111”) tBCKH 100 (PLL Mode, PLL4-0 bit = “01110”, “01111”) tBCKH 0.4 x tBCK tLRB 50 LRCK Edge to BICK “↑” (Note 26) tBLR 50 BICK “↑” to LRCK Edge (Note 26) SDATA Hold Time tSDH 50 SDATA Setup Time tSDS 50 Master Mode (M/S bit = “1”): BICK Frequency (BF bit = “1”) fBCK (BF bit = “0”) fBCK BICK Duty dBCK tMBLR BICK “↓” to LRCK −50 SDATA Hold Time tSDH 50 SDATA Setup Time tSDS 50 Control Interface Timing (3-wire Serial mode) CCLK Period tCCK 200 CCLK Pulse Width Low tCCKL 80 Pulse Width High tCCKH 80 CDTI Setup Time tCDS 40 CDTI Hold Time tCDH 40 CSN “H” Time tCSW 150 tCSS 50 CSN Edge to CCLK “↑” (Note 27) tCSH 50 CCLK “↑” to CSN Edge (Note 27) MS0684-E-02 typ max Units - 27 24.576 - MHz MHz ns ns ns 44.1 50 48 55 - kHz % % 33 12.288 60 - MHz % % 1/(32fs) 1/(64fs) 1/(32fs) - ns ns ns - - ns - - ns - - ns - - ns ns ns ns ns 64fs 32fs 50 - 50 - Hz Hz % ns ns ns - - ns ns ns ns ns ns ns ns 2008/12 - 11 - [AK4372] Parameter Symbol min typ max Units 2 Control Interface Timing (I C Bus mode): (Note 28) SCL Clock Frequency fSCL 400 kHz Bus Free Time Between Transmissions tBUF 1.3 μs Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 μs Clock Low Time tLOW 1.3 μs Clock High Time tHIGH 0.6 μs Setup Time for Repeated Start Condition tSU:STA 0.6 μs SDA Hold Time from SCL Falling (Note 29) tHD:DAT 0 μs SDA Setup Time from SCL Rising tSU:DAT 0.1 μs Rise Time of Both SDA and SCL Lines tR 0.3 μs Fall Time of Both SDA and SCL Lines tF 0.3 μs Setup Time for Stop Condition tSU:STO 0.6 μs Capacitive Load on Bus Cb 400 pF Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 50 ns Power-down & Reset Timing PDN Pulse Width (Note 30) tPD 150 ns Note 22. Except AC coupling. Note 23. Pulse width to ground level when the MCKI pin is connected to a capacitor in series and a resistor is connected to ground. (Refer to Figure 3.) Note 24. Refer to “Serial Data Interface”. Note 25. Min is longer value between 312.5ns or 1/(64fs) except for PLL Mode, PLL4-0 bits = “01110”, “01111”. Note 26. BICK rising edge must not occur at the same time as LRCK edge. Note 27. CCLK rising edge must not occur at the same time as CSN edge. Note 28. I2C is a registered trademark of Philips Semiconductors. Note 29. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 30. When power-up, the AK4372 can be reset by bringing PDN pin = “H” from “L”. MS0684-E-02 2008/12 - 12 - [AK4372] ■ Timing Diagram 1/fCLK tACW 1000pF tACW Measurement Point MCKI Input VAC 100kΩ VSS2 VSS2 Figure 3. MCKI AC Coupling Timing 1/fCLK VIH MCKI VIL tCLKH tCLKL 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL MCKO 50% DVDD tH tL dMCK=tH/(tH+tL) or tL/(tH+tL) Figure 4. Clock Timing MS0684-E-02 2008/12 - 13 - [AK4372] VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDH tSDS VIH SDATA VIL Figure 5. Serial Interface Timing (Slave Mode) 50%DVDD LRCK tMBLR BICK 50%DVDD tSDH tSDS VIH SDATA VIL Figure 6. Serial Interface Timing (Master mode) MS0684-E-02 2008/12 - 14 - [AK4372] VIH CSN VIL tCSS tCSH tCCKL tCCKH VIH CCLK VIL tCCK tCDH tCDS VIH CDTI C1 C0 R/W VIL Figure 7. WRITE Command Input Timing tCSW VIH CSN VIL tCSH tCSS VIH CCLK VIL VIH CDTI D2 D1 D0 VIL Figure 8. WRITE Data Input Timing VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA tSU:STO Start Stop Figure 9. I2C Bus Mode Timing tPD PDN VIL Figure 10. Power-down & Reset Timing MS0684-E-02 2008/12 - 15 - [AK4372] OPERATION OVERVIEW ■ System Clock There are the following six clock modes to interface with external devices (Table 1 and Table 2). Mode PLL Master Mode PLL Slave Mode 1 (PLL Reference Clock: MCKI pin) PLL Slave Mode 2 (PLL Reference Clock: BICK pin) PLL Slave Mode 3 (PLL Reference Clock: LRCK pin) EXT Master Mode EXT Slave Mode Mode PLL Master Mode PLL Slave Mode 1 (PLL Reference Clock: MCKI pin) PMPLL bit 1 M/S bit 1 PLL3-0 bits See Table 4 Figure Figure 11 1 0 See Table 4 Figure 12 1 0 See Table 4 Figure 13 1 0 See Table 4 Figure 14 x x Figure 15 Figure 16 0 1 0 0 Table 1. Clock Mode Setting (x: Don’t care) MCKO bit 0 1 0 1 MCKO pin L Selected by PS1-0 bits L Selected by PS1-0 bits MCKI pin Selected by PLL4-0 bits Selected by PLL4-0 bits PLL Slave Mode 2 (PLL Reference Clock: BICK pin) 0 L GND PLL Slave Mode 3 (PLL Reference Clock: LRCK pin) 0 L GND EXT Master Mode 0 L Selected by FS3-0 bits EXT Slave Mode Selected by FS3-0 bits Table 2. Clock pins state in Clock Mode 0 L BICK pin Output (Selected by BF bit) LRCK pin Input (32fs ∼ 64fs) Input (1fs) Input (Selected by PLL4-0 bits) Input (32fs ∼ 64fs) Output (Selected by BF bit) Input (32fs ∼ 64fs) Output (1fs) Input (1fs) Input (1fs) Output (1fs) Input (1fs) ■ Master Mode/Slave Mode The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the AK4372 is power-down mode (PDN pin = “L”) and exits reset state, the AK4372 is slave mode. After exiting reset state, the AK4372 changes to master mode by setting M/S bit = “1”. When the AK4372 is in master mode, the LRCK and BICK pins are a floating state until M/S bit becomes “1”. The LRCK and BICK pins of the AK4372 should be pulled-down or pulled-up by a resistor (about 100kΩ) externally to avoid the floating state. M/S bit Mode 0 Slave Mode (default) 1 Master Mode Table 3. Select Master/Slave Mode MS0684-E-02 2008/12 - 16 - [AK4372] ■ PLL Mode (PMPLL bit = “1”) When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL4-0 and FS3-0 bits (Table 4, Table 5, Table 6). The PLL lock time is shown in Table 4, whenever the AK4372 is supplied to a stable clocks after PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes. 1) Setting of PLL Mode Mode PLL4 PLL3 PLL2 PLL1 PLL0 Reference Clock fs (Note 31) R,C at VCOC R[Ω] C[F] 10k 22n 10k 22n 10k 47n 10k 22n 10k 22n 15k 330n 10k 47n 10k 47n 15k 330n 10k 47n 10k 22n 10k 22n 10k 22n 10k 22n 6.8k 47n 6.8k 47n 6.8k 330n 0 0 0 0 0 0 MCKI 11.2896MHz Type 1 1 0 0 0 0 1 MCKI 14.4MHz Type 1 2 0 0 0 1 0 MCKI 12MHz Type 1 3 0 0 0 1 1 MCKI 19.2MHz Type 1 4 0 0 1 0 0 MCKI 15.36MHz Type 1 5 0 0 1 0 1 MCKI 13MHz Type 1 6 0 0 1 1 0 MCKI 19.68MHz Type 1 7 0 0 1 1 1 MCKI 19.8MHz Type 1 8 0 1 0 0 0 MCKI 26MHz Type 1 9 0 1 0 0 1 MCKI 27MHz Type 1 10 0 1 0 1 0 MCKI 13MHz Type 2 11 0 1 0 1 1 MCKI 26MHz Type 2 12 0 1 1 0 0 MCKI 19.8MHz Type 3 13 0 1 1 0 1 MCKI 27MHz Type 4 14 0 1 1 1 0 BICK 32fs Table 6 15 0 1 1 1 1 BICK 64fs Table 6 16 1 0 0 0 0 LRCK fs Table 6 Others Others N/A Note 31. Refer to Table5 about Type1-4 Note 32 : Clock jitter is lower in Mode10-13 than Mode5/ 7/ 8/ 9 respectively Note 33. Modes 14~16 are available at Slave Mode only. Table 4. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not available) PLL Lock Time (typ) 20ms 20ms 20ms 20ms 20ms 100ms 20ms 20ms 100ms 20ms 20ms 20ms 20ms 20ms 20ms 20ms 80ms (default) 2) Setting of sampling frequency in PLL Mode When PLL reference clock input is MCKI pin, the sampling frequency is selected by FS3-0 bits as defined in Table 5. Mode FS3 FS2 FS1 FS0 fs Type 1 48kHz 24kHz 12kHz 32kHz 16kHz 8kHz 44.1kHz 22.05kHz 11.025kHz Type 2 48.0007kHz 24.0004kHz 12.0002kHz 32.0005kHz 16.0002kHz 8.0001kHz 44.0995kHz 22.0498kHz 11.0249kHz Type 3 47.9992kHz 23.9996kHz 11.9998kHz 31.9994kHz 15.9997kHz 7.9999kHz 44.0995kHz 22.0498kHz 11.0249kHz Type 4 47.9997kHz 23.9999kHz 11.9999kHz 31.9998kHz 15.9999kHz 7.9999kHz 44.0995kHz 22.0498kHz 11.0249kHz 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 8 1 0 0 0 (default) 9 1 0 0 1 10 1 0 1 0 3, 7, Others N/A N/A N/A N/A 11-15 Table 5. Setting of Sampling Frequency (PLL reference clock input is the MCKI pin) (N/A: Not available) MS0684-E-02 2008/12 - 17 - [AK4372] When PLL reference clock input is the LRCK or BICK pin, the sampling frequency is selected by FS3-0 bits. (Table 6) Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency Range 0 0 0 1 0 (default) 32kHz < fs ≤ 48kHz 0 1 1 1 0 24kHz < fs ≤ 32kHz 0 0 2 1 1 16kHz < fs ≤ 24kHz 0 1 3 1 1 12kHz < fs ≤ 16kHz 1 0 4 1 0 8kHz ≤ fs ≤ 12kHz Others Others N/A Table 6. Setting of Sampling Frequency (PLL reference clock input is LRCK or BICK pin) (N/A: Not available) ■ PLL Unlock State 1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) In master mode (M/S bits = “1”), the LRCK and BICK pins output “L” before the PLL is locked by setting PMPLL = PMDAC bits = “0” Æ “1”. At that time, the MCKO pin outputs an irregular frequency clock at MCKO bit = “1”. When MCKO bit = “0”, the MCKO pin outputs “L”. After the PLL is locked, the LRCK and BICK start outputting the clocks (Table 7). Master Mode (M/S bit = “1”) Power Up Power Down PLL Unlock (PMDAC bit= PMPLL bit= “1”) (PMDAC bit= PMPLL bit= “0”) Input or MCKI pin Refer to Table 4. Refer to Table 4. fixed to “L” or “H” externally MCKO bit = “0”: “L” MCKO bit = “0”: L MCKO pin L MCKO bit = “1”: Output MCKO bit = “1”: Unsettling BF bit = “1”: 64fs output BICK pin L L BF bit = “0”: 32fs output LRCK pin Output L L Table 7. Clock Operation in Master mode (PLL mode) 2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) In slave mode (M/S bits = “0”), an invalid clock is output from the MCKO pin when MCKO bit = “1”, before the PLL is locked by setting PMPLL = PMDAC bits = “0” Æ “1”. When MCKO bit = “0”, the MCKO pin outputs “L”. After the PLL is locked, the MCKO pin starts outputting the clocks (Table 9). Slave Mode (M/S bit = “0”) Power Up Power Down (PMDAC bit= PMPLL bit= “1”) (PMDAC bit= PMPLL bit= “0”) Input or MCKI pin Refer to Table 4. fixed to “L” or “H” externally MCKO bit = “0”: “L” MCKO pin L MCKO bit = “1”: Output BICK pin LRCK pin PLL Unlock Refer to Table 4. MCKO bit = “0”: L MCKO bit = “1”: Unsettling Input or Input Fixed to “L” or “H” externally Fixed to “L” or “H” externally Input or Input Fixed to “L” or “H” externally Fixed to “L” or “H” externally Table 8. Clock Operation in Slave mode (PLL mode) MS0684-E-02 2008/12 - 18 - [AK4372] ■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) When an external clock (11.2896MHz, 12MHz, 13MHz, 14.4MHz, 15.36MHz, 19.2MHz, 19.68MHz,19.8MHz, 26MHz or 27MHz) is input to the MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO output frequency is selected by PS1-0 bits (Table 9) and the output is enabled by MCKO bit. The BICK output frequency is selected between 32fs or 64fs, by BF bit (Table 10). 27MHz,26MHz,19.8MHz,19.68MHz, 19.2MHz,15.36MHz,14.4MHz,13MHz, 12MHz,11.2896MHz AK4372 DSP or μP MCKI MCKO BICK LRCK 256fs/128fs/64fs/32fs 32fs, 64fs 1fs MCLK BCLK LRCK SDTO SDATA Figure 11. PLL Master Mode PS1 PS0 MCKO 0 0 256fs (default) 0 1 128fs 1 0 64fs 1 1 32fs Table 9. MCKO Frequency (PLL mode, MCKO bit = “1”) BF bit BICK Frequency 0 32fs (default) 1 64fs Table 10. BICK Output Frequency at Master Mode MS0684-E-02 2008/12 - 19 - [AK4372] ■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) A reference clock of PLL is selected among the input clocks to the MCKI, BICK or LRCK pin. The required clock to the AK4372 is generated by an internal PLL circuit. Input frequency is selected by PLL4-0 bits (Table 4). a) PLL reference clock: MCKI pin BICK and LRCK inputs should be synchronized with MCKO output. The phase between MCKO and LRCK dose not matter. The MCKO pin outputs the frequency selected by PS1-0 bits (Table 9) and the output is enabled by MCKO bit. Sampling frequency can be selected by FS3-0 bits (Table 5). The external clocks (MCKI, BICK and LRCK) should always be present whenever the DAC is in operation (PMDAC bit = “1”). If these clocks are not provided, the AK4372 may draw excess current and will not possible to operate properly because it utilizes dynamic refreshed logic internally. If the external clocks are not present, the DAC should be in the power-down mode (PMDAC bits = “0”). 27MHz,26MHz,19.8MHz,19.68MHz, 19.2MHz,15.36MHz,14.4MHz,13MHz, 12MHz,11.2896MHz AK4372 DSP or μP MCKI MCKO BICK LRCK 256fs/128fs/64fs/32fs 32fs ~ 64fs 1fs MCLK BCLK LRCK SDTO SDATA Figure 12. PLL Slave Mode (PLL Reference Clock: MCKI pin) b) PLL reference clock: BICK pin Sampling frequency corresponds to 8kHz to 48kHz by changing FS3-0 bits (Table 6). AK4372 DSP or μP MCKI MCKO BICK LRCK 32fs or 64fs 1fs BCLK LRCK SDTO SDATA Figure 13. PLL Slave Mode (PLL Reference Clock: BICK pin) MS0684-E-02 2008/12 - 20 - [AK4372] c) PLL reference clock: LRCK pin Sampling frequency corresponds to 8kHz to 48kHz by changing FS3-0 bits (Table 6). AK4372 DSP or μP MCKI MCKO BICK LRCK 32fs ∼ 64fs 1fs BCLK LRCK SDTO SDATA Figure 14. PLL Slave Mode (PLL Reference Clock: LRCK pin) MS0684-E-02 2008/12 - 21 - [AK4372] ■ EXT Mode (PMPLL bit = “0”: Default) The AK4372 can be placed in external clock mode (EXT mode) by setting the PMPLL bit to “0”. In EXT mode, the master clock can directly input to the DAC via the MCKI pin without going through the PLL. In this case, the sampling frequency and MCKI frequency can be selected by FS3-0 bits (Table 11). In EXT mode, PLL4-0 bits are ignored. MCKO output is enabled by MCKO bit. The MCKO output frequency can be controlled by PS1-0 bits. If the sampling frequency is changed during normal operation of the DAC (PMDAC bit = “1”), the input must be muted by SMUTE bit = “1”, or set to “0” data. LRCK and BICK are output from the AK4372 in master mode(Figure 15). The clock input to the MCKI pin should always be present whenever the DAC is in normal operation (PMDAC bit = “1”). If these clocks are not provided, the AK4372 may draw excessive current and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the DAC should be placed in power-down mode (PMDAC bit = “0”). AK4372 DSP or μP MCKO 256fs, 384fs, 512fs, 768fs or 1024fs MCKI 32fs, 64fs BICK 1fs LRCK MCLK BCLK LRCK SDTO SDATA Figure 15. EXT Master Mode The external clocks required to operate the AK4372 in slave mode are MCKI, LRCK and BICK(Figure 16). The master clock (MCKI) should be synchronized with the sampling clock (LRCK). The phase between these clocks does not matter. All external clocks (MCKI, BICK and LRCK) should always be present whenever the DAC is in normal operation mode (PMDAC bit = “1”). If these clocks are not provided, the AK4372 may draw excessive current and will not operate properly, because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the DAC should be placed in power-down mode (PMDAC bit = “0”). AK4372 DSP or μP MCKO MCKI BICK LRCK 256fs, 384fs, 512fs, 768fs or 1024fs 32fs, 64fs 1fs MCLK BCLK LRCK SDTO SDATA Figure 16. EXT Slave Mode MS0684-E-02 2008/12 - 22 - [AK4372] Mode FS3 FS2 FS1 FS0 fs MCKI 0 0 0 0 0 256fs 8kHz ∼ 48kHz 1 0 0 0 1 512fs 8kHz ∼ 48kHz 2 0 0 1 0 1024fs 8kHz ∼ 24kHz 4 0 1 0 0 256fs 8kHz ∼ 48kHz 5 0 1 0 1 512fs 8kHz ∼ 48kHz 6 0 1 1 0 1024fs 8kHz ∼ 24kHz 8 1 0 0 0 256fs (default) 8kHz ∼ 48kHz 9 1 0 0 1 512fs 8kHz ∼ 48kHz 10 1 0 1 0 1024fs 8kHz ∼ 24kHz 12 1 1 0 0 384fs 8kHz ∼ 48kHz 13 1 1 0 1 768fs 8kHz ∼ 24kHz Others Others N/A N/A Table 11. Relationship between Sampling Frequency and MCKI Frequency (EXT mode) (N/A: Not available) PS1 PS0 MCKO 0 0 256fs (default) 0 1 128fs 1 0 64fs 1 1 32fs Table 12. MCKO frequency (EXT mode, MCKO bit = “1”) MCKI pin MCKO pin BICK pin LRCK pin Master Mode (M/S bit = “1”) Power Up (PMDAC bit = “1”) Power Down (PMDAC bit = “0”) Input or Refer to Table 11 fixed to “L” or “H” externally MCKO bit = “0”: L L MCKO bit = “1”: Output BF bit = “1”: 64fs output L BF bit = “0”: 32fs output Output L Table 13. Clock Operation in Master mode (EXT mode) Slave Mode (M/S bit = “0”) Power Up (PMDAC bit = “1”) Power Down (PMDAC bit = “0”) Input or MCKI pin Refer to Table 11 fixed to “L” or “H” externally MCKO bit = “0”: L MCKO pin L MCKO bit = “1”: Output BICK pin Input Fixed to “L” or “H” externally LRCK pin Input Fixed to “L” or “H” externally Table 14. Clock Operation in Slave mode (EXT mode) For low sampling rates, DR and S/N degrade because of the out-of-band noise. DR and S/N are improved by using higher frequency for MCKI. Table 15 shows DR and S/N when the DAC output is to the HP-amp. DR, S/N (BW=20kHz, A-weight) fs=8kHz fs=16kHz 256fs/384fs/512fs 56dB 75dB 768fs/1024fs 75dB 90dB Table 15. Relationship between MCKI frequency and DR (and S/N) of HP-amp (2.4V) MCKI MS0684-E-02 2008/12 - 23 - [AK4372] ■ Serial Data Interface The AK4372 interfaces with external systems via the SDATA, BICK and LRCK pins. Five data formats are available, selected by setting the DIF2, DIF1 and DIF0 bits (Table 16). Mode 0 is compatible with existing 16-bit DACs and digital filters. Mode 1 is a 20-bit version of Mode 0. Mode 4 is a 24-bit version of Mode 0. Mode 2 is similar to AKM ADCs and many DSP serial ports. Mode 3 is compatible with the I2S serial data protocol. In Modes 2 and 3 with BICK≥48fs, the following formats are also valid: 16-bit data followed by eight zeros (17th to 24th bits) and 20-bit data followed by four zeros (21st to 24th bits). In all modes, the serial data is MSB first and 2’s complement format. When master mode and BICK=32fs(BF bit = “0”), the AK4372 cannot be set to Mode 1 Mode 2 or Mode 4. Mode 0 1 2 3 4 DIF2 0 0 0 0 1 DIF1 0 0 1 1 0 DIF0 0 1 0 1 0 Format BICK 0: 16bit, LSB justified 32fs ≤ BICK ≤ 64fs 1: 20bit, LSB justified 40fs ≤ BICK ≤ 64fs 2: 24bit, MSB justified 48fs ≤ BICK ≤ 64fs 3: I2S Compatible BICK=32fs or 48fs ≤ BICK ≤ 64fs 4: 24bit, LSB justified 48fs ≤ BICK ≤ 64fs Table 16. Audio Data Format Figure Figure 17 Figure 18 Figure 19 Figure 20 Figure 18 (default) LRCK BICK (32fs) SDATA Mode 0 15 14 6 5 4 3 2 15 14 1 0 15 14 0 Don’t care 6 5 4 3 2 1 0 15 14 0 19 0 19 0 15 14 BICK SDATA Mode 0 Don’t care 15:MSB, 0:LSB Lch Data Rch Data Figure 17. Mode 0 Timing (LRP = BCKP bits = “0”) LRCK BICK SDATA Mode 1 Don’t care 19 0 Don’t care 19 0 Don’t care 19:MSB, 0:LSB SDATA Mode 4 Don’t care 23 22 21 20 23 22 21 20 23:MSB, 0:LSB Lch Data Rch Data Figure 18. Mode 1, 4 Timing (LRP = BCKP bits = “0”) MS0684-E-02 2008/12 - 24 - [AK4372] Rch Lch LRCK BICK SDATA 15 14 0 19 18 4 1 0 23 22 8 3 4 Don’t care 15 14 0 Don’t care 19 18 4 1 0 Don’t care 23 22 8 3 4 Don’t care 15 14 Don’t care 19 18 Don’t care 23 22 16bit SDATA 20bit SDATA 1 0 1 0 24bit Figure 19. Mode 2 Timing (LRP = BCKP bits = “0”) Lch LRCK Rch BICK SDATA 16bit SDATA 20bit SDATA 24bit 15 14 0 19 18 4 1 0 23 22 8 3 4 1 0 15 14 6 5 4 3 2 Don’t care 15 14 0 Don’t care 19 18 4 1 0 Don’t care 23 22 8 3 4 1 15 14 6 5 4 3 Don’t care 15 Don’t care 19 0 Don’t care 23 2 1 BICK (32fs) SDATA 16bit 0 1 0 0 15 Figure 20. Mode 3 Timing (LRP = BCKP bits = “0”) MS0684-E-02 2008/12 - 25 - [AK4372] ■ Digital Attenuator The AK4372 has a channel-independent digital attenuator (256 levels, 0.5dB step). This digital attenuator is placed before the D/A converter. ATTL/R7-0 bits set the attenuation level (0dB to −127dB or MUTE) for each channel (Table 17). At DATTC bit = “1”, ATTL7-0 bits control both channel’s attenuation levels. At DATTC bit = “0”, ATTL7-0 bits control the left channel level and ATTR7-0 bits control the right channel level. ATTL7-0 Attenuation ATTR7-0 FFH 0dB FEH −0.5dB FDH −1.0dB FCH −1.5dB : : 02H −126.5dB 01H −127.0dB 00H (default) MUTE (−∞) Table 17. Digital Volume ATT values The ATS bit sets the transition time between set values of ATT7-0 bits as either 1061/fs or 7424/fs (Table 18). When the ATS bit = “0”, a soft transition between the set values occurs(1062 levels). It takes 1061/fs (24ms@fs=44.1kHz) from FFH(0dB) to 00H(MUTE). The ATTs are 00H when the PMDAC bit is “0”. When the PMDAC returns to “1”, the ATTs fade to their current value. The digital attenuator is independent of the soft mute function. ATT speed 0dB to MUTE 1 step 0 1061/fs 4/fs (default) 1 7424/fs 29/fs Table 18. Transition time between set values of ATT7-0 bits ATS MS0684-E-02 2008/12 - 26 - [AK4372] ■ Soft Mute Soft mute operation is performed in the digital domain. When the SMUTE bit changes to “1”, the output signal is attenuated by −∞ during the ATT_DATA×ATT transition time (Table 18) from the current ATT level. When the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA×ATT transition time. If the soft mute is cancelled before attenuating to −∞ after starting the operation, the attenuation is discontinued and is returned to the ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission. SMUTE bit ATT Level ATS bit ATS bit (1) (1) (3) Attenuation -∞ GD (2) GD Analog Output Figure 21. Soft Mute Function Notes: (1) ATT_DATA×ATT transition time (Table 18). For example, this time is 3712LRCK cycles (3712/fs) at ATS bit = “1” and ATT_DATA = “128”(-63.5dB). (2) The analog output corresponding to the digital input has a group delay, GD. (3) If the soft mute is cancelled before attenuating to −∞ after starting the operation, the attenuation is discontinued and it is returned to the ATT level by the same cycle. MS0684-E-02 2008/12 - 27 - [AK4372] ■ De-emphasis Filter The AK4372 includes a digital de-emphasis filter (tc = 50/15μs), using an IIR filter corresponding to three sampling frequencies (32kHz, 44.1kHz and 48kHz). The de-emphasis filter is enabled by setting DEM1-0 bits (Table 19). DEM1 bit DEM0 bit De-emphasis 0 0 44.1kHz 0 1 OFF (default) 1 0 48kHz 1 1 32kHz Table 19. De-emphasis Filter Frequency Select ■ Bass Boost Function By controlling the BST1-0 bits, a low frequency boost signal can be output from DAC. The setting value is common for both channels (Table 20). BST1 bit BST0 bit BOOST 0 0 OFF (default) 0 1 MIN 1 0 MID 1 1 MAX Table 20. Low Frequency Boost Select ■ Digital Mixing Function MONO1-0 bits select the digital data mixing for the DAC (Table 21). MONO1 bit 0 0 1 1 MONO0 bit Lch 0 L 1 L 0 R 1 (L+R)/2 Table 21. Mixer Setting Rch R L R (L+R)/2 (default) ■ System Reset The PDN pin should be held to “L” upon power-up. The 4372 should be reset by bringing the PDN pin “L” for 150ns or more. All of the internal register values are initialized by the system reset. After exiting reset, VCOM, DAC, HPL, HPR, LOUT and ROUT switch to the power-down state. The contents of the control register are maintained until the reset is completed. The DAC exits reset and power down states by MCKI after the PMDAC bit is changed to “1”. The DAC is in power-down mode until MCKI is input. MS0684-E-02 2008/12 - 28 - [AK4372] ■ Headphone Output (HPL, HPR pins) The power supply voltage for the headphone-amp is supplied from the AVDD pin and is centered on the MUTET voltage. The headphone-amp output load resistance is 16Ω (min). When the MUTEN bit is “1” at PMHPL=PMHPR= “1”, the common voltage rises to 0.475 x AVDD. When the MUTEN bit is “0”, the common voltage of the headphone-amp falls and the outputs (HPL and HPR pins) go to VSS1. 70k x C (typ) tr: Rise Time up to VCOM/2 tf: Fall Time down to VCOM/2 60k x C (typ) Table 22. Headphone-Amp Rise/Fall Time [Example] : Capacitor between the MUTET pin and ground = 1μF: Rise time up to VCOM/2: tr = 70k x 1μ = 70ms(typ). Fall time down to VCOM/2: tf = 60k x 1μ = 60ms(typ). When the PMHPL and PMHPR bits are “0”, the headphone-amp is powered-down, and the outputs (HPL and HPR pins) go to VSS1. PMHPL/R bit MUTEN bit HPL/R pin VCOM VCOM/2 tf tr (1) (2) (3) (4) Figure 22. Power-up/Power-down Timing for the Headphone-Amp (1) Headphone-amp power-up (PMHPL and PMHPR bits = “1”). The outputs are still at VSS1. (2) Headphone-amp common voltage rises up (MUTEN bit = “1”). Common voltage of the headphone-amp is rising. This rise time depends on the capacitor value connected with the MUTET pin. The rise time up to VCOM/2 is tr = 70k x C(typ) when the capacitor value on MUTET pin is “C”. (3) Headphone-amp common voltage falls down (MUTEN bit = “0”). Common voltage of the headphone-amp is falling to VSS1. This fall time depends on the capacitor value connected with the MUTET pin. The fall time down to VCOM/2 is tf = 60k x C(typ) when the capacitor value on the MUTET pin is “C”. (4) Headphone-amp power-down (PMHPL, PMHPR bits = “0”). The outputs are at VSS1. If the power supply is switched off or the headphone-amp is powered-down before the common voltage settles to VSS1, some pop noise may occur. MS0684-E-02 2008/12 - 29 - [AK4372] < External Circuit of Headphone-Amp > The cut-off frequency of the headphone-amp output depends on the external resistor and capacitor used. Table 23 shows the cut off frequency and the output power for various resistor/capacitor combinations. The headphone impedance RL is 16Ω. Output powers are shown at AVDD = 2.4, 3.0 and 3.3V. The output voltage of the headphone-amp is 0.48 x AVDD (Vpp) @−3dBFS. HP-AMP R C Headphone 16Ω AK4372 Figure 23. External Circuit Example of Headphone R [Ω] C [μF] 0 6.8 16 220 100 100 47 100 47 fc [Hz] BOOST=OFF fc [Hz] BOOST=MIN Output Power [mW] 2.4V 3.0V 45 17 21 33 100 43 70 28 10 16 149 78 50 19 5 8 106 47 Table 23. Relationship of external circuit, output power and frequency response 3.3V 40 20 10 < Wired OR with External Headphone-Amp > When PMVCM=PMHPL=PMHPR bits = “0” and HPZ bit = “1”, Headphone-amp is powered-down and HPL/R pins are pulled-down to VSS1 by 200kΩ (typ). In this setting, it is able to connect headphone-amp of AK4372 and external single supply headphone-amp by “wired OR”. PMVCM x 0 1 1 PMHPL/R 0 0 1 1 HPMTN HPZ Mode x 0 Power-down & Mute x 1 Power-down 0 x Mute 1 x Normal Operation Table 24. HP-Amp Mode Setting (x: Don’t care) HPL/R pins VSS1 Pull-down by 200kΩ VSS1 Normal Operation (default) HPL pin AK4372 Headphone HPR pin Another HP-Amp Figure 24. Wired OR with External HP-Amp MS0684-E-02 2008/12 - 30 - [AK4372] < Analog Mixing Circuit for Headphone Output > DALHL, LINHL, RINHL and MINHL bits control each path switch of the HPL output. DARHR, LINHR, RINHR and MINHR bits control each path switch of the HPR output. When LHM bit = “0”, HPG1-0 bits = “00” (R1H= R2H = RDH= 100k) and ATTH4-0 bits = “00H”(0dB), the mixing gain is +0.95dB(typ). When HPG1-0 bit = “01” (RDH= 50k), the mixing gain of DAC path is +6.95dB(typ). When HPG1-0 bit = “10” (RDH= 25k), the mixing gain of DAC path is +12.95dB(typ). When LHM bit is “1”, LIN and RIN signals are output from the HPL/R pins as (L+R)/2 respectively. When LDIF=LDIFH=LINL=RINR bits = “1”, the LIN and RIN pins becomes IN+ and IN− pins, respectively. The IN+ and IN− pins can be used as full-differential mono line input for analog mixing for headphone-amp. In this case, LINHL, RINHL, LINHR and RINHR bits should be “0”. If the path is OFF and the signal is input to the input pin, the input pin should be biased to a voltage equivalent to VCOM voltage (= 0.475 x AVDD) externally. Figure 51 shows the external bias circuit example. 100k(typ) Figure 27 LDIFH bit R1H LIN pin LINHL bit R1H RIN pin RINHL bit R2H MIN pin 100k(typ) 1.11RH MINHL bit RDH DAC Lch DALHL bit − RH + − HPL pin + HP-Amp 100k(typ) Figure 27 LDIFH bit R1H LIN pin LINHR bit R1H RIN pin RINHR bit R2H MIN pin 100k(typ) 1.11RH MINHR bit RDH DAC Rch DARHR bit − RH + − + HPR pin HP-Amp Figure 25. Summation circuit for HPL/R output MS0684-E-02 2008/12 - 31 - [AK4372] ■ Headphone Output Volume HPL/HPR volume is controlled by ATTH4-0 bits when HMUTE bit = “0” (+12dB ∼ −51dB or +6dB ∼ −57dB or 0dB ∼ −63dB, 1.5dB or 3dB step, Table 25) HMUTE ATTH4-0 0 1 00H 01H 02H 03H : 12H 13H 14H 15H 16H : 1DH 1EH 1FH x HPG1-0 bits = “10” (DAC Only) +12dB +10.5dB +9dB +7.5dB : −15dB −16.5dB −18dB −21dB −24dB : −45dB −48dB −51dB MUTE HPG1-0 bits = “01” (DAC Only) +6dB +4.5dB +3dB +1.5dB : −21dB −22.5dB −24dB −27dB −30dB : −51dB −54dB −57dB MUTE HPG1-0 bits = “00” 0dB −1.5dB −3dB −4.5dB : −27dB −28.5dB −30dB −33dB −36dB : −57dB −60dB −63dB MUTE STEP (default) 1.5dB 3dB Table 25. HPL/HPR Volume ATT values (x: Don’t care) MS0684-E-02 2008/12 - 32 - [AK4372] ■ Stereo Line Output (LOUT, ROUT pins) The common voltage is 0.475 x AVDD. The load resistance is 10kΩ(min). When the PMLO bit is “1”, the stereo line output is powered-up. DALL, LINL, RINL and MINL bits control each path switch of LOUT. DARR, LINR, RINR and MINR bits control each path switch of ROUT. When LM bit = “0”, LOG bit = “0” (R1L = R2L = RDL = 100k) and ATTS3-0 bits is “0FH”(0dB), the mixing gain is 0dB(typ) for all paths. When the LOG bit = “1”(RDL= 50k), the DAC path gain is +6dB. When LM bit = “1”, LIN and RIN signals are output from LOUT/ROUT pins as (L+R)/2 respectively. If the path is OFF and the signal is input to the input pin, the input pin should be biased to a voltage equivalent to VCOM voltage (= 0.475 x AVDD) externally. Figure 51 shows the external bias circuit example. R1L LIN pin LINL bit R1L RIN pin RINL bit R2L 100k(typ) MIN pin RL MINL bit RDL DAC Lch DALL bit − RL + − LOUT pin + R1L LIN pin LINR bit R1L RIN pin RINR bit R2L 100k(typ) MIN pin RL MINR bit RDL DAC Rch DARR bit − RL + − + ROUT pin Figure 26. Summation circuit for stereo line output MS0684-E-02 2008/12 - 33 - [AK4372] < Analog Mixing Circuit of Full-differential Mono input > When LDIF=LINL=RINR bits = “1”, the LIN and RIN pins becomes IN+ and IN− pins, respectively. The IN− and IN+ pins can be used as full-differential mono line input for analog mixing of LOUT/ROUT pins. It is not available to mix with other signal source for LOUT/ROUT outputs. If the path is OFF and the signal is input to the input pin, the input pin should be biased to a voltage equivalent to VCOM voltage (= 0.475 x AVDD) externally. Figure 51 shows the external bias circuit example. Figure 25 HPL/R pins LDIFH bit R2L IN− pin 100k(typ) RL LINL bit 100k(typ) LDIF bit − RL + R2L IN+ pin − LOUT pin + 100k(typ) RL RINR bit − RL + − + ROUT pin Figure 27. Summation circuit for stereo line output (Full-differential input) ■ Stereo Line Output (LOUT/ROUT pins) Volume LOUT/ROUT volume is controlled by ATTS3-0 bits when LMUTE bit = “0” (+6dB ∼ −24dB or 0dB ∼ −30dB, 2dB step, Table 26). Pop noise occurs when ATTS3-0 bits are changed. LOG bit = “1” LOG bit = “0” (DAC Only) FH +6dB 0dB EH +4dB −2dB DH +2dB −4dB CH 0dB −6dB : : : 1H −22dB −28dB 0H −24dB −30dB x MUTE MUTE (default) Table 26. LOUT/ROUT Volume ATT values (x: Don’t care) LMUTE 0 1 ATTS3-0 MS0684-E-02 2008/12 - 34 - [AK4372] ■ Power-Up/Down Sequence (EXT mode) 1) DAC → HP-Amp Power Supply (10) (1) >150ns PDN pin Don’t care (2) >0s PMVCM bit Don’t care (3) Don’t care Don’t care Clock Input PMDAC bit DAC Internal State PD Normal Operation PD Normal Operation PD SDTI pin DALHL, DARHR bits (4) >0s PMHPL, PMHPR bits (4) >0s (5) >2ms (5) >2ms MUTEN bit ATTL7-0 ATTR7-0 bits 00H(MUTE) FFH(0dB) (8) GD (9) 1061/fs (6) FFH(0dB) 00H(MUTE) (8) (8) (9) (7) (6) (9) 00H(MUTE) (8) (9) (7) HPL/R pin Figure 28. Power-up/down sequence of DAC and HP-amp (Don’t care: except Hi-Z) (1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or more. The PDN pin should be set to “H” at least 150ns after power is supplied. (2) PMVCM and PMDAC bits should be changed to “1” after the PDN pin is set to “H”. (3) External clocks (MCKI, BICK, LRCK) are needed to operate the DAC. When the PMDAC bit = “0”, these clocks can be stopped. The headphone-amp can operate without these clocks. (4) DALHL and DARHR bits should be changed to “1” after PMVCM and PMDAC bit is changed to “1”. (5) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin is 2.2μF) after the DALHL and DARHR bits are changed to “1” (6) Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to VCOM/2 is tr = 70k x C(typ). When C=1μF, tr = 70ms(typ). (7) Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to VCOM/2 is tf = 60k x C(typ). When C=1μF, tf = 60ms(typ). PMHPL and PMHPR bits should be changed to “0” after the HPL and HPR pins settle to VSS1. After that, the DALHL and DARHR bits should be changed to “0”. (8) Analog output corresponding to the digital input has a group delay (GD) of 22/fs(=499µs@fs=44.1kHz). (9) The ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz). (10) The power supply should be switched off after the headphone-amp is powered down (HPL/R pins become “L”). When AVDD and DVDD are supplied separately, DVDD should be powered-down at the same time or later than AVDD. MS0684-E-02 2008/12 - 35 - [AK4372] 2) DAC → Lineout Power Supply (1) >150ns PDN pin PMVCM bit (2) >0s Don’t care (5) Clock Input Don’t care Don’t care (4) >0s PMDAC bit DAC Internal State PD Normal Operation PD(Power-down) Normal Operation SDTI pin DALL, DARR bits (3) >0s PMLO bit ATTL/R7-0 bits LMUTE, ATTS3-0 bits FFH(0dB) 00H(MUTE) FFH(0dB) 0FH(0dB) 10H(MUTE) (7) GD LOUT/ROUT pins 00H(MUTE) (8) 1061/fs (7) (6) (8) (7) (Hi-Z) (8) (6) (6) (Hi-Z) Figure 29. Power-up/down sequence of DAC and LOUT/ROUT (Don’t care: except Hi-Z) (1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or more. The PDN pin should be set to “H” at least 150ns after power is supplied. (2) PMVCM bit should be changed to “1” after the PDN pin is set to “H”. (3) DALL and DARR bits should be changed to “1” after the PMVCM bit is changed to “1”. (4) PMDAC and PMLO bits should be changed to “1” after DALL and DARR bits is changed to “1”. (5) External clocks (MCKI, BICK, LRCK) are needed to operate the DAC. When the PMDAC bit = “0”, these clocks can be stopped. The LOUT/ROUT buffer can operate without these clocks. (6) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins. (7) Analog output corresponding to the digital input has a group delay (GD) of 22/fs(=499μs@fs=44.1kHz). (8) The ATS bit sets the transition time of the digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz). MS0684-E-02 2008/12 - 36 - [AK4372] 3) LIN/RIN/MIN → HP-Amp Power Supply (1) >150ns PDN pin (2) >0s PMVCM bit Don’t care LINHL, MINHL, RINHR, MINHR bits (3) >0s PMHPL/R bits (5) >2ms (5) >2ms MUTEN bit (Hi-Z) (4) LIN/RIN/MIN pins (Hi-Z) (7) (6) (6) HPL/R pins Figure 30. Power-up/down sequence of LIN/RIN/MIN and HP-Amp (1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or more. The PDN pin should be set to “H” at least 150ns after power is supplied. MCKI, BICK and LRCK can be stopped when DAC is not used. (2) PMVCM bit should be changed to “1” after the PDN pin is set to “H”. (3) LINHL, MINHL, RINHR and MINHR bits should be changed to “1” after PMVCM bit is changed to “1”. (4) When LINHL, MINHL, RINHR or MINHR bit is changed to “1”, the LIN, RIN or MIN pin is biased to 0.475 x AVDD. (5) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at the VCOM pin is 2.2μF) after LINHL, MINHL, RINHR and MINHR bits are changed to “1”. (6) Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to VCOM/2 is tr = 70k x C(typ). When C=1μF, tr = 70ms(typ). (7) Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to VCOM/2 is tf = 60k x C(typ). When C=1μF, tf = 60ms(typ). PMHPL and PMHPR bits should be changed to “0” after the HPL and HPR pins settle to VSS1. After that, the LINHL, MINHL, RINHR and MINHR bits should be changed to “0”. MS0684-E-02 2008/12 - 37 - [AK4372] 4) LIN/RIN/MIN → Lineout Power Supply (1) >150ns PDN pin (2) >0s PMVCM bit Don’t care LINL, MINL, RINR, MINR bits (3) >0s PMLO bit (5) >2ms (5) >2ms (Hi-Z) (4) LIN/RIN/MIN pins LMUTE, ATTS3-0 bits LOUT/ROUT pins (Hi-Z) 0FH(0dB) 10H(MUTE) (6) (6) (Hi-Z) (6) (Hi-Z) Figure 31. Power-up/down sequence of LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 and Lineout (1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or more. The PDN pin should be set to “H” at least 150ns after power is supplied. MCKI, BICK and LRCK can be stopped when DAC is not used. (2) PMVCM bit should be changed to “1” after the PDN pin is set to “H”. (3) LINL, MINL, RINR and MINR bits should be changed to “1” after PMVCM bit is changed to “1”. (4) When LINL, MINL, RINR or MINR bit is changed to “1”, the LIN, RIN or MIN pin is biased to 0.475 x AVDD. (5) PMLO bit should be changed to “1” at least 2ms (in case external capacitance at VCOM pin is 2.2μF) after LINL, MINL, RINR and MINR bits are changed to “1”. (6) When the PMLO bit is changed, pop noise is output from the LOUT/ROUT pins. MS0684-E-02 2008/12 - 38 - [AK4372] Power-Up/Down Sequence (PLL Slave mode) 1) DAC → HP-Amp Power Supply (12) (1) >150ns PDN pin PMVCM, PMPLL, PMDAC, MCKO bits Don’t care (2) >0s Don’t care (3) Don’t care Don’t care MCKI pin Unstable (4) ~20ms Don’t care (5) Unstable (4) ~20ms MCKO pin Unstable Don’t care (5) BICK, LRCK pins Unstable Unstable DAC Internal State PD Don’t care Normal Operation PD Unstable Normal Operation PD Don’t care SDTI pin DALHL, DARHR bits Unstable (6) >0s PMHPL, PMHPR bits (6) >0s (7) >2ms (7) >2ms MUTEN bit ATTL7-0 ATTR7-0 bits 00H(MUTE) FFH(0dB) FFH(0dB) 00H(MUTE) (9) (8) 00H(MUTE) (10) (11) (10) (11) (10) GD (11) 1061/fs (10) (11) (8) (9) HPL/R pin Figure 32. Power-up/down sequence of DAC and HP-amp (Don’t care: except Hi-Z) (1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or more. The PDN pin should be set to “H” at least 150ns after power is supplied. (2) PMVCM, PMPLL, PMDAC and MCKO bits should be changed to “1” after the PDN pin goes “H”. (3) The PLL operation is executed when the system clock is input to the MCKI pin. (4) The PLL lock time is referred to Table 4. After the PLL is locked, the MCKO pin outputs the master clock. (5) The clocks (BICK, LRCK) generated by MCKO are needed to operate the DAC. When the PMDAC bit = “0”, these clocks can be stopped. The headphone-amp can operate without these clocks. (6) DALHL and DARHR bits should be changed to “1” after the PLL is locked. (7) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin is 2.2μF) after the DALHL and DARHR bits are changed to “1”. (8) Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to VCOM/2 is tr = 70k x C(typ). When C=1μF, tr = 70ms(typ). (9) Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to VCOM/2 is tf = 60k x C(typ). When C=1μF, tf = 60ms(typ). PMHPL and PMHPR bits should be changed to “0” after HPL and HPR pins go to HVSS. After that, the DALHL/DARHR bits should be changed to “0”. (10) Analog output corresponding to the digital input has a group delay (GD) of 22/fs(=499μs@fs=44.1kHz). (11) The ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz). (12) The power supply should be switched off after the headphone-amp is powered down (HPL/R pins become “L”). When AVDD and DVDD are supplied separately, DVDD should be powered-down at the same time or after AVDD. MS0684-E-02 2008/12 - 39 - [AK4372] 2) DAC → Lineout Power Supply (1) >150ns PDN pin (2)>0s PMVCM, PMPLL, PMDAC, MCKO bits Don’t care Don’t care Don’t care (3) MCKI pin (4) ~20ms Unstable Unstable (4) ~20ms MCKO pin Don’t care Unstable (5) Unstable (5) BICK, LRCK pins Unstable DAC Internal State Unstable PD Normal Operation Don’t care PD Normal Operation Unstable Unstable SDTI pin DALL, DARR bits (6) >0s (6) >0s (7) >0s (7) >0s PMLO bit ATTL/R7-0 bits LMUTE, ATTS3-0 bits 00H(MUTE) FFH(0dB) 10H(MUTE) FFH(0dB) 0FH(0dB) (9) GD (10) 1061/fs LOUT/ROUT pins 00H(MUTE) (8) (9) (10) (9) (Hi-Z) (10) (8) (8) (Hi-Z) Figure 33. Power-up/down sequence of DAC and LOUT/ROUT (Don’t care: except Hi-Z) (1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or more. The PDN pin should be set to “H” at least 150ns after power is supplied. (2) PMVCM, PMPLL, PMDAC and MCKO bits should be changed to “1” after the PDN pin goes “H”. (3) The PLL operation is executed when the system clock is input to the MCKI pin. (4) The PLL lock time is referred to Table 4. After the PLL is locked, the MCKO pin outputs the master clock. (5) The clocks (BICK, LRCK) generated by MCKO are needed to operate the DAC. When the PMDAC bit = “0”, these clocks can be stopped. The LOUT/ROUT buffer can operate without these clocks. (6) DALL and DARR bits should be changed to “1” after the PLL is locked (7) PMLO bit is changed to “1”. (8) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins. (9) Analog output corresponding to the digital input has group delay (GD) of 22fs(=499μs@fs=44.1kHz). (10) The ATS bit sets the transition time of the digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz). MS0684-E-02 2008/12 - 40 - [AK4372] 3) LIN/RIN/MIN → HP-Amp Power Supply (1) >150ns PDN pin (2) >0s PMVCM bit Don’t care LINHL, MINHL, RINHR, MINHR bits (3) >0s PMHPL/R bits (5) >2ms (5) >2ms MUTEN bit (Hi-Z) (4) LIN/RIN/MIN pins (Hi-Z) (7) (6) (6) HPL/R pins Figure 34. Power-up/down sequence of LIN/RIN/MIN and HP-Amp (1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or more. The PDN pin should be set to “H” at least 150ns after power is supplied. MCKI, BICK and LRCK can be stopped when DAC is not used. (2) PMVCM bit should be changed to “1” after the PDN pin is set to “H”. (3) LINHL, MINHL, RINHR and MINHR bits should be changed to “1” after PMVCM bit is changed to “1”. (4) When LINHL, MINHL, RINHR or MINHR bit is changed to “1”, the LIN, RIN or MIN pin is biased to 0.475 x AVDD. (5) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at the VCOM pin is 2.2μF) after LINHL, MINHL, RINHR and MINHR bits are changed to “1”. (6) Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to VCOM/2 is tr = 70k x C(typ). When C=1μF, tr = 70ms(typ). (7) Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to VCOM/2 is tf = 60k x C(typ). When C=1μF, tf = 60ms(typ). PMHPL and PMHPR bits should be changed to “0” after the HPL and HPR pins settle to VSS1. After that, the LINHL, MINHL, RINHR and MINHR bits should be changed to “0”. MS0684-E-02 2008/12 - 41 - [AK4372] 4) LIN/RIN/MIN → Lineout Power Supply (1) >150ns PDN pin (2) >0s PMVCM bit Don’t care LINL, MINL, RINR, MINR bits (3) >0s PMLO bit (5) >2ms (5) >2ms (Hi-Z) (4) LIN/RIN/MIN pins LMUTE, ATTS3-0 bits LOUT/ROUT pins (Hi-Z) 0FH(0dB) 10H(MUTE) (6) (6) (Hi-Z) (6) (Hi-Z) Figure 35. Power-up/down sequence of LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 and Lineout (1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or more. The PDN pin should be set to “H” at least 150ns after power is supplied. MCKI, BICK and LRCK can be stopped when DAC is not used. (2) PMVCM bit should be changed to “1” after the PDN pin is set to “H”. (3) LINL, MINL, RINR and MINR bits should be changed to “1” after PMVCM bit is changed to “1”. (4) When LINL, MINL, RINR or MINR bit is changed to “1”, the LIN, RIN or MIN pin is biased to 0.475 x AVDD. (5) PMLO bit should be changed to “1” at least 2ms (in case external capacitance at the VCOM pin is 2.2μF) after LINL, MINL, RINR and MINR bits are changed to “1”. (6) When the PMLO bit is changed, pop noise is output from the LOUT/ROUT pins. MS0684-E-02 2008/12 - 42 - [AK4372] Power-Up/Down Sequence (PLL Master mode) 1) DAC → HP-Amp Power Supply (11) (1) >150ns PDN pin Don’t care (2) >0 M/S, PMVCM, PMPLL, PMDAC, MCKO bits Don’t care (3) Don’t care Don’t care MCKI pin Unstable (4) ~20ms Unstable (4) ~20ms MCKO pin Don’t care “L” Don’t care Unstable BICK, LRCK pins Unstable DAC Internal State Unstable PD Don’t care Normal Operation PD Unstable Normal Operation PD Don’t care SDTI pin DALHL, DARHR bits Unstable (5) >0 PMHPL, PMHPR bits (5) >0 (6) >2ms (6) >2ms MUTEN bit ATTL7-0 ATTR7-0 bits 00H(MUTE) FFH(0dB) (9) GD (10) 1061/fs (9) FFH(0dB) 00H(MUTE) (9) (10) (9) (10) (8) (7) 00H(MUTE) (10) (7) (8) HPL/R pin Figure 36 Power-up/down sequence of DAC and HP-amp (Don’t care: except Hi-Z) (1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or more. The PDN pin should be set to “H” at least 150ns after power is supplied. (2) PMVCM, PMPLL, PMDAC, MCKO and M/S bits should be changed to “1” after the PDN pin goes “H”. (3) The PLL operation is executed when the system clock is input to the MCKI pin. (4) The PLL lock time is referred to Table 4. After the PLL is locked, each clock is output from BICK, LRCK and MCKO pins. (5) DALHL and DARHR bits should be changed to “1” after the PLL is locked. (6) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at VCOM pin is 2.2μF) after the DALHL and DARHR bits are changed to “1”. (7) Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to VCOM/2 is tr = 70k x C(typ). When C=1μF, tr = 70ms(typ). (8) Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to VCOM/2 is tf = 60k x C(typ). When C=1μF, tf = 60ms(typ). PMHPL and PMHPR bits should be changed to “0” after HPL and HPR pins go to HVSS. After that, the DALHL/DARHR bits should be changed to “0”. (9) Analog output corresponding to the digital input has group delay (GD) of 22/fs(=499μs@fs=44.1kHz). (10) The ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz). (11) The power supply should be switched off after the headphone-amp is powered down (HPL/R pins become “L”). When AVDD and DVDD are supplied separately, DVDD should be powered-down at the same time or after AVDD. MS0684-E-02 2008/12 - 43 - [AK4372] 2) DAC → Lineout Power Supply (1) >150ns PDN pin (2) >0 M/S, PMVCM, PMPLL, PMDAC, MCKO bits Don’t care Don’t care Don’t care (3) MCKI pin (4) ~20ms Unstable Unstable (4) ~20ms MCKO pin Don’t care “L” Unstable BICK, LRCK pins Unstable DAC Internal State Unstable PD Normal Operation Don’t care PD Unstable Normal Operation Unstable SDTI pin DALL, DARR bits (5) >0 (5) >0 (6) >0 (6) >0 PMLO bit ATTL/R7-0 bits LMUTE, ATTS3-0 bits FFH(0dB) 00H(MUTE) 10H(MUTE) FFH(0dB) 0FH(0dB) (8) GD (9) 1061/fs LOUT/ROUT pins 00H(MUTE) (7) (8) (9) (8) (7) (8) (Hi-Z) (9) (Hi-Z) Figure 37. Power-up/down sequence of DAC and LOUT/ROUT(Don’t care: except Hi-Z) (1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or more. The PDN pin should be set to “H” at least 150ns after power is supplied. (2) PMVCM, PMPLL, PMDAC, MCKO and M/S bits should be changed to “1” after the PDN pin goes “H”. (3) The PLL operation is executed when the system clock is input to the MCKI pin. (4) The PLL lock time is referred to Table 4. After the PLL is locked, each clock is output from BICK, LRCK and MCKO pins. (5) DALL and DARR bits should be changed to “1” after the PLL is locked. (6) PMLO bit is changed to “1”. (7) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins. (8) Analog output corresponding to the digital input has group delay (GD) of 22fs(=499μs@fs=44.1kHz). (9) The ATS bit sets the transition time of the digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz). MS0684-E-02 2008/12 - 44 - [AK4372] 3) LIN/RIN/MIN → HP-Amp Power Supply (1) >150ns PDN pin (2) >0s PMVCM bit Don’t care LINHL, MINHL, RINHR, MINHR bits (3) >0s PMHPL/R bits (5) >2ms (5) >2ms MUTEN bit (Hi-Z) (4) LIN/RIN/MIN pins (Hi-Z) (7) (6) (6) HPL/R pins Figure 38. Power-up/down sequence of LIN/RIN/MIN and HP-Amp (1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or more. The PDN pin should be set to “H” at least 150ns after power is supplied. MCKI, BICK and LRCK can be stopped when DAC is not used. (2) PMVCM bit should be changed to “1” after the PDN pin is set to “H”. (3) LINHL, MINHL, RINHR and MINHR bits should be changed to “1” after PMVCM bit is changed to “1”. (4) When LINHL, MINHL, RINHR or MINHR bit is changed to “1”, the LIN, RIN or MIN pin is biased to 0.475 x AVDD. (5) PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case external capacitance at the VCOM pin is 2.2μF) after LINHL, MINHL, RINHR and MINHR bits are changed to “1”. (6) Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to VCOM/2 is tr = 70k x C(typ). When C=1μF, tr = 70ms(typ). (7) Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to VCOM/2 is tf = 60k x C(typ). When C=1μF, tf = 60ms(typ). PMHPL and PMHPR bits should be changed to “0” after the HPL and HPR pins settle to VSS1. After that, the LINHL, MINHL, RINHR and MINHR bits should be changed to “0”. MS0684-E-02 2008/12 - 45 - [AK4372] 4) LIN/RIN/MIN → Lineout Power Supply (1) >150ns PDN pin (2) >0s PMVCM bit Don’t care LINL, MINL, RINR, MINR bits (3) >0s PMLO bit (5) >2ms (5) >2ms (Hi-Z) (4) LIN/RIN/MIN pins LMUTE, ATTS3-0 bits LOUT/ROUT pins (Hi-Z) 0FH(0dB) 10H(MUTE) (6) (6) (Hi-Z) (6) (Hi-Z) Figure 39. Power-up/down sequence of LIN1/RIN1/LIN2/RIN2/LIN3/RIN3 and Lineout (1) When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or more. The PDN pin should be set to “H” at least 150ns after power is supplied. MCKI, BICK and LRCK can be stopped when DAC is not used. (2) PMVCM bit should be changed to “1” after the PDN pin is set to “H”. (3) LINL, MINL, RINR and MINR bits should be changed to “1” after PMVCM bit is changed to “1”. (4) When LINL, MINL, RINR or MINR bit is changed to “1”, the LIN, RIN or MIN pin is biased to 0.475 x AVDD. (5) PMLO bit should be changed to “1” at least 2ms (in case external capacitance at the VCOM pin is 2.2μF) after LINL, MINL, RINR and MINR bits are changed to “1”. (6) When the PMLO bit is changed, pop noise is output from the LOUT/ROUT pins. MS0684-E-02 2008/12 - 46 - [AK4372] ■ Serial Control Interface (1) 3-wire Serial Control Mode (I2C pin = “L”) Internal registers may be written to via the 3-wire μP interface pins (CSN, CCLK and CDTI). The data on this interface consists of the Chip address (2-bits, Fixed to “01”), Read/Write (1-bit, Fixed to “1”, Write only), Register address (MSB first, 5-bits) and Control data (MSB first, 8-bits). Address and data are clocked in on the rising edge of CCLK. For write operations, the data is latched after a low-to-high transition of the 16th CCLK. CSN should be set to “H” once after 16 CCLKs for each address. The clock speed of CCLK is 5MHz(max). The value of the internal registers is initialized at the PDN pin = “L”. CSN 0 CCLK Clock, “H” or “L” CDTI “H” or “L” 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Clock, “H” or “L” C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: R/W: A4-A0: D7-D0: “H” or “L” Chip Address (Fixed to “01”) READ/WRITE (Fixed to “1”, Write only) Register Address Control Data Figure 40. 3-wire Serial Control I/F Timing MS0684-E-02 2008/12 - 47 - [AK4372] (2) I2C-bus Control Mode (I2C pin = “H”) The AK4372 supports fast-mode I2C-bus (max: 400kHz, Version 1.0). (2)-1. WRITE Operations Figure 41 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates START condition (Figure 47). After the START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W). The most significant six bits of the slave address are fixed as “001000”. The next bit is CAD0 (device address bit). This bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) sets this device address bit (Figure 42). If the slave address matches that of the AK4372, the AK4372 generates an acknowledgement and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 48). A R/W bit value of “1” indicates that the read operation is to be executed. A “0” indicates that the write operation is to be executed. The second byte consists of the control register address of the AK4372. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 43). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 44). The AK4372 generates an acknowledgement after each byte is received. A data transfer is always terminated by STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is HIGH defines STOP condition (Figure 47). The AK4372 can perform more than one byte write operation per sequence. After receiving the third byte the AK4372 generates an acknowledgement and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 13H prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW(Figure 49) except for the START and STOP conditions. S T A R T SDA S T O P R/W="0" Slave S Address Sub Address(n) Data(n) A C K A C K Data(n+1) A C K Data(n+x) A C K A C K P A C K Figure 41. Data Transfer Sequence at the I2C-Bus Mode 0 0 1 0 0 0 CAD0 R/W A2 A1 A0 D2 D1 D0 (Those CAD0 should match with CAD0 pin) Figure 42. The First Byte 0 0 0 A4 A3 Figure 43. The Second Byte D7 D6 D5 D4 D3 Figure 44. Byte Structure after the second byte MS0684-E-02 2008/12 - 48 - [AK4372] (2)-2. READ Operations Set the R/W bit = “1” for the READ operation of the AK4372. After a transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the writing cycle after receiving the first data word. After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 13H prior to generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. The AK4372 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ. (2)-2-1. CURRENT ADDRESS READ The AK4372 contains an internal address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) were to address “n”, the next CURRENT READ operation would access data from the address “n+1”. After receiving the slave address with R/W bit “1”, the AK4372 generates an acknowledge, transmits 1-byte of data to the address set by the internal address counter, and increments the internal address counter by 1. If the master does not generate an acknowledgement but instead generates stop condition, the AK4372 ceases transmission. S T A R T SDA S T O P R/W="1" Slave S Address Data(n) A C K Data(n+1) A C K Data(n+2) A C K Data(n+x) A C K A C K P A C K Figure 45. CURRENT ADDRESS READ (2)-2-2. RANDOM ADDRESS READ The random read operation allows the master to access any memory location at random. Prior to issuing the slave address with the R/W bit “1”, the master must first perform a “dummy” write operation. The master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master immediately reissues the start request and the slave address with the R/W bit “1”. The AK4372 then generates an acknowledgement, 1 byte of data and increments the internal address counter by 1. If the master does not generate an acknowledgement but instead generates stop condition, the AK4372 ceases transmission. S T A R T SDA S T A R T R/W="0" Slave S Address Slave S Address Sub Address(n) A C K A C K S T O P R/W="1" Data(n) A C K Data(n+1) A C K Data(n+x) A C K A C K P A C K Figure 46. RANDOM ADDRESS READ MS0684-E-02 2008/12 - 49 - [AK4372] SDA SCL S P start condition stop condition Figure 47. START and STOP Conditions DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 48. Acknowledge on the I2C-Bus SDA SCL data line stable; data valid change of data allowed Figure 49. Bit Transfer on the I2C-Bus MS0684-E-02 2008/12 - 50 - [AK4372] ■ Register Map Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H Register Name Power Management 0 PLL Control Clock Control Mode Control 0 Mode Control 1 DAC Lch ATT DAC Rch ATT Headphone Out Select 0 Lineout Select 0 Lineout ATT Reserved Reserved Reserved Headphone Out Select 1 Headphone ATT Lineout Select 1 Mono Mixing Differential Select Reserved Reserved D7 D6 D5 D4 D3 D2 D1 D0 0 FS3 PLL4 0 ATS ATTL7 ATTR7 HPG1 0 0 0 0 0 0 0 0 0 0 0 0 PMPLL FS2 0 MONO1 DATTC ATTL6 ATTR6 HPG0 LOG 0 0 0 0 0 HPZ 0 0 0 0 0 PMLO FS1 M/S MONO0 LMUTE ATTL5 ATTR5 MINHR MINR 0 0 0 0 0 HMUTE 0 0 0 0 0 MUTEN FS0 PMHPR PLL3 BF LRP BST1 ATTL3 ATTR3 RINHR RINR ATTS3 0 0 0 0 ATTH3 0 0 0 0 0 PMHPL PLL2 PS0 DIF2 BST0 ATTL2 ATTR2 LINHL LINL ATTS2 0 0 0 0 ATTH2 0 0 0 0 0 PMDAC PLL1 PS1 DIF1 DEM1 ATTL1 ATTR1 DARHR DARR ATTS1 0 0 0 LINHR ATTH1 LINR LM LDIFH 0 0 PMVCM MCKAC BCKP SMUTE ATTL4 ATTR4 MINHL MINL 0 0 0 0 0 ATTH4 0 0 0 0 1 PLL0 MCKO DIF0 DEM0 ATTL0 ATTR0 DALHL DALL ATTS0 0 0 0 RINHL ATTH0 RINL LHM LDIF 0 0 All registers inhibit writing at PDN pin = “L”. PDN pin = “L” resets the registers to their default values. For addresses from 14H to 1FH, data must not be written. Unused bits indicated by “0” must contain a “0” value. Unused bits indicated by “1” must contain a “1” value. MS0684-E-02 2008/12 - 51 - [AK4372] ■ Register Definitions Addr 00H Register Name Power Management 0 R/W Default D7 0 RD 0 D6 PMPLL R/W 0 D5 PMLO R/W 0 D4 D3 D2 D1 D0 MUTEN PMHPR PMHPL PMDAC PMVCM R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 PMVCM: Power Management for VCOM Block 0: Power OFF (default) 1: Power ON PMDAC: Power Management for DAC Blocks 0: Power OFF (default) 1: Power ON When the PMDAC bit is changed from “0” to “1”, the DAC is powered-up to the current register values (ATT value, sampling rate, etc). PMHPL: Power Management for the left channel of the headphone-amp 0: Power OFF (default). The HPL pin settles to VSS1(0V). 1: Power ON PMHPR: Power Management for the right channel of the headphone-amp 0: Power OFF (default). The HPR pin settles to VSS1(0V). 1: Power ON MUTEN: Headphone Amp Mute Control 0: Mute (default). The HPL and HPR pins settles to VSS1(0V). 1: Normal operation. HPL and HPR pins go to 0.475 x AVDD. PMLO: Power Management for Stereo Output 0: Power OFF (default) LOUT/ROUT pins change to Hi-Z. 1: Power ON PMPLL: Power Management for PLL 0: Power OFF: EXT mode (default) 1: Power ON: PLL mode Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDN pin is “L”, all blocks are powered-down regardless of setting of this address. In this case, register is initialized to the default value. When PMVCM, PMDAC, PMHPL, PMHPR, PMLO, PMMO, PMPLL and MCKO bits are “0”, all blocks are powered-down. The register values remain unchanged. Power supply current is 20μA(typ) in this case. For fully shut down (typ. 1μA), the PDN pin should be “L”. MS0684-E-02 2008/12 - 52 - [AK4372] Addr 01H Register Name PLL Control R/W Default D7 FS3 R/W 1 D6 FS2 R/W 0 D5 FS1 R/W 0 D4 FS0 R/W 0 D3 PLL3 R/W 0 D4 D3 BF R/W 0 D2 R/W 0 D1 PLL1 R/W 0 D0 PLL0 R/W 0 D2 PS0 R/W 0 D1 PS1 R/W 0 D0 MCKO R/W 0 PLL2 FS3-0: Select Sampling Frequency PLL mode: Table 5 EXT mode: Table 11 PLL4-0: Select PLL Reference Clock PLL mode: Table 3 EXT mode: PLL4-0 bits are disabled (PLL4 bit is D7 bit of 02H.) Addr 02H Register Name Clock Control R/W Default D7 PLL4 R/W 0 D6 0 RD 0 D5 M/S R/W 0 MCKAC R/W 0 MCKO: Control of MCKO signal 0: Disable (default) 1: Enable PS1-0: MCKO Frequency PLL mode: Table 9 EXT mode: Table 12 BF: BICK Period setting in Master Mode. In slave mode, this bit is ignored. 0: 32fs (default) 1: 64fs MCKAC: MCKI Input Mode Select 0: CMOS input (default) 1: AC coupling input M/S: Select Master/Slave Mode 0: Slave mode (default) 1: Master mode PLL4-0: Select PLL Reference Clock PLL3-0 bits are D3-0 bits of 01H. MS0684-E-02 2008/12 - 53 - [AK4372] Addr 03H Register Name Mode Control 0 R/W Default D7 0 RD 0 D6 D5 MONO1 MONO0 R/W 0 R/W 0 D4 BCKP R/W 0 D3 LRP R/W 0 D2 DIF2 R/W 0 D1 DIF1 R/W 1 D0 DIF0 R/W 0 D3 BST1 R/W 0 D2 BST0 R/W 0 D1 DEM1 R/W 0 D0 DEM0 R/W 1 DIF2-0: Audio Data Interface Format Select (Table 16) Default: “010” (Mode 2) LRP: LRCK Polarity Select in Slave Mode 0: Normal (default) 1: Invert BCKP: BICK Polarity Select in Slave Mode 0: Normal (default) 1: Invert MONO1-0: Digital Mixing Select (Table 21) Default: “00” (LR) Addr 04H Register Name Mode Control 1 R/W Default D7 ATS R/W 0 D6 D5 D4 DATTC LMUTE SMUTE R/W 0 R/W 1 R/W 0 DEM1-0: De-emphasis Filter Frequency Select (Table 19 ) Default: “01” (OFF) BST1-0: Low Frequency Boost Function Select (Table 20) Default: “00” (OFF) SMUTE: Soft Mute Control 0: Normal operation (default) 1: DAC outputs soft-muted LMUTE: Mute control for LOUT/ROUT (Table 26) 0: Normal operation. ATTS3-0 bits control attenuation value. 1: Mute. ATTS3-0 bits are ignored. (default) DATTC: DAC Digital Attenuator Control Mode Select 0: Independent (default) 1: Dependent At DATTC bit = “1”, ATTL7-0 bits control both channel attenuation levels, while register values of ATTL7-0 bits are not written to the ATTR7-0 bits. At DATTC bit = “0”, the ATTL7-0 bits control the left channel level and the ATTR7-0 bits control the right channel level. ATS: Digital attenuator transition time setting (Table 18) 0: 1061/fs (default) 1: 7424/fs MS0684-E-02 2008/12 - 54 - [AK4372] Addr 05H 06H Register Name DAC Lch ATT DAC Rch ATT R/W Default D7 ATTL7 ATTR7 R/W 0 D6 ATTL6 ATTR6 R/W 0 D5 ATTL5 ATTR5 R/W 0 D4 ATTL4 ATTR4 R/W 0 D3 ATTL3 ATTR3 R/W 0 D2 ATTL2 ATTR2 R/W 0 D1 ATTL1 ATTR1 R/W 0 D0 ATTL0 ATTR0 R/W 0 ATTL7-0: Setting of the attenuation value of output signal from DACL (Table 17) ATTR7-0: Setting of the attenuation value of output signal from DACR (Table 17) Default: “00H” (MUTE) Addr 07H Register Name Headphone Out Select 0 R/W Default D7 HPG1 R/W 0 D6 HPG0 R/W 0 D5 D4 D3 D2 D1 D0 MINHR MINHL RINHR LINHL DARHR DALHL R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 DALHL: DAC left channel output signal is added to the left channel of the headphone-amp. 0: OFF (default) 1: ON DARHR: DAC right channel output signal is added to the right channel of the headphone-amp. 0: OFF (default) 1: ON LINHL: Input signal to LIN pin is added to the left channel of the headphone-amp. 0: OFF (default) 1: ON RINHR: Input signal to RIN pin is added to the right channel of the headphone-amp. 0: OFF (default) 1: ON MINHL: Input signal to MIN pin is added to the left channel of the headphone-amp. 0: OFF (default) 1: ON MINHR: Input signal to MIN pin is added to the right channel of the headphone-amp. 0: OFF (default) 1: ON HPG1-0: DAC Æ HPL/R Gain (Table 25) Default: “00”: +0.95dB MS0684-E-02 2008/12 - 55 - [AK4372] Addr 08H Register Name Lineout Select 0 R/W Default D7 0 RD 0 D6 LOG R/W 0 D5 D4 D3 D2 D1 D0 MINR MINL RINR LINL DARR DALL R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 D3 D2 D1 D0 ATTS3 ATTS2 ATTS1 ATTS0 R/W 0 R/W 0 R/W 0 R/W 0 DALL: DAC left channel output is added to the LOUT buffer amp. 0: OFF (default) 1: ON DARR: DAC right channel output is added to the ROUT buffer amp. 0: OFF (default) 1: ON LINL: Input signal to the LIN pin is added to the LOUT buffer amp. 0: OFF (default) 1: ON RINR: Input signal to the RIN pin is added to the ROUT buffer amp. 0: OFF (default) 1: ON MINL: Input signal to the MIN pin is added to the LOUT buffer amp. 0: OFF (default) 1: ON MINR: Input signal to the MIN pin is added to the ROUT buffer amp. 0: OFF (default) 1: ON LOG: DAC Æ LOUT/ROUT Gain 0: 0dB (default) 1: +6dB Addr 09H Register Name Lineout ATT R/W Default D7 0 RD 0 D6 0 RD 0 D5 0 RD 0 D4 0 RD 0 ATTS3-0: Analog volume control for LOUT/ROUT (Table 26) Default: LMUTE bit = “1”, ATTS3-0 bits = “0000” (MUTE) Setting of ATTS3-0 bits is enabled at LMUTE bit is “0”. MS0684-E-02 2008/12 - 56 - [AK4372] Addr 0DH Register Name Headphone Out Select R/W Default D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 LINHR RINHL RD 0 RD 0 RD 0 RD 0 RD 0 RD 0 R/W 0 R/W 0 D3 D2 ATTH2 R/W 0 D1 D0 ATTH0 R/W 0 RINHL: RIN signal is added to the left channel of the Headphone-Amp 0: OFF (default) 1: ON LINHR: LIN signal is added to the right channel of the Headphone-Amp 0: OFF (default) 1: ON Addr 0EH Register Name Headphone ATT R/W Default D7 D6 D5 0 HPZ HMUTE RD 0 R/W 0 R/W 0 D4 ATTH4 R/W 0 ATTH3 R/W 0 ATTH1 R/W 0 ATTH4-0: Setting of the attenuation value of output signal from Headphone (Table 25) Default: HMUTE bit = “0”, ATTH4-0 bits = “00” (0dB) Setting of ATTH4-0 bits is enabled at HMUTE bit is “0”. HMUTE: Mute control for Headphone-Amp (Table 25) 0: Normal operation. ATTH4-0 bits control attenuation value. (default) 1: Mute. ATTH4-0 bits are ignored. HPZ: Headphone-Amp Pull-down Control 0: Shorted to GND (default) 1: Pulled-down by 200kΩ (typ) MS0684-E-02 2008/12 - 57 - [AK4372] Addr 0FH Register Name Lineout Select R/W Default D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 LINR RINL RD 0 RD 0 RD 0 RD 0 RD 0 RD 0 R/W 0 R/W 0 D5 D4 D3 D2 D1 D0 0 0 0 0 LM LHM RD 0 RD 0 RD 0 RD 0 R/W 0 R/W 0 D4 0 RD 0 D3 0 RD 0 D2 0 RD 0 D1 D0 LDIFH LDIF R/W 0 R/W 0 RINL: RIN signal is added to the left channel of the Lineout 0: OFF (default) 1: ON LINR: LIN signal is added to the right channel of the Lineout 0: OFF (default) 1: ON Addr 10H Register Name Mono Mixing R/W Default D7 0 RD 0 D6 0 RD 0 LHM: LIN/RIN signal is added to Headphone-Amp as (L+R)/2. 0: OFF (default) 1: ON LM: LIN/RIN signal is added to LOUT/ROUT as (L+R)/2. 0: OFF (default) 1: ON Addr 11H Register Name Differential Select R/W Default D7 0 RD 0 D6 0 RD 0 D5 0 RD 0 LDIF: Switch control from IN+/IN− pin to LOUT/ROUT. 0: OFF (default) 1: ON When LDIF bit = “1”, the LIN1 and RIN1 pins become IN+ and IN− pins respectively. LDIFH: Switch control from the IN+/IN− pin to Headphone-Amp. (Setting of LIDFH bit is enable at LDIF bit = “1”) 0: OFF (default) 1: ON MS0684-E-02 2008/12 - 58 - [AK4372] SYSTEM DESIGN Figure 50 shows the system connection diagram. The evaluation board [AKD4372] demonstrates the optimum layout, power supply arrangements and measurement results. Digital Ground Analog Ground µP Cp Rp VSS2 CCLK CSN PDN MUTET VCOC MCKO CDTI LOUT ROUT AK4372ECB 1000p Audio MCKI Controller LRCK DVDD SPK-Amp + I2C Top View 1µ VCOM 2.2µ Analog Supply 10 + SDATA BICK LIN HPR AVDD RIN MIN HPL VSS1 + 220µ 10µ 1.6∼3.6V 0.1µ 0.1µ + 220µ 16Ω 16Ω Headphone Notes: - VSS1 and VSS2 of the AK4372 should be distributed separately from the ground of external controllers. - All digital input pins (I2C, SDA/CDTI, SCL/CCLK, CAD0/CSN, SDATA, LRCK, BICK, MCKI, PDN) must not be left floating. - When the AK4372 is in EXT mode (PMPLL bit = “0”), a resistor and capacitor for the VCOC pin are not needed. - When the AK4372 is in PLL mode (PMPLL bit = “1”), a resistor and capacitor for the VCOC pin are shown in Table 4 - When the AK4372 is used in master mode, LRCK and BICK pins are floating before the M/S bit is changed to “1”. Therefore, a 100kΩ pull-up resistor should be connected to the LRCK and BICK pins of the AK4372. - When DVDD is supplied from AVDD via 10Ω series resistor, the capacitor larger than 0.1μF should not be connected between DVDD and the ground. Figure 50. Typical Connection Diagram (In case of AC coupling to MCKI) MS0684-E-02 2008/12 - 59 - [AK4372] AVDD AK4372 110k LIN1 pin HP-Amp LIN1HL bit 100k Note: If the path is OFF and the signal is input to the input pin, the input pin should be biased to a voltage equivalent to VCOM voltage (= 0.475 x AVDD) externally. Figure 51. External Bias Circuit Example for Line Input Pin 1. Grounding and Power Supply Decoupling The AK4372 requires careful attention to power supply and grounding arrangements. AVDD is usually supplied from the analog power supply in the system and DVDD is supplied from AVDD via a 10Ω resistor. Alternatively if AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or more. When the AK4372 is powered-down, DVDD should be powered-down at the same time or later than AVDD. VSS1 and VSS2 must be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as close to the AK4372 as possible, with the small value ceramic capacitors being the nearest. 2. Voltage Reference The input voltage to AVDD sets the analog output range. Usually a 0.1μF ceramic capacitor is connected between AVDD and VSS1. VCOM is a signal ground of this chip (0.475 x AVDD). The electrolytic capacitor around 2.2μF attached between VCOM anVSS1 eliminates the effects of high frequency noise, too. No load current may be drawn from the VCOM pin. All signals, especially clock, should be kept away from AVDD and VCOM in order to avoid unwanted coupling into the AK4372. 3. Analog Outputs The analog outputs are single-ended outputs, and 0.48 x AVDD Vpp(typ)@−3dBFS for headphone-amp, 0.61xAVDD Vpp(typ) @0dBFS for LOUT/ROUT centered on the VCOM voltage. The input data format is 2’s compliment. The output voltage is a positive full scale for 7FFFFFH(@24bit) and negative full scale for 800000H(@24bit). The ideal output is VCOM voltage for 000000H(@24bit). DC offsets on the analog outputs should be eliminated by AC coupling since the analog outputs have a DC offset equal to VCOM plus a few mV. MS0684-E-02 2008/12 - 60 - [AK4372] PACKAGE 24pin CSP (Unit: mm) Top View Bottom View 2.50 ± 0.05 A 0.4 5 5 4 4 4372 3 2.50 ± 0.05 3 XXXX 2 B 2 1 1 A B C D E E D C B A φ 0.25 ± 0.05 φ 0.05 M S AB 0.20 ± 0.05 0.65 S 0.08 S ■ Material & Lead finish Package material: Epoxy resin, Halogen (bromine and chlorine) free Solder ball material: SnAgCu MS0684-E-02 2008/12 - 61 - [AK4372] MARKING 4372 XXXX 1 A XXXX: Date code (4 digit) REVISION HISTORY Date (YY/MM/DD) 07/10/30 08/12/04 08/12/19 Revision 00 01 02 Reason First Edition Product Addition Specification Change Description Addition Page Contents 1, 3, 4, 6 AK4372VCB was added. Ambient Temperature AK4372ECB: −30 ∼ 85°C AK4372VCB: −40 ∼ 85°C 53 Package material was changed. 39-42 Power-Up/Down Sequence (PLL Slave mode, PLL Master mode) were added. IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. MS0684-E-02 2008/12 - 62 -