SN75LVDS81 FLATLINK TRANSMITTER SLLS258B – NOVEMBER 1996 – REVISED MAY 1999 D D D D D D D D D D D D D DGG PACKAGE (TOP VIEW) 28:4 Data Channel Compression at up to 227.5 Million Bytes per Second Throughput Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI 28 Data Channels and Clock In Low-Voltage TTL 4 Data Channels and Clock-Out Low-Voltage Differential Operates From a Single 3.3-V Supply With 250 mW (Typ) 5-V Tolerant Data Inputs Falling Clock-Edge-Triggered Inputs Packaged in Thin Shrink Small-Outline Package With 20-Mil Terminal Pitch Consumes Less Than 1 mW When Disabled Wide Phase-Lock Input Frequency Range . . . 31 MHz to 68 MHz No External Components Required for PLL Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard Improved Replacement for the National DS90C581 VCC D5 D6 D7 GND D8 D9 D10 VCC D11 D12 D13 GND D14 D15 D16 NC D17 D18 D19 GND D20 D21 D22 D23 VCC D24 D25 description 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 D4 D3 D2 GND D1 D0 D27 LVDSGND Y0M Y0P Y1M Y1P LVDSVCC LVDSGND Y2M Y2P CLKOUTM CLKOUTP Y3M Y3P LVDSGND PLLGND PLLVCC PLLGND SHTDN CLKIN D26 GND 31 The SN75LVDS81 FlatLink transmitter contains 27 30 four 7-bit parallel-load serial-out shift registers, a 28 29 7× clock synthesizer, and five low-voltage differential-signaling (LVDS) line drivers in a NC – Not Connected single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82. The SN75LVDS81 can also be used in 21-bit links with the SN75LVDS86 receiver. When transmitting, data bits D0 through D27 are each loaded into registers upon the falling edge of the input clock signal (CLKIN) The frequency of CLKIN is multiplied seven times (7×) and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN. The SN75LVDS81 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user. The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low-level on SHTDN clears all internal registers to a low level. The SN75LVDS81 is characterized for operation over free-air temperature ranges of 0_C to 70_C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FlatLink is a registered trademark of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN75LVDS81 FLATLINK TRANSMITTER SLLS258B – NOVEMBER 1996 – REVISED MAY 1999 functional block diagram D0, D1, D2, D3, D4, D6, D7 Parallel-Load 7-Bit Shift Register 7 A,B, ...G SHIFT/LOAD Y0P Y0M CLK D8, D9, D12, D13, D14, D15, D18 Parallel-Load 7-Bit Shift Register 7 Y1P A,B, ...G SHIFT/LOAD Y1M CLK D5, D10, D11, D16, D17, D23, D27 7 Y2P A,B, ...G SHIFT/LOAD 7 Input Bus D19, D20, D21, D22, D24, D25, D26 Parallel-Load 7-Bit Shift Register Y2M CLK Parallel-Load 7-Bit Shift Register Y3P A,B, ...G SHIFT/LOAD Y3M CLK Control Logic SHTDN 7× Clock/PLL CLKIN 7×CLK CLKOUTP CLK CLKOUTM CLKINH 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS81 FLATLINK TRANSMITTER D0 CLKIN CLKOUT SLLS258B – NOVEMBER 1996 – REVISED MAY 1999 ÉÉÉ ÉÉÉ ÉÉ ÉÉ ÉÉ ÉÉÉ ÉÉÉ ÉÉ ÉÉ ÉÉ ÇÇ ÇÇ ÇÇ Previous Cycle ÇÇ ÇÇ ÇÇ Next Cycle Current Cycle Y0 D0–1 D7 D6 D4 D3 D2 D1 D0 D7+1 Y1 D8–1 D18 D15 D14 D13 D12 D9 D8 D18+1 Y2 D19–1 D26 D25 D24 D22 D21 D20 D19 D26+1 Y3 D27–1 D23 D17 D16 D11 D10 D5 D27 D23+1 Figure 1. SN75LVDS81 Load and Shift Timing Sequences equivalent input and output schematic diagrams VCC VCC 5Ω D or SHTDN YnP or YnM 10 kΩ 50 Ω 7V 7V 300 kΩ INPUT OUTPUT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN75LVDS81 FLATLINK TRANSMITTER SLLS258B – NOVEMBER 1996 – REVISED MAY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V Output voltage range, VO (all terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.5 V Input voltage range, VI (all terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see Dissipation Rating Table Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65_C to 150_C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260_C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to the GND terminals. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR‡ ABOVE TA = 25°C TA = 70°C POWER RATING DGG 1377 mW 11.0 mW/°C 882 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. recommended operating conditions MIN Supply voltage, VCC 3 High-level input voltage, VIH 2 NOM 3.3 MAX UNIT 3.6 V V Low-level input voltage, VIL 0.8 V Differential load impedance, ZL 90 132 Ω Operating free-air temperature, TA 0 70 °C timing requirements MAX UNIT 14.7 MIN NOM 32.4 ns 0.4 tc 0.6 tc ns 5 ns tc tw Input clock cycle time tt tsu Input signal transition time Data setup time, D0 – D27 before CLKIN↓ See Figure 2 3 ns th Data hold time, D0 – D27 valid after CLKIN↓ See Figure 2 1.5 ns 4 High-level input clock pulse width duration POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS81 FLATLINK TRANSMITTER SLLS258B – NOVEMBER 1996 – REVISED MAY 1999 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VIT |VOD| Input threshold voltage ∆|VOD| Change in the steady-state differential output voltage magnitude between opposite binary states VOC(SS) VOC(PP) Steady-state common-mode output voltage IIH IIL High-level input current TYP† MAX UNIT 454 mV 50 mV 1.4 Differential steady-state output voltage magnitude Peak-to-peak common-mode output voltage RL = 100 Ω, Ω See Figure 3 See Figure 3 247 1.125 Low-level input current Short circuit output current Short-circuit IOZ High-impedance state output current V 150 mV 20 µA ±10 µA VO(Yn) = 0 VOD = 0 ±24 mA ±12 mA VO = 0 to VCC Disabled, All inputs at GND ±10 µA 280 µA 72 80 mA 85 110 mA Enabled, RL = 100 Ω, Gray-scale pattern (see Figure 4), VCC = 3.3 V, tc = 15.28 ns Enabled, RL = 100 Ω, Worst-case pattern (see Figure 5), tc = 15.28 ns Quiescent supply current V 1.375 VIH = VCC VIL = 0 IOS ICC MIN CI Input capacitance † All typical values are at VCC = 3.3 V, TA = 25°C. POST OFFICE BOX 655303 3 • DALLAS, TEXAS 75265 pF 5 SN75LVDS81 FLATLINK TRANSMITTER SLLS258B – NOVEMBER 1996 – REVISED MAY 1999 switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† – 0.2 0 MAX t0 Delay time, CLKOUT↑ after Yn valid (serial bit position 0) t1 Delay time, CLKOUT↑ after Yn valid (serial bit position 1) 1t 7 c * 0.2 1t 7 c t2 Delay time, CLKOUT↑ after Yn valid (serial bit position 2) 2t 7 c * 0.2 2t 7 c ) 0.2 2 t ) 0.2 7 c t3 Delay time, CLKOUT↑ after Yn valid (serial bit position 3) 3t 7 c 3t 7 c t4 Delay time, CLKOUT↑ after Yn valid (serial bit position 4) * 0.2 4 t * 0.2 7 c t5 Delay time, CLKOUT↑ after Yn valid (serial bit position 5) 5t 7 c 5t 7 c t6 Delay time, CLKOUT↑ after Yn valid (serial bit position 6) * 0.2 6 t * 0.2 7 c tsk(o) Output skew, t n t7 Delay time, CLKIN↓ to CLKOUT↓ 15 38 ns (± 0 2%) tc = 15.38 0.2%), |Input clock jitter| < 50 ps‡, See Figure 6 * n7 tc ∆ tc(o) O tp t clock jitter§ ( ) Output 3t 7 c 4t 7 c 6t 7 c 0.2 1t 7 c ) 0.2 4 t ) 0.2 7 c 5 t ) 0.2 7 c 6t 7 c – 0.2 UNIT ns ns ns ns ns ns ) 0.2 ns 0.2 ns tc = 15.38 ns (± 0.2%), |Input clock jitter| < 50 ps‡, See Figure 6 4.2 ns tc = 15.38 ± 0.75 sin (2π500E3t) + 0.05 ns, See Figure 7 ± 80 ps tc = 15.38 ± 0.75 sin (2π3E6t) + 0.05 ns, See Figure 7 ± 300 ps 0.57 tc ns tw High-level output clock pulse duration tt Differential output transition time (tr or tf) See Figure 3 ten Enable time, SHTDN↑ to phase lock (Yn valid) See Figure 8 1 ms tdis Disable time, SHTDN↓ to off state (CLKOUT low) See Figure 9 250 ns 260 700 † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ |Input clock jitter| is the magnitude of the change in the input clock period. § Output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15 000 cycles. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1500 ps SN75LVDS81 FLATLINK TRANSMITTER SLLS258B – NOVEMBER 1996 – REVISED MAY 1999 PARAMETER MEASUREMENT INFORMATION ÉÉÉÉÉ ÉÉÉÉÉ Dn tsu th ÉÉÉÉ ÉÉÉÉ CLKIN NOTE A: All input timing is defined at 1.4 V on an input signal with a 10%-to-90% rise or fall time of less than 5 ns. Figure 2. Setup and Hold Time Waveforms 49.9 Ω ± 1% (2 Places) YP VOD VOC YM CL = 10 pF Max (2 Places) NOTE A: The lumped instrumentation capacitance for any single-ended voltage measurement is less than or equal to 10 pF. When making measurements at YP or YM, the complementary output will be similarly loaded. a. SCHEMATIC 100% 80% VOD(H) 0V VOD(L) 20% 0% tf tr VOC(PP) VOC(SS) VOC(SS) 0V b. WAVEFORMS Figure 3. Test Load and Voltage Waveforms for LVDS Outputs POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN75LVDS81 FLATLINK TRANSMITTER SLLS258B – NOVEMBER 1996 – REVISED MAY 1999 PARAMETER MEASUREMENT INFORMATION CLKIN D0, 8, 16 D1, 9, 17 D2, 10, 18 D3, 11, 19 D4–7, 12–15, 20–23 D24–27 NOTE A: The 16-grayscale test-pattern test device power consumption for a typical display pattern. Figure 4. 16-Grayscale Test-Pattern Waveforms tc CLKIN EVEN Dn ODD Dn NOTE A: The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs. Figure 5. Worst-Case Test-Pattern Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS81 FLATLINK TRANSMITTER SLLS258B – NOVEMBER 1996 – REVISED MAY 1999 PARAMETER MEASUREMENT INFORMATION t7 CLKIN ÇÇ ÉÉÉ ÇÇ ÇÇ ÉÉÉ ÇÇ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ CLKOUT t0 Yn t1 t2 t3 t4 t5 t6 ≈ 2.5 V CLKIN 1.4 V VOD(H) CLKOUT or Yn 0 V ± 0.01 V ≈ 0.5 V VOD(L) t7 t0– t6 Figure 6. SN75LVDS81 Timing Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN75LVDS81 FLATLINK TRANSMITTER SLLS258B – NOVEMBER 1996 – REVISED MAY 1999 PARAMETER MEASUREMENT INFORMATION Reference + ∑ Device Under Test VCO + Modulation V(t) = A sin (2 π f(mod) t) HP8656B Signal Generator 0.1 MHz – 990 MHz HP8665A Synthesized Signal Generator 0.1 MHz – 4200 MHz Device Under Test OUTPUT RF Output CLKIN CLKOUT DTS2070C Digital Time Scope Input Modulation Input Figure 7. Output Clock Jitter Testing CLKIN Dn ten SHTDN ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Yn Invalid Figure 8. Enable Time Waveforms CLKIN tdis SHTDN CLKOUT Figure 9. Disable Time Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Valid SN75LVDS81 FLATLINK TRANSMITTER SLLS258B – NOVEMBER 1996 – REVISED MAY 1999 TYPICAL CHARACTERISTICS AVERAGE SUPPLY CURRENT vs CLOCK FREQUENCY I CC – Average Supply Current – mA 80 VCC = 3.6 V 70 60 VCC = 3.3 V 50 VCC = 3 V 40 Greyscale Data Pattern RL = 100 Ω TA = 25°C 30 30 40 50 60 70 fclk – Clock Frequency – MHz Figure 10 ZERO-TO-PEAK OUTPUT JITTER vs MODULATION FREQUENCY 300 Input jitter = 750 sin (6.28 f(mod) t) ps VCC = 3.3 V TA = 25°C Zero-to-Peak Output Jitter – ps 250 200 150 100 50 0 0 0.5 1 1.5 2 2.5 3 f(mod) – Modulation Frequency – MHz Figure 11 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN75LVDS81 FLATLINK TRANSMITTER SLLS258B – NOVEMBER 1996 – REVISED MAY 1999 APPLICATION INFORMATION Host Graphic Controller 12-BIT RED0 RED1 RED2 RED3 RSVD RSVD NA NA GREEN0 GREEN1 GREEN2 GREEN3 RSVD RSVD NA NA BLUE0 BLUE1 BLUE2 BLUE3 RSVD RSVD NA NA H_SYNC V_SYNC ENABLE NA CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 NA NA GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 NA NA BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 NA NA H_SYNC V_SYNC ENABLE NA CLOCK 24-BIT RED0 RED1 RED2 RED3 RED4 RED5 RED6 RED7 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 GREEN6 GREEN7 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 BLUE6 BLUE7 H_SYNC V_SYNC ENABLE RSVD CLOCK Cable Flat Panel Display SN75LVDS81 51 52 54 55 56 3 50 2 4 6 7 11 12 14 8 10 15 19 20 22 23 24 16 18 27 28 30 25 31 D0 D1 D2 D3 D4 D6 D27 D5 D7 D8 D9 D12 D13 D14 D10 D11 D15 D18 D19 D20 D21 D22 D16 D17 D24 D25 D26 D23 CLKIN SN75LVDS82 Y0M 48 9 A0M 100 Ω Y0P Y1M 47 10 46 11 A0P A1M 100 Ω Y1P Y2M 45 12 42 15 A1P A2M 100 Ω Y2P Y3M 41 16 38 19 A2P A3M 100 Ω Y3P CLKOUTM 37 20 40 40 A3P CLKINM 100 Ω CLKOUTP 39 39 CLKINP NOTES: A. The five 100-Ω terminating resistors are recommended to be 0603 types. B. NA – not applicable, these unused inputs should be left open. Figure 12. 24-Bit Color Host To 24-Bit LCD Panel Display Application 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS81 FLATLINK TRANSMITTER SLLS258B – NOVEMBER 1996 – REVISED MAY 1999 APPLICATION INFORMATION Host Graphic Controller 12-BIT RED0 RED1 RED2 RED3 RSVD RSVD NA NA GREEN0 GREEN1 GREEN2 GREEN3 RSVD RSVD NA NA BLUE0 BLUE1 BLUE2 BLUE3 RSVD RSVD NA NA H_SYNC V_SYNC ENABLE NA CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 NA NA GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 NA NA BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 NA NA H_SYNC V_SYNC ENABLE NA CLOCK 24-BIT RED0 RED1 RED2 RED3 RED4 RED5 RED6 RED7 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 GREEN6 GREEN7 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 BLUE6 BLUE7 H_SYNC V_SYNC ENABLE RSVD CLOCK Cable Flat Panel Display SN75LVDS81 51 52 54 55 56 3 50 2 4 6 7 11 12 14 8 10 15 19 20 22 23 24 16 18 27 28 30 25 31 D0 D1 D2 D3 D4 D6 D27 D5 D7 D8 D9 D12 D13 D14 D10 D11 D15 D18 D19 D20 D21 D22 D16 D17 D24 D25 D26 D23 CLKIN SN75LVDS86 Y0M 48 9 A0M 100 Ω Y0P Y1M 47 10 46 11 A0P A1M 100 Ω Y1P Y2M 45 12 42 15 A1P A2M 100 Ω Y2P Y3M Y3P CLKOUTM 41 16 A2P 38 37 40 40 CLKINM 100 Ω CLKOUTP 39 39 CLKINP NOTES: A. The four 100-Ω terminating resistors are recommended to be 0603 types. B. NA – not applicable, these unused inputs should be left open. Figure 13. 24-Bit Color Host To 18-Bit LCD Panel Display Application POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SN75LVDS81 FLATLINK TRANSMITTER SLLS258B – NOVEMBER 1996 – REVISED MAY 1999 MECHANICAL INFORMATION DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PIN SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. 14 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated