SN75DP139 www.ti.com...................................................................................................................................................................................................... SLLS977 – APRIL 2009 DisplayPort to TMDS Translator FEATURES APPLICATIONS • • 1 • • • • • • • DisplayPort Physical Layer Input Port to TMDS Physical Layer Output Port Integrated TMDS level translator with Receiver Equalization Supports Data Rates up to 2.5Gbps Integrated I2C Logic Block for DVI/HDMI Connector Recognition Integrated Active I2C Buffer Enhanced ESD: 10KV on all pins Enhanced Commercial Temperature Range: 0°C to 85°C 48 Pin 7 × 7 QFN Package Personal Computer Market – DP/TMDS Dongle – Desktop PC – Notebook PC – Docking Station – Standalone Video Card DESCRIPTION The SN75DP139 is a Dual-Mode DisplayPort input to Transition-Minimized Differential Signaling (TMDS) output. The TMDS output has a built in level translator supporting Digital Video Interface (DVI) 1.0 and High Definition Multimedia Interface (HDMI) 1.3 standards. The SN75DP139 is specified up to a maximum data rate of 2.5Gbps, supporting resolutions greater then 1920x1200 or HDTV 12 bit color depth at 1080p (progressive scan). An integrated Active I2C buffer isolates the capacitive loading of the source system from that of the sink and interconnecting cable. This isolation improves overall signal integrity of the system and allows for considerable design margin within the source system for DVI / HDMI compliance testing. A logic block was designed into the SN75DP139 in order to assist with TMDS connector identification. Through the use of the I2C_EN pin, this logic block can be enabled to indicate the translated port is an HDMI port; therefore legally supporting HDMI content. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated SN75DP139 SLLS977 – APRIL 2009...................................................................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. TYPICAL APPLICATION GPU DP++ SN75DP139 TMDS TMDS Buffer Computer Notebook Docking Station DVI or HDMI Compliant Monitor or HDTV Dongle GPU - Graphics Processing Unit DP++ - Dual-Mode DisplayPort TMDS - Transition-Minimized Differential Signaling DVI - Digital Visual Interface HDMI - High Definition Multimedia Interface 2 GPU Graphics Processing Unit DP++ Dual-Mode DisplayPort TMDS Transition-Minimized Differential Signaling DVI Digital Visual Interface HDMI High Definition Multimedia Interface Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 SN75DP139 www.ti.com...................................................................................................................................................................................................... SLLS977 – APRIL 2009 GND OE_N VCC GND SCL_SINK SDA_SINK HPD_SINK GND DDC_EN VCC HPDINV OVS GND DATA FLOW BLOCK DIAGRAM Vsadj, SRC, OE_N GND SN75DP139 IN_D1- OUT_D1IN_D1+ VCC OUT_D1+ I 2C Slave I2C_EN OVS, DDC_EN VCC IN_D2- OUT_D2- IN_D2+ OUT_D2+ GND 130kohm GND IN_D3- OUT_D3- IN_D3+ OUT_D3+ VCC VCC HPDINV IN_D4- OUT_D4- IN_D4+ GND VCC NC SCL_SOURCE SDA_SOURCE HPD_SOURCE Vsadj GND I2C_EN SRC VCC GND OUT_D4+ Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 3 SN75DP139 SLLS977 – APRIL 2009...................................................................................................................................................................................................... www.ti.com DEVICE INFORMATION 4 OE_N VCC GND SCL_SINK SDA_SINK HPD_SINK GND DDC_EN IN_D1+ 39 VCC 40 IN_D2- 41 IN_D2+ 42 GND 43 IN_D3- 44 IN_D3+ 45 VCC 46 IN_D4- 47 IN_D4+ 48 1 2 3 4 5 6 7 8 9 10 11 12 VCC SRC I2C_EN GND Vsadj HPD_SOURCE SDA_SOURCE SCL_SOURCE 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 GND IN_D1- VCC OVS GND GND HPDINV RGZ PACKAGE Submit Documentation Feedback OUT_D1- 22 OUT_D1+ 21 VCC 20 OUT_D2- 19 OUT_D2+ 18 GND 17 OUT_D3- 16 OUT_D3+ 15 VCC 14 OUT_D4- 13 OUT_D4+ GND VCC NC DP139 TOP VIEW GND Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 SN75DP139 www.ti.com...................................................................................................................................................................................................... SLLS977 – APRIL 2009 PIN FUNCTIONS PIN SIGNAL I/O DESCRIPTION NO. MAIN LINK INPUT PINS IN_D1 38, 39 I DisplayPort Main Link Channel 0 Differential Input IN_D2 41, 42 I DisplayPort Main Link Channel 1 Differential Input IN_D3 44, 45 I DisplayPort Main Link Channel 2 Differential Input IN_D4 47, 48 I DisplayPort Main Link Channel 3 Differential Input MAIN LINK PORT B OUTPUT PINS OUT_D1 23, 22 O TMDS Data 2 Differential Output OUT_D2 20, 19 O TMDS Data 1 Differential Output OUT_D3 17, 16 O TMDS Data 0 Differential Output OUT_D4 14, 13 O TMDS Data Clock Differential Output HPD_SOURCE 7 O Hot Plug Detect Output HPD_SINK 30 I Hot Plug Detect Input SDA_SOURCE, SCL_SOURCE 8, 9 I/O Source Side Bidirectional DisplayPort Auxiliary Data Line 29, 28 I/O TMDS Port Bidirectional DDC Data Lines OE_N 25 I NC 10 OVS 35 I DDC I2C buffer offset select DDC_EN 32 I Enables or Disables the DDC I2C buffer HPDINV 34 I HPD_SOURCE Logic and Level Select VSadj 6 I TMDS Compliant Voltage Swing Control SRC 3 I TMDS outputs rise and fall time select I2C_EN 4 I Internal I2C register enable, used for HDMI / DVI connector differentiation HOT PLUG DETECT PINS AUXILIARY DATA PINS SDA_SINK, SCL_SINK CONTROL PINS Output Enable and power saving function for High Speed Differential level shifter path. No Connect SUPPLY AND GROUND PINS VCC 2, 11, 15, 21, 26, 33, 40, 46 GND 1, 5, 12, 18, 24, 27, 31, 36, 37, 43 3.3V Supply Ground Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 5 SN75DP139 SLLS977 – APRIL 2009...................................................................................................................................................................................................... www.ti.com Input/Output Equivalent Circuits VTERM VCC VTERM 50 W 50 W – + Figure 1. DisplayPort Input Stage Y Z 10 mA Figure 2. TMDS Output Stage 6 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 SN75DP139 www.ti.com...................................................................................................................................................................................................... SLLS977 – APRIL 2009 OE_N 2 I C_EN HPDINV SRC OVS DDC_EN HPD_SINK Figure 3. HPD and Control Input Stage VCC HPD_OUT Figure 4. HPD Output Stage SCL SDA AUX+/– 400 W VOL Figure 5. I2C Input and Output Stage Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 7 SN75DP139 SLLS977 – APRIL 2009...................................................................................................................................................................................................... www.ti.com Table 1. Control Pin Lookup Table SIGNAL OE_N I2C_EN VSadj HPDINV SRC OVS DDC_EN (1) 8 LEVEL (1) STATE DESCRIPTION H Power Saving Mode Main Link is disabled. IN_Dx termination = 50 Ω with common mode voltage set to 0V. OUT_Dx outputs = high impedance L Normal Mode IN_Dx termination = 50 Ω OUT_Dx outputs = active H HDMI L DVI 4.02 kΩ ±5% Output Voltage Swing Contol Driver output voltage swing precision control to aid with system compliance H HPD Inversion HPD_SOURCE VOH =0.9V (typical) and HPD logic is inverted L HPD non-inversion HPD_SOURCE VOH =3.2V (typical) and HPD logic is non-inverted H Edge Rate: Slowest SRC helps to slow down the rise and fall time. SRC =High adds ~60ps to the rise and fall time of the TMDS differential output signals in addition to the I2C_EN pin selection L Edge Rate: Slow SRC helps to slow down the rise and fall time. SRC =Low adds ~30ps to the rise and fall time of the TMDS differential output signals in addition to the I2C_EN pin selection Hi-Z Edge Rate Leaving the SRC pin High Z, will keep the default rise and fall time of the TMDS differential output signals as selected by the I2C_EN pin. It is recommended that an external resistor-divider (less than 100 kΩ) is used so that voltage on this pin = VCC/2, if Hi-Z logic level is intended on this pin. H Offset 1 DDC source side VOL and VIL offset range 1 L Offset 2 DDC source side VOL and VIL offset range 2 Hi-Z Offset 3 DDC source side VOL and VIL offset range 3 It is recommended that an external resistor-divider (less than 100 kΩ) is used so that voltage on this pin = VCC/2, if Hi-Z logic level is intended on this pin. H DDC Buffer enabled DDC Buffer is enabled L DDC buffer disabled DDC Buffer is disabled The Internal I2C register is active and readable when the TMDS port is selected indicating that the connector being used is HDMI. This mode selects the fastest rise and fall time for the TMDS differential output signals The Internal I2C register is disabled and not readable when the TMDS port is selected indicating that the connector being used is DVI. This mode selects a slower rise and fall time for the TMDS differential output signals See DVI Application Section. (H) Logic High; (L) Logic Low; (Z) High Z Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 SN75DP139 www.ti.com...................................................................................................................................................................................................... SLLS977 – APRIL 2009 ORDERING INFORMATION (1) (1) PART NUMBER PART MARKING PACKAGE SN75DP139RGZR DP139 48-pin QFN Reel (large) SN75DP139RGZT DP139 48-pin QFN Reel (small) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) Supply voltage range (2) (1) VALUE UNIT –0.3 to 3.6 V 1.56 V –0.3 to 4 V HPD I/O (HPD_SOURCE, HPD_SINK) –0.3 to 5.5 V Auxiliary I/O (SCL_SOURCE, SDA_SOURCE, SCL_SINK, SDA_SINK) –0.3 to 5.5 V Control I/O (OE_N, DDC_EN, SRC, OVS, HPDINV) –0.3 to 5.5 V VCC Main Link Input (IN_Dx) differential voltage TMDS Outputs (OUT_Dx) Voltage range Human body model Electrostatic discharge (3) ±10000 V Charged-device model (4) ±1500 V Machine model (5) ±200 V Continuous power dissipation (1) (2) (3) (4) (5) See Dissipation Rating Table Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-B Tested in accordance with JEDEC Standard 22, Test Method C101-A Tested in accordance with JEDEC Standard 22, Test Method A115-A DISSIPATION RATINGS PACKAGE 48-pin QFN (RGZ) (1) PCB JEDEC STANDARD TA ≤ 25°C DERATING FACTOR (1) ABOVE TA = 25°C Low-K 1426.8 mW 14.28 mW/°C 570 mW High-K 3125 mW 31.25 mW/°C 1250 mW TA = 85°C POWER RATING This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 9 SN75DP139 SLLS977 – APRIL 2009...................................................................................................................................................................................................... www.ti.com THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX (1) TYP UNIT RθJB Junction-to-board thermal resistance 9 °C/W RθJC Junction-to-case thermal resistance 22 °C/W PD1 Device power dissipation (2) HDMI Mode: OE_N = 0V, DDC_EN = 5V, VCC = 3.6V, ML: VID_PP = 1200mV, 2.5Gbps TMDS pattern AUX: VI = 3.3V, 100 kHz PRBS HPD: HPD_SINK = 5V, I2C_EN = 5V, SRC = Hi-Z PD2 Device power dissipation (2) DVI Mode: OE_N = 0V, DDC_EN = 5V, VCC = 3.6V, ML: VID_PP = 1200mV, 2.5Gbps TMDS pattern AUX: VI = 3.3V, 100 kHz PRBS HPD: HPD_SINK= 5V, I2C_EN = 0V, SRC = Hi-Z PSD1 Device power dissipation under low power with HPDINV = LOW OE_N = 5V, DDC_EN = 0V, HPDINV = 0V, HPD_SINK = 0V 18 54 µW PSD2 Device power dissipation under low power with HPDINV =HIGH OE_N = 5V, DDC_EN = 0V, HPDINV = 5V 1.7 3 mW PSD3 Device power dissipation under low power with DDC enabled with HPDINV = HIGH OE_N = 5V, DDC_EN = 5V, HPDINV = 5V 16.5 29 mW PSD4 Device power dissipation under low power with DDC enabled with HPDINV = LOW OE_N = 5V, DDC_EN = 5V, HPDINV = 0V 15 26 mW (1) (2) 270+146 (2) 396+146 (2) mW 214+146 (2) 306+146 (2) mW The maximum rating is simulated under 3.6V VCC unless otherwise noted. Power dissipation is the sum of the power consumption from the VCC pins, plus the 146 mW of power from the AVCC (HDMI/DVI Receiver Termination Supply). RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX 3.3 UNIT VCC Supply Voltage 3 3.6 V TA Operating free-air temperature 0 85 °C MAIN LINK DIFFERENTIAL INPUT PINS VID_PP Peak-to-peak AC input differential voltage 0.15 1.2 V dR Data rate 0.25 2.5 Gbps trise fall time Input Signal Rise and Fall time (20%-80%) VPRE Pre-emphasis on the Input Signal at IN_Dx pins 75 ps 0 0 0 db 3 3.3 3.6 V 2.5 Gbps TMDS DIFFERENTIAL OUTPUT PINS AVCC TMDS output termination voltage dR Data rate RT Termination resistance RVsadj TMDS output swing voltage bias resistor (1) 0.25 45 50 3.65 4.02 55 Ω kΩ AUXILIARY AND I2C PINS VI Input voltage dR(I2C) I2C data rate (1) 10 0 5.5 V 100 kHz RVsadj resistor controls the SN75DP139 Driver output voltage swing and thus helps in meeting system compliance. It is recommended that RVsadj resistor should be above the MIN value as indicated in the RECOMMENDED OPERATING CONDITIONS table, however for NOM and MAX value, Figure 24 could be used as reference. It is important to note that system level losses, AVCC and RT variation affect RVsadj resistor selection. Worse case variation on system level losses, AVCC, RT could make RVsadj resistor value of 4.02 kΩ ±5% result in non-compliant TMDS output voltage swing. In such cases Figure 24 could be used as reference. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 SN75DP139 www.ti.com...................................................................................................................................................................................................... SLLS977 – APRIL 2009 RECOMMENDED OPERATING CONDITIONS (continued) over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT HPD_SINK, HPDINV, OE_N, DDC_EN, I2C_EN VIH High-level input voltage 2 5.5 V VIL Low-level input voltage 0 0.8 V VIH_SRC_OVS High-level input voltage 3 5.5 V VIL_SRC_OVS Low-level input voltage 0 0.5 V SRC, OVS DEVICE POWER The SN75DP139 is designed to operate off of one supply voltage VCC. The SN75DP139 offers features to enable or disable different functionality based on the status of the output enable (OE_N) and DDC Enable (DDC_EN) inputs. • • • OE_N affects only the High Speed Differential channels (Main Link/TMDS link). OE_N has no influence on the HPD_SINK input, HPD_SOURCE output, or the DDC buffer. DDC_EN affects only the DDC channel. The DDC_EN should never change state during the I2C operation. Disabling DDC_EN during a bus operation will hang the bus, while enabling the DDC_EN during bus traffic will corrupt the I2C bus operation. DDC_EN should only be toggled while the bus is idle. TMDS output edge rate control has impact on the SN75DP139 Active power. See Figure 20. TMDS output edge rate can be controlled by SRC pin. Slower output Edge Rate Setting helps in reducing the Active power consumption. HPD_SINK HPDINV OE_N DDC_EN IN_Dx OUT_Dx DDC HPD_SOURCE MODE Input = H or L L L L 50 Ω termination active Enabled Highimpedance Output = non inverted, follows HPD_SINK Active Input = H or L L L H 50 Ω termination active Enabled enabled Output = non inverted, follows HPD_SINK Active Input = H or L L H L 50 Ω termination active: Terminations connected to common Mode Voltage = 0V. Highimpedance Highimpedance Output = non inverted, follows HPD_SINK Low Power Input = H or L L H H 50 Ω termination active: Terminations connected to common Mode Voltage = 0V. Highimpedance enabled Output = non inverted, follows HPD_SINK Low Power with DDC channel enabled Input = H or L H L L 50 Ω termination active Enabled Highimpedance Output = inverted, follows HPD_SINK Active Input = H or L H L H 50 Ω termination active Enabled enabled Output = inverted, follows HPD_SINK Active Input = H or L H H L 50 Ω termination active: Terminations connected to common Mode Voltage = 0V. Highimpedance Highimpedance Output = inverted, follows HPD_SINK Low Power Input = H or L H H H 50 Ω termination active: Terminations connected to common Mode Voltage = 0V. Highimpedance enabled Output = inverted, follows HPD_SINK Low Power with DDC channel enabled L = LOW, H = HIGH Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 11 SN75DP139 SLLS977 – APRIL 2009...................................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) TYP MAX UNIT ICC1 Supply current (HDMI Mode) PARAMETER HDMI Mode: OE_N = 0V, DDC_EN = 5V, VCC = 3.6V, ML: VID_PP = 1200mV, 2.5Gbps TMDS pattern AUX: VI = 3.3V, 100 kHz PRBS HPD: HPD_SINK = 5V, I2C_EN = 5V, SRC = Hi-Z 82 110 mA ICC2 Supply Current (DVI Mode) DVI Mode: OE_N = 0V, DDC_EN = 5V, VCC = 3.6V, ML: VID_PP = 1200mV, 2.5Gbps TMDS pattern AUX: VI = 3.3V, 100 kHz PRBS HPD: HPD_SINK= 5V, I2C_EN = 0V, SRC = Hi-Z 65 85 mA ISD1 Shutdown current with HPDINV = LOW OE_N = 5V, DDC_EN = 0V, HPDINV = 0V, HPD_SINK = 0V 5.5 15 µA ISD2 Shutdown current with HPDINV = HIGH OE_N = 5V, DDC_EN = 0V, HPDINV = 5V 0.5 0.8 mA ISD3 Shutdown current with DDC enabled with HPDINV = HIGH 5 8 mA OE_N = 5V, DDC_EN = 5V, HPDINV = 5V Shutdown current with DDC enabled with HPDINV = LOW 4.5 7.2 mA OE_N = 5V, DDC_EN = 5V, HPDINV = 0V ISD4 TEST CONDITIONS MIN Hot Plug Detect The SN75DP139 has a built in level shifter for the HPD outputs. The output voltage level of the HPD pin is defined by the voltage level of the VCC pin. The HPD input or HPD_SINK side has 130kohm of pull down resistor integrated. The logic of the HPD_SOURCE output always follows the logic state of the HPD_SINK input based on the HPDINV pin logic, regardless of whether the device is in Active or Low Power Mode ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH3.3 High-level output voltage IOH = –100 µA, VCC = 3.3 V ±10%, HPDINV = LOW 2.8 3.6 V VOH1.1 High-level output voltage IOH = –100 µA, VCC = 3.3 V ±10%, HPDINV = HIGH 0.8 1.1 V VOL Low-level output voltage IOH = 100 µA 0 0.1 V IIH High-level input current VIH = 2.0 V, VCC = 3.6 V –30 30 µA IIL Low-level input current VIL = 0.8 V, VCC = 3.6 V –30 30 µA RINTHPD Input pull down on HPD_SINK (HPD Input) kΩ 110 130 160 MIN TYP MAX SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER tPD(HPD) 12 Propagation delay TEST CONDITIONS VCC = 3.6 V Submit Documentation Feedback 2 30 UNIT ns Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 SN75DP139 www.ti.com...................................................................................................................................................................................................... SLLS977 – APRIL 2009 1.1 V HPD Input/HPD_sink Dp139 HPD Output/HPD_source DP139 130 kW 100 kW 130 kW 10 kW HPD Input/HPD_sink 100 kW HPD Output/HPD_source 130 kW Pull down resistor on the sink side is integrated 130 kW Pull down resistor is integrated Figure 6. HPD Test Circuit (HPDINV = LOW) Figure 7. HPD Test Circuit (VOH =1.1), HPDINV=HIGH 5V HPD_SINK 5V HPD_SINK 50% 50% 0V 0V tPD(HPD) VCC tPD(HPD) HPD_SOURCE 1.1 V 50% 50% HPD_SOURCE 0V 0V Figure 8. HPD Timing Diagram (HPDINV = LOW) Figure 9. HPD Timing Diagram (HPDINV = HIGH) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 13 SN75DP139 SLLS977 – APRIL 2009...................................................................................................................................................................................................... www.ti.com AUX / I2C pins The SN75DP139 utilizes an active I2C repeater. The repeater is designed to isolate the parasitic effects of the system in order to aid with system level compliance. In addition to the I2C repeater, the SN75DP139 also supports the connector detection I2C register. This register is enabled via the I2C_EN pin. When active an internal memory register is readable via the AUX_I2C I/O. The functionality of this register block is described in the APPLICATION INFORMATION section. ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IL Low input current VCC = 3.6 V, VI = 0 V –10 10 µA Ilkg(AUX) Input leakage current AUX_I2C pins (SCL_SOURCE, SDA_SOURCE) VCC = 3.6V, VI = 3.6 V –10 10 µA CIO(AUX) Input/Output capacitance AUX_I2C pins (SCL_SOURCE, SDA_SOURCE) DC bias = 1.65 V, AC = 2.1Vp-p, f = 100 kHz 15 pF VIH(AUX) High-level input voltage AUX_I2C pins (SCL_SOURCE, SDA_SOURCE) 1.6 5.5 V VIL1(AUX) Low-level input voltage AUX_I2C pins (SCL_SOURCE, SDA_SOURCE) OVS = HIGH –0.2 0.4 V VOL1(AUX) Low-level output voltage AUX_I2C pins (SCL_SOURCE, SDA_SOURCE) IO = 3 mA, OVS = HIGH 0.6 0.7 V VIL2(AUX) Low-level input voltage AUX_I2C pins (SCL_SOURCE, SDA_SOURCE) OVS = Hi-Z –0.2 0.4 V VOL2(AUX) Low-level output voltage AUX_I2C pins (SCL_SOURCE, SDA_SOURCE) IO = 3 mA, OVS = Hi-Z 0.5 0.6 V VIL3(AUX) Low-level input voltage AUX_I2C pins (SCL_SOURCE, SDA_SOURCE) OVS = Low –0.2 0.3 V VOL3(AUX) Low-level output voltage AUX_I2C pins (SCL_SOURCE, SDA_SOURCE) IO = 3 mA, OVS = Low 0.4 0.5 V Ilkg(I2C) Input leakage current I2C SDA/SCL pins VCC = 3.6 V, VI = 4.95 V (SCL_SINK, SDA_SINK) –10 10 µA CIO(I2C) Input/Output capacitance I2C SDA/SCL pins DC bias = 2.5 V, AC = 3.5Vp-p, f = 100 (SCL_SINK, kHz SDA_SINK) 15 pF VIH(I2C) High-level input voltage I2C SDA/SCL pins (SCL_SINK, SDA_SINK) 2.1 5.5 V VIL(I2C) Low-level input voltage I2C SDA/SCL pins (SCL_SINK, SDA_SINK) –0.2 1.5 V VOL(I2C) Low-level output voltage I2C SDA/SCL pins IO = 3mA (SCL_SINK, SDA_SINK) 0.2 V 14 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 SN75DP139 www.ti.com...................................................................................................................................................................................................... SLLS977 – APRIL 2009 SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) MAX UNIT tPLH1 Propagation delay time, low to high PARAMETER Source to Sink TEST CONDITIONS MIN 204 TYP 600 ns tPHL1 Propagation delay time, high to low Source to Sink 35 200 ns tPLH2 Propagation delay time, low to high Sink to Source 80 251 ns tPHL2 Propagation delay time, high to low Sink to Source 35 200 ns tf1 Output signal fall time Sink Side 20 72 ns tf2 Output signal fall time Source Side 20 fSCL SCL clock frequency for internal register Source Side tW(L) Clock LOW period for I2C register Source Side tW(H) Clock HIGH period for internal register tSU1 Internal register setup time, SDA to SCL th(1) 72 ns 100 kHz 4.7 µs Source Side 4.0 µs Source Side 250 ns Internal register hold time, SCL to SDA Source Side 0 µs T(buf) Internal register bus free time between STOP and START Source Side 4.7 µs tsu(2) Internal register setup time, SCL to START Source Side 4.7 µs th(2) Internal register hold time, START to SCL Source Side 4.0 µs tsu(3) Internal register hold time, SCL to STOP Source Side 4.0 µs 3.3 V VCC R L = 2 kW PULSE GENERATOR D.U.T. CL = 100 pF RT VIN VOUT Figure 10. Source Side Test Circuit (SCL_SOURCE, SDA_SOURCE) 5V VCC R L = 2 kW PULSE GENERATOR D.U.T. CL = 400 pF RT VIN VOUT Figure 11. Sink Side Test Circuit (SCL_SINK,SDA_SINK) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 15 SN75DP139 SLLS977 – APRIL 2009...................................................................................................................................................................................................... www.ti.com 5V SCL_SINK SDA_SINK Input 1.6 V 0.1 V tPHL2 tPLH2 3.3 V 80% SCL_SOURCE SDA_SOURCE Output 1.6 V 20% VOL tf2 Figure 12. Source Side Output AC Measurements 3.3 V SCL_SOURCE SDA_SOURCE Input 1.6 V 0.1 V tPHL1 5V 80% SCL_SINK SDA_SINK Output 1.6 V 20% VOL tf1 Figure 13. Sink Side Output AC Measurements 3.3 V SCL_SOURCE SDA_SOURCE Input VOL tPLH1 SCL_SINK SDA_SINK Output 5V 1.6 V Figure 14. Sink Side Output AC Measurements Continued TMDS and Main link pins The main link inputs are designed to support DisplayPort 1.1 specification. The TMDS outputs of the SN75DP139 are designed to support the Digital Video Interface (DVI) 1.0 and High Definition Multimedia Interface (HDMI) 1.3 specifications. The differential output voltage swing can be fine tuned with the RVsadj resistor. 16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 SN75DP139 www.ti.com...................................................................................................................................................................................................... SLLS977 – APRIL 2009 ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN AVCC = 3.3 V, RT = 50 Ω, VOH Single-ended HIGH level output voltage VOL Single-ended LOW level output voltage VSWING Single-ended output voltage swing VOC(SS) Change in steady-state common-mode output voltage between logic states VOD(PP) Peak-to-Peak output differential voltage V(O)SBY Single-ended standby output voltage AVCC = 3.3 V, RT = 50 Ω, OE_N = High I(O)OFF Single-ended power down output current IOS Short circuit output current RINT Input termination impedance Vterm Input termination voltage TYP MAX UNIT AVCC–10 AVCC+10 mV AVCC–600 AVCC-400 mV 400 600 mV –5 5 mV 800 1200 mV AVCC–10 AVCC+10 mV 0V ≤ VCC ≤ 1.5 V, AVCC = 3.3 V, RT = 50Ω –10 10 µA See Figure 19 –15 15 mA 60 Ω 2 V 40 50 1 SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time 250 350 600 ps tPHL Propagation delay time 250 350 600 ps tR1 Rise Time (I2C_EN = HI, SRC = Hi-Z) 60 85 120 ps tF1 Fall Time (I2C_EN = HI, SRC = Hi-Z) 60 85 120 ps tR2 Rise Time (I2C_EN = Low, SRC = Hi-Z) 115 150 ps tF2 Fall Time (I2C_EN = Low, SRC = Hi-Z) 115 150 ps tR3 Rise Time (I2C_EN = HI, SRC = HI) 150 180 ps tF3 Fall Time (I2C_EN = HI, SRC = HI) 150 180 ps tR4 Rise Time (I2C_EN = HI, SRC = Low) 115 150 ps tF4 Fall Time (I2C_EN = HI, SRC = Low) 115 150 ps tR5 Rise Time (I2C_EN = Low, SRC = HI) 175 220 ps tF5 Fall Time (I2C_EN = Low, SRC = HI) 175 220 ps tR6 Rise Time (I2C_EN = Low, SRC = Low) 150 180 ps tF6 Fall Time (I2C_EN = Low, SRC = Low) 150 180 ps tSK(P) Pulse skew 8 15 ps tSK(D) Intra-pair skew 20 65 ps tSK(O) Inter-pair skew 20 100 ps tJITD(PP) Peak-to-peak output residual data jitter AVCC = 3.3 V, RT = 50Ω, dR=2.5Gbps, TMDS output slew rate (default). RVsadj = 4.02 kΩ (refer to Figure 18) 14 50 ps tJITC(PP) Peak-to-peak output residual clock jitter AVCC = 3.3 V, RT = 50Ω, f = 250 MHz TMDS output slew rate (default). RVsadj= 4.02 kΩ (refer to Figure 18) 8 30 ps AVCC=3.3 V, RT = 50 Ω, f = 1MHz, RVsadj = 4.02 kΩ Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 17 SN75DP139 SLLS977 – APRIL 2009...................................................................................................................................................................................................... www.ti.com VTERM 3.3V 50 Ω 50 Ω 50 Ω 50 Ω 0.5 pF D+ 100 pF VD+ Receiver VID D- 100 pF V D- Y Driver VY Z VOD = VY - VZ VOC = (VY + VZ) VID = VD+ - VDVICM = (VD+ + VD-) 2 VZ 2 Figure 15. TMDS Main Link Test Circuit 2.2 V VTERM VID 1.8 V VID+ VID(pp) 0V tPHL 80% 0V 20% tf VID- tPLH 80% VOD(pp) VOD 20% tr Figure 16. TMDS Main Link Timing Measurements VOC ΔVOC (SS) Figure 17. TMDS Main Link Common Mode Measurements 18 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 SN75DP139 www.ti.com...................................................................................................................................................................................................... SLLS977 – APRIL 2009 Avcc (4) (8) RT Data + Parallel BERT Data - Coax Coax SMA SMA RX +EQ SMA 600, 800 mV VPP Differential [No Pre-emphasis] (1) FR 4 PCB trace & AC coupling Caps Clk + Coax Clk - Coax SMA SN 75 DP 139 Coax Coax FR 4 PCB trace AVcc RT SMA RX +EQ TTP 2 Jitter Test Instrument (2,3) RT Coax OUT SMA Coax (6) (7) TTP 1 (5) OUT SMA SMA RT Jitter Test Instrument (2,3) TTP 4 TTP 3 1. The FR4 trace between TTP1 and TTP2 is designed to emulate 1-8" of FR4, AC coupling cap, connector and another 1-8" of FR4. Trace width - 4 mils. 2. All Jitter is measured at a BER of 10-9 3. Residual jitter reflects the total jitter measured at TTP4 minus the jitter measured at TTP1 4. AVCC = 3.3V 5. RT = 50Ω, 6. Jitter data is taken with SN75DP139 configured in the fastest slew rate setting(default) 7. Rvsadj = 4.02kΩ 8. The input signal from parallel BERT does not have any pre-emphasis. Refer to recommended operating conditions Figure 18. TMDS Jitter Measurements 50 W I OS Driver 50 W + 0 V or 3.6 V - Figure 19. TMDS Main Link Short Circuit Output Circuit Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 19 SN75DP139 SLLS977 – APRIL 2009...................................................................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS AVCC = 3.3 V, RT = 50Ω, RVsadj = 4.02 kΩ POWER DISSIPATION vs DATA RATE RESIDUAL JITTER OF 2.5 Gbps vs SUPPLY VOLTAGE 420 Peak-To-Peak Residual Data Jitter - ps 60 400 85°C 25°C 0°C Power - mW 380 85°C Slowest Edge Rate 360 340 0°C Slowest Edge Rate 320 25°C Slowest Edge Rate 55 50 0°C Slowest Edge Rate 45 85°C Slowest Edge Rate 40 35 85°C 30 25 25°C 20 0°C 300 0 0.5 1 1.5 2 Data Rate - Gbps 2.5 15 3 3 3.3 VCC - Supply Voltage - V Figure 20. Figure 21. RESIDUAL JITTER vs DATA RATE GAIN vs FREQUENCY 50 3.6 20 VID(PP) = 800 mV (Slowest Edge Rate) 45 VID(PP) = 600 mV (Slowest Edge Rate) 15 40 35 VID(PP) = 1000 mV (Slowest Edge Rate) 10 30 VID(PP) = 600 mV 25 20 15 Gain − dB Peak-To-Peak Residual Data Jitter - ps 25°C Slowest Edge Rate −5 −0 −5 VID(PP) = 800 mV 10 VID(PP) = 1000 mV −10 5 0 0.25 −15 0.75 1.25 1.75 Data Rate - Gbps 2.25 10 1000 10000 f − Frequency − MHz Figure 22. 20 100 Figure 23. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 SN75DP139 www.ti.com...................................................................................................................................................................................................... SLLS977 – APRIL 2009 TYPICAL CHARACTERISTICS (continued) AVCC = 3.3 V, RT = 50Ω VOD vs Vsadj VOD(pp) − Differential Output Voltage − mV 1300 VCC = 3.6 V 1200 VCC = 3.3 V 1100 1000 900 VCC = 3.0 V 800 700 600 3.5 4 4.5 5 5.5 6 6.5 VSadj Resistance − kΩ Figure 24. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 21 SN75DP139 SLLS977 – APRIL 2009...................................................................................................................................................................................................... www.ti.com APPLICATION INFORMATION DVI APPLICATION In DVI application case, it is recommended that between the SN75DP139 TMDS outputs (OUT_Dx) and a through hole DVI connector a series resistor placeholder is incorporated. This could help in case if there are signal integrity issues as well as help pass system level compliance. I2C INTERFACE NOTES The I2C interface can be used to access the internal memory of the SN75DP139. I2C is a two-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. The SN75DP139 works as a slave and supports the standard mode transfer (100 kbps) as defined in the I2C-Bus Specification. The basic I2C start and stop access cycles are shown in Figure 25. The basic access cycle consists of the following: • A start condition • A slave address cycle • Any number of data cycles • A stop condition SDA SDA SCL SCL Start Condition Stop Condition Figure 25. I2C Start and Stop Conditions GENERAL I2C PROTOCOL • • • • 22 The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 27. All I2C-compatible devices should recognize a start condition. The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 26). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 27) by pulling the SDA line low during the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a communication link with a slave has been established. The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary (See Figure 28 ). To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 28). This releases the bus and stops the communication link Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 SN75DP139 www.ti.com...................................................................................................................................................................................................... SLLS977 – APRIL 2009 with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address. SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 26. I2C Bit Transfer Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL From Master Clock Pulse for Acknowledgement START Condition Figure 27. I2C Acknowledge SCL SDA Acknowledge Slave Address Acknowledge Data Figure 28. I2C Address and Data Cycles During a read cycle, the slave receiver will acknowledge the initial address byte if it decodes the address as its address. Following this initial acknowledge by the slave, the master device becomes a receiver and acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from the slave, the not acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 29 and Figure 30. See Example – Reading from the SN75DP139 section for more information. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 23 SN75DP139 SLLS977 – APRIL 2009...................................................................................................................................................................................................... www.ti.com Figure 29. I2C Read Cycle Figure 30. Multiple Byte Read Transfer SLAVE ADDRESS Both SDA and SCL must be connected to a positive supply voltage via a pull-up resistor. These resistors should comply with the I2C specification that ranges from 2kΩ to 19kΩ. When the bus is free, both lines are high. The address byte is the first byte received following the START condition from the master device. The 7 bit address is factory preset to 1000000. Table 2 lists the calls that the SN75DP139 will respond to. Table 2. SN75DP139 Slave Address Fixed Address Read/Write Bit Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (R/W) 1 0 0 0 0 0 0 1 Sink Port Selection Register and Source Plug-In Status Register Description (Sub-Address) The SN75DP139 operates using a multiple byte transfer protocol similar to Figure 30. The internal memory of the SN75DP139 contains the phrase “DP-HDMI ADAPTOR<EOT>” converted to ASCII characters. The internal memory address registers and the value of each can be found in Table 3. During a read cycle, the SN75DP139 will send the data in its selected sub-address in a single transfer to the master device requesting the information. See the Example – Reading from the SN75DP139 section of this document for the proper procedure on reading from the SN75DP139. Table 3. SN75DP139 Sink Port and Source Plug-In Status Registers Selection Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 Data 44 50 2D 48 44 4D 49 20 41 44 41 50 54 4F 52 04 FF 24 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 SN75DP139 www.ti.com...................................................................................................................................................................................................... SLLS977 – APRIL 2009 EXAMPLE – READING FROM THE SN75DP139: The read operation consists of several steps. The I2C master begins the communication with the transmission of the start sequence followed by the slave address of the SN75DP139 and logic address of 00h. The SN75DP139 will acknowledge it’s presence to the master and begin to transmit the contents of the memory registers. After each byte is transferred the SN75DP139 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master. If an ACK is received the next byte of data will be transmitted. If a NACK is received the data transmission sequence is expected to end and the master should send the stop command. The SN75DP139 will continue to send data as long as the master continues to acknowledge each byte transmission. If an ACK is received after the transmission of byte 0x0F the SN75DP139 will transmit byte 0x10 and continue to transmit byte 0x10 for all further ACK’s until a NACK is received. The SN75DP139 also supports an accelerated read mode where steps 1–6 can be skipped. SN75DP139 Read Phase Step 1 0 I2C Start (Master) S Step 2 7 6 5 4 3 2 1 0 I2C General Address Write (Master) 1 0 0 0 0 0 0 0 Step 3 9 I2C Acknowledge (Slave) A Step 4 7 6 5 4 3 2 1 0 I2C Logic Address (Master) 0 0 0 0 0 0 0 0 Step 5 9 I2C Acknowledge (Slave) A Step 6 0 2 I C Stop (Master) P Step 7 0 2 I C Start (Master) S Step 8 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 1 2 I C General Address Read (Master) Step 9 9 I2C Acknowledge (Slave) A Step 10 I2C Read Data (Slave) 7 6 5 4 3 2 1 0 Data Data Data Data Data Data Data Data Where Data is determined by the Logic values Contained in the Sink Port Register Step 11 9 I2C Not-Acknowledge (Master) X Where X is an A (Acknowledge) or A (Not-Acknowledge) An A causes the pointer to increment and step 10 is repeated. An A causes the slave to stop transmitting and proceeds to step 12. Step 12 2 I C Stop (Master) 0 P Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): SN75DP139 25 PACKAGE OPTION ADDENDUM www.ti.com 14-Apr-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN75DP139RGZR ACTIVE QFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN75DP139RGZT ACTIVE QFN RGZ 48 250 CU NIPDAU Level-3-260C-168 HR Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN75DP139RGZR QFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 SN75DP139RGZT QFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75DP139RGZR QFN RGZ 48 2500 346.0 346.0 33.0 SN75DP139RGZT QFN RGZ 48 250 190.5 212.7 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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